CN216213418U

CN216213418U - Diode packaging structure

Info

Publication number: CN216213418U
Application number: CN202122400421.1U
Authority: CN
Inventors: 赵良; 陈松; 胡爱斌
Original assignee: Ruineng Semiconductor Technology Co ltd
Current assignee: Ruineng Weien Semiconductor Shanghai Co ltd
Priority date: 2021-09-30
Filing date: 2021-09-30
Publication date: 2022-04-05
Anticipated expiration: 2031-09-30

Abstract

The application discloses diode packaging structure, diode packaging structure includes: the connecting bottom plate comprises a conductive body, a first connecting column and a second connecting column, the conductive body is provided with a first surface, and the first connecting column and the second connecting column are connected with the first surface; the lead frame is connected to one end of the conductive body; the chip assembly comprises a first chip and a second chip, wherein the anode end of the first chip is connected with the first connecting column, the cathode end of the first chip is connected with the lead frame, the anode end of the second chip is connected with the second connecting column, and the cathode end of the second chip is connected with the lead frame; the packaging structure covers the first connecting column, the second connecting column and the chip assembly on one side of the first surface. According to the diode packaging structure provided by the embodiment of the application, a larger space is provided for the installation of the chip assembly, the application of the chip assembly with a larger size is realized, and one side of the conductive body is exposed to improve the heat dissipation effect.

Description

Diode packaging structure

Technical Field

The application relates to the technical field of semiconductors, in particular to a diode packaging structure.

Background

With the progress of technology and the development of informatics, the market demand for semiconductor devices is increasing. The semiconductor device needs to have good heat dissipation and stable and reliable connection, and needs to accommodate a chip assembly with a larger and larger volume, but products in the prior art often cannot provide a better solution.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a diode packaging structure, and a conductive body is designed to connect two chips, so that the heat dissipation effect is improved, and a larger space is provided for the installation of the chips.

In a first aspect, an embodiment of the present application provides a diode package structure, including: the connecting bottom plate comprises a conductive body, a first connecting column and a second connecting column, the conductive body is provided with a first surface, and the first connecting column and the second connecting column are connected with the first surface; the lead frame is connected to one end of the conductive body; the chip assembly comprises a first chip and a second chip, wherein the anode end of the first chip is connected with the first connecting column, the cathode end of the first chip is connected with the lead frame, the anode end of the second chip is connected with the second connecting column, and the cathode end of the second chip is connected with the lead frame; the packaging structure covers the first connecting column, the second connecting column and the chip assembly on one side of the first surface, and the output end of the lead frame extends out of one side of the packaging structure.

According to an aspect of the embodiments of the present application, the height of the first connection post is greater than the thickness of the first chip anode frame, and the height of the second connection post is greater than the thickness of the second chip anode frame.

According to an aspect of the embodiments of the present application, an orthographic projection of the first chip on the first surface completely covers an orthographic projection of the first connection post on the first surface, and an orthographic projection of the second chip on the first surface completely covers an orthographic projection of the second connection post on the first surface.

According to an aspect of an embodiment of the present application, a lead frame includes: the first pin, the second pin and the third pin are sequentially arranged along a first direction, and the input end of the first pin is connected with the cathode end of the first chip through a first copper sheet; the input end of the third pin is connected with the cathode end of the second chip through a second copper sheet; the input end of the second pin is connected with the conductive body.

According to an aspect of the embodiment of the present application, the first connection posts and the second connection posts are disposed on the first surface at intervals along the second direction, the first connection posts are disposed near the first pins in the first direction, and the second connection posts are disposed near the third pins in the first direction.

According to an aspect of an embodiment of the present application, the anode terminals of the first chip and the second chip are coated with a metal adhesive layer having a characteristic of being bondable with the solder material.

According to one aspect of an embodiment of the present application, the metal adhesion layer is a titanium-nickel-silver alloy layer.

According to an aspect of the embodiments of the present application, the first connection post and the second connection post are integrally formed with the conductive body.

According to an aspect of the embodiment of the present application, the first connection post and the second connection post are formed to protrude upward from the first surface of the conductive body.

According to the diode packaging structure of the embodiment of the application, the anode of the first chip and the anode of the second chip are simultaneously connected with the two chips through the conductive body, a larger space is provided for the installation of the chip assembly, the application of the chip assembly with a larger size can be realized, one side of the conductive body is completely exposed, and the heat dissipation effect is improved.

Drawings

Other features, objects, and advantages of the present application will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.

Fig. 1 is a schematic structural diagram of a diode package structure according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a connection substrate of a diode package structure according to an embodiment of the present disclosure;

FIG. 3 is a schematic cross-sectional view of the connection base as shown in FIG. 2;

fig. 4 is a schematic structural diagram of a first chip or a second chip of a diode package structure according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a chip assembly connection structure of a diode package structure according to an embodiment of the present disclosure;

FIG. 6 is an enlarged schematic view at A in FIG. 1;

fig. 7a to 7g are schematic views illustrating a manufacturing process of a diode package structure according to an embodiment of the present application;

fig. 8 is a schematic flowchart of a method for manufacturing a diode package structure according to an embodiment of the present disclosure.

Detailed description of the reference numerals

10. Connecting the bottom plate; 101. a conductive body; 102. a first connecting column; 103. a second connecting column; 104. a first surface;

20. a lead frame; 201. a first pin; 202. a second pin; 203. a third pin;

30. a chip assembly; 301. a first chip; 302. a second chip; 303. an anode frame; 304. a first copper sheet; 305. a second copper sheet; 306. a first solder paste; 307. a second solder paste; 308. third solder paste; 309. fourth solder paste; 310. fifth solder paste; 311. sixth solder paste;

40. and (7) packaging the structure.

Detailed Description

Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the utility model and are not to be construed as limiting the utility model. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.

Features and exemplary embodiments of various aspects of the present invention will be described in detail below. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

The embodiment of the application provides a diode packaging structure. The diode package structure according to the embodiment of the present application is described in detail below with reference to the accompanying drawings.

Referring to the drawings, fig. 1 is a schematic structural diagram of a diode package structure according to an embodiment of the present application, fig. 2 is a schematic structural diagram of a connection substrate 10 of the diode package structure according to an embodiment of the present application, and fig. 3 is a schematic cross-sectional structural diagram of the connection substrate 10 shown in fig. 2.

As shown in fig. 1 to 3, the diode package structure includes a connection base plate 10, a lead frame 20, a chip assembly 30, and a package structure. The connection base 10 includes a conductive body 101, a first connection post 102, and a second connection post 103. The conductive body 101 has a first surface 104, and the first connection post 102 and the second connection post 103 are connected to the first surface 104. The lead frame 20 is connected to one end of the conductive body 101. The chip assembly 30 includes a first chip 301 and a second chip 302. The anode terminal of the first chip 301 is connected to the first connection post 102, and the cathode terminal of the first chip 301 is connected to the lead frame 20. The anode terminal of the second chip 302 is connected to the second connection post 103, and the cathode terminal of the second chip 302 is connected to the lead frame 20. The package structure is disposed to cover the first connection post 102, the second connection post 103 and the chip assembly 30 at the side of the first surface 104, and the output terminal of the lead frame 20 protrudes from the side of the package structure 40.

According to the diode packaging structure of the embodiment of the application, the anode of the first chip 301 and the anode of the second chip 302 are simultaneously connected with the two chips through the conductive body 101, a larger space is provided for the installation of the chip assembly 30, the application of the chip assembly 30 with a larger size can be realized, one side of the conductive body 101 is completely exposed, and the heat dissipation effect is improved.

The conductive body 101 serves to connect the anode of the chip assembly 30 and provide a space for mounting the chip assembly 30, while also providing a heat dissipation function. The conductive body 101 may be square for ease of production and cutting. The conductive body 101 is usually made of a metal material, such as copper, which can conduct heat generated during the operation of the chip assembly 30 well, reduce the temperature inside the structure, and ensure normal operation.

The first connecting pillar 102 and the second connecting pillar 103 are columnar structures, and both the first connecting pillar 102 and the second connecting pillar 103 have conductivity. The first connection post 102 and the second connection post 103 may be made of a metal material, such as copper. Two ends of the first connection column 102 are respectively connected to the first battery cell and the conductive body 101, and two ends of the second connection column 103 are respectively connected to the second battery cell and the conductive body 101.

The lead frame 20 is a structure in which the connection terminals of the chip assembly 30 are led out, and is convenient to assemble and connect by making a plurality of leads into a frame-type structure, the number of leads being set according to the requirements of the chip assembly 30. The anodes of the two chips are simultaneously connected with the conductive body 101 through the structure and are led out through the lead frame 20, so that a common anode diode structure is formed. By adopting the structure, the chip assembly 30 can be conveniently installed, and the installation efficiency is improved.

In some embodiments of the present application, the chip assembly 30 is flip-chip mounted on the conductive body 101. Referring to fig. 4 to 6, the first chip 301 and the second chip 302 have an anode frame 303 protruding upward in the circumferential direction. Specifically, the height of the first connection post 102 is greater than the thickness of the anode frame 303 of the first chip 301, and the height of the second connection post 103 is greater than the thickness of the anode frame 303 of the second chip 302.

The anode end of the first chip 301 in this embodiment of the application is connected with the first connection post 102 through the flip-chip manner, and the anode end of the second chip 302 is connected with the second connection post 103 through the flip-chip manner, so that the structure realizes that the anode frame 303 of the first chip 301 and the conductive body 101 are arranged at an interval, and the anode frame 303 of the second chip 302 and the conductive body 101 are arranged at an interval. In order to smoothly assemble the anode terminal of the first chip 301 and the anode terminal of the second chip 302 with the conductive body 101, the anode frame 303 is prevented from contacting the conductive body 101, and a short circuit is prevented. The installation is facilitated, and the probability of short circuit caused by installation error is reduced.

In some embodiments of the present application, the orthographic projection of the first chip 301 on the first surface 104 completely covers the orthographic projection of the first connection post 102 on the first surface 104, and the orthographic projection of the second chip 302 on the first surface 104 completely covers the orthographic projection of the second connection post 103 on the first surface 104. The surface of the first chip 301 in contact with the first connecting post 102 is larger than the area of the end surface of the first connecting post 102, so that the anode frame 303 of the first chip 301 can be exposed in the mounting process, and short circuit caused by contact between the anode frame 303 of the first chip 301 and the first connecting post 102 is avoided. The second chip 302 is similar to the first chip, and will not be described herein.

In some embodiments of the present application, the lead frame 20 includes: the first pin 201, the second pin 202 and the third pin 203 are sequentially arranged along a first direction, and the input end of the first pin 201 is connected with the cathode end of the first chip 301 through a first copper sheet 304; the input end of the third pin 203 is connected with the cathode end of the second chip 302 through a second copper sheet 305; the input of the second pin 202 is connected to the conductive body 101.

In the above structure, the first chip 301 and the second chip 302 are respectively connected to the first lead 201 and the third lead 203 on both sides of the lead frame 20, so that the connection interval between the first chip 301 and the second chip 302 is longer, and the reliability and convenience of mounting are improved. In addition, the first chip 301 and the second chip 302 are respectively connected to the first copper sheet 304 and the second copper sheet 305, and the stability of connection and the surge capability of the chip can be improved through copper sheet connection, so that the stability of the diode structure is ensured.

In some embodiments of the present application, the first connecting posts 102 and the second connecting posts 103 are disposed on the first surface 104 at intervals along the second direction, and the first connecting posts 102 are disposed near the first leads 201 in the first direction, and the second connecting posts 103 are disposed near the second leads 202 in the first direction. The first direction and the second direction are mutually perpendicular directions in the same plane. According to the embodiment, the first connecting column 102 and the second connecting column 103 are arranged along the diagonal line of the conductive body 101, the chip assembly 30 is reasonably arranged, the space on the conductive body 101 can be better utilized, and the installation efficiency and the heat dissipation performance are improved.

In some embodiments of the present application, the anode terminals of the first chip 301 and the second chip 302 are coated with a metal adhesive layer, and the metal adhesive layer has a characteristic that the metal adhesive layer can be adhered with a welding material, so that the metal adhesive layer can be conveniently mounted.

In some embodiments of the present application, the metallic bonding layer is a titanium-nickel-silver alloy layer. The titanium-nickel-silver alloy has good adhesive property and conductivity, and can provide a good substrate for the flip of a semiconductor chip.

In some embodiments of the present application, the first connection post 102 and the second connection post 103 are integrally formed with the conductive body 101. The first connecting column 102 and the second connecting column 103 are integrally formed, so that the installation efficiency can be improved, and the installation process is simplified.

In some embodiments of the present application, the first connection post 102 and the second connection post 103 are formed to protrude upward from the first surface 104 of the conductive body 101.

An embodiment of the present application further provides a method for manufacturing a diode package structure, as shown in fig. 7a to 7g and fig. 8, which are schematic diagrams of a diode package structure provided in an embodiment of the present application during a manufacturing process, the method includes the following steps,

s1, the conductive body 101 is taken, and the first connection post 102 and the second connection post 103 are connected or formed on the first surface 104 of the conductive body 101 to form the connection base plate 10.

Here, the connection may be that the first connection post 102 and the second connection post 103 are directly welded on the conductive body 101, and here, the first connection post 102 and the second connection post 103 are integrally formed with the conductive body 101. For example, the first connection post 102 or the second connection post 103 protruding from the first surface can be formed on the surface of a metal conductor by half etching.

S2, the connection substrate 10 and the lead frame 20 are taken, and the lead frame 20 is connected to one end of the connection substrate 10.

S3, taking core wafer assembly 30, connecting the anode terminal of first chip 301 with first connecting stud 102, and connecting the anode terminal of second chip 302 with second connecting stud 103.

Specifically, the chip assembly 30 is connected to the conductive body 101 by dispensing a first solder paste 306 on the first connection stud 102 and a second solder paste 307 on the second connection stud 103.

S4, the cathode terminal of the first chip 301 is connected to the first lead 201 of the lead frame 20, and the cathode terminal of the second chip 302 is connected to the second lead 202 of the lead frame 20.

Specifically, the third solder paste 308 is dotted on the cathode end of the first chip 301, and the fourth solder paste 309 is dotted on the first lead 201, so that two ends of the first copper sheet 304 are respectively connected to the third solder paste 308 and the fourth solder paste 309. And dotting a fifth solder paste 310 at the cathode end of the second chip 302, dotting a sixth solder paste 311 on the third pin 203, and connecting the two ends of the first copper sheet 304 with the fifth solder paste 310 and the sixth solder paste 311 respectively.

S5, taking the package structure 40, covering the first connecting posts 102, the second connecting posts 103 and the chip assembly 30 on the first surface 104 side, and extending the output ends of the lead frame 20 from one side of the package structure.

In the method for manufacturing the diode package structure according to the embodiment of the present application, after the package structure 40 is assembled, baking is performed to cure all the solder paste, so as to improve the mounting efficiency.

In the method for manufacturing the diode package structure according to the embodiment of the present application, the anode end of the first chip 301 is connected to the first connection post 102 in a flip-chip manner, the anode end of the second chip 302 is connected to the second connection post 103 in a flip-chip manner, the anode frame 303 of the first chip 301 and the first surface 104 are spaced by a gap, and the anode frame 303 of the second chip 302 and the first surface 104 are spaced by a gap.

According to the diode packaging method, the conductive body 101 is arranged to connect the two chips at the same time, so that a larger space is provided for the installation of the chips, the application of the chips with larger sizes can be realized, and the heat dissipation effect is improved. Meanwhile, the method has the advantages of simple process flow, stable performance of the manufactured diode packaging structure and high transmission efficiency.

In accordance with the embodiments of the present application as described above, these embodiments are not exhaustive and do not limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.

Claims

1. A diode package structure, comprising:

the connecting bottom plate comprises a conductive body, a first connecting column and a second connecting column, the conductive body is provided with a first surface, and the first connecting column and the second connecting column are connected with the first surface;

the lead frame is connected to one end of the conductive body;

the chip assembly comprises a first chip and a second chip, wherein the anode end of the first chip is connected with the first connecting column, the cathode end of the first chip is connected with the lead frame, the anode end of the second chip is connected with the second connecting column, and the cathode end of the second chip is connected with the lead frame;

packaging structure covers first surface one side first spliced pole, second spliced pole and chip module set up, the output of lead frame is followed packaging structure's one side stretches out.

2. The diode package structure of claim 1, wherein the height of the first connection post is greater than the thickness of the first chip anode bezel, and the height of the second connection post is greater than the thickness of the second chip anode bezel.

3. The diode package structure of claim 2, wherein an orthographic projection of the first chip on the first surface completely covers an orthographic projection of the first connection post on the first surface, and an orthographic projection of the second chip on the first surface completely covers an orthographic projection of the second connection post on the first surface.

4. The diode package structure of claim 3, wherein the lead frame comprises: a first pin, a second pin and a third pin arranged along a first direction in sequence,

the input end of the first pin is connected with the cathode end of the first chip through a first copper sheet; the input end of the third pin is connected with the cathode end of the second chip through a second copper sheet; the input end of the second pin is connected with the conductive body.

5. The diode package structure of claim 4, wherein the first connection posts and the second connection posts are spaced apart from each other along a second direction on the first surface, and the first connection posts are disposed adjacent to the first leads in the first direction, and the second connection posts are disposed adjacent to the third leads in the first direction.

6. The diode package structure of claim 2, wherein the anode terminals of the first chip and the second chip are coated with a metal adhesive layer having a characteristic of being bondable with a solder material.

7. The diode package structure of claim 6, wherein the metal adhesion layer is a titanium-nickel-silver alloy layer.

8. The diode package structure of any one of claims 1 to 7, wherein the first and second connection posts are integrally formed with the conductive body.

9. The diode package structure of claim 8, wherein the first and second connection posts are upwardly protruding from the first surface of the conductive body.