CN216211000U - USB3.0 conversion circuit - Google Patents

Abstract

The utility model discloses a USB3.0 conversion circuit, which comprises a USB3.0 interface and a conversion chip for interface conversion, wherein the USB3.0 interface comprises a USB2.0 signal line, three groups of pairs of differential signal lines and four groups of conversion signal lines, the conversion chip converts each group of differential signal lines into four signals through the four groups of conversion signal lines, and the three groups of differential signal lines form one USB3.0 interface. The utility model improves the utilization efficiency of the interface, has reasonable design and simple structure, is convenient for production and manufacture, reduces the manufacturing cost, is more favorable for being used in mobile phones and tablet computers, and can meet the use requirement.

Description

USB3.0 conversion circuit

Technical Field

The utility model relates to the technical field of chips, in particular to a USB3.0 conversion circuit.

Background

Along with the development of science and technology and the improvement of living standard of people, more and more electronic products enter people's lives, and greatly enrich people's daily lives and bring convenience to people's work, the mobile phones or flat panel electric energy on the market at present basically only have one USB interface, and cannot simultaneously use a plurality of external devices, and the use of a plurality of USB interfaces in daily lives is more and more urgent, although there is a Chinese utility model patent with the authorization publication number of CN202189358U, a USB3.0 interface circuit and a multimedia terminal are disclosed, which comprises a USB3.0 interface, a conversion chip and a memory for storing conversion chip parameters, wherein the USB3.0 interface comprises 1 pair of first differential signal lines for sending signals to the conversion chip and at least 1 pair of second differential signal lines for receiving signals of the conversion chip, the conversion chip converts received USB3.0 data signals into SATA signals and transmits the SATA signals to a signal receiving end, the memory is connected with the conversion chip. Although the USB2.0 standard can be compatible at the same time, the efficiency of data transmission is improved, a memory needs to be provided, which not only increases the manufacturing difficulty and cost, but also is not good for use in a mobile phone and a tablet computer, so that an improvement on the prior art is needed.

Disclosure of Invention

Aiming at the defects in the prior art, the utility model provides the USB3.0 conversion circuit which is reasonable in design, simple in structure, convenient to produce and manufacture, capable of reducing the manufacturing cost, more favorable for being used in mobile phones and tablet computers and capable of meeting the use requirements.

In order to achieve the purpose, the technical scheme adopted by the utility model is as follows:

a USB3.0 conversion circuit comprises a USB3.0 interface and a conversion chip for interface conversion, wherein the USB3.0 interface comprises USB2.0 signal lines, three pairs of differential signal lines and four groups of signal lines, the conversion chip converts each pair of differential signal lines into four signals through the four groups of signal lines, and the three pairs of differential signal lines form one USB3.0 interface.

Preferably, the conversion chip is connected with a boost DCDC power supply circuit, an LDO power supply circuit and a power management chip power supply circuit, wherein the boost DCDC power supply circuit, the LDO power supply circuit and the power management chip power supply circuit are all electrically connected with the conversion chip.

Preferably, the type of the boost DCDC power supply circuit is SGM 6611C; the LDO power supply circuit adopts a linear voltage regulator of SGM2031-1.8YUDH4G/TR model; the power supply circuit of the power management chip is a power supply circuit of the power management chip of the high-pass platform.

Preferably, the boost DCDC power supply circuit is used for enabling a 5V power supply to use the boost DCDC power supply circuit, and the platform GPIO is connected with the EN control output of the DCDC; the LDO power supply circuit adopts a 3.3V external LDO power supply circuit; the power supply circuit of the power management chip is a 1.2V power supply circuit of the power management chip of the high-pass platform.

Preferably, a line concentration controller is arranged between the conversion chip and the boost DCDC power supply circuit.

Preferably, the type adopted by the line concentration controller is GL3523-QFN 76.

Preferably, the three pairs of differential signal lines include a first differential signal line, a second differential signal line, and a third differential signal line, the first differential signal line employs TXPE _ UP (SSTX-)/TXNE _ UP (SSTX +), the second differential signal line employs RXN _ UP (SSRX +)/RXP _ UP (SSRX +), the third differential signal line employs DM _ HUB (D +)/DP _ HUB (D-), and the first, second, and third differential signal lines tap out four signals through the four sets of tap-out signal lines.

Preferably, the four sets of outgoing signal lines include a first set of outgoing signal lines, a second set of outgoing signal lines, a third set of outgoing signal lines, and a fourth set of outgoing signal lines,

the first group of the outgoing signal lines is:

DM1/DP1,RXP_DS1/RXN_DS1,TXP_DS1/TXN_DS1；

the second group of the outgoing signal lines is:

DM2/DP2,RXP_DS2/RXN_DS2,TXP_DS2/TXN_DS2；

the third group of the turned-out signal lines is as follows:

DM3/DP3,RXP_DS3/RXN_DS3,TXP_DS3/TXN_DS3；

the fourth group of the turned-out signal lines is as follows:

DM4/DP4,RXP_DS4/RXN_DS4,TXP_DS4/TXN_DS4。

compared with the prior art, the utility model has the beneficial effects that:

the USB3.0 interface comprises a USB2.0 signal line, three groups of differential signal lines and four groups of output signal lines, wherein each group of differential signal lines is respectively output with four signals through the four groups of output signal lines by a conversion chip, and the three groups of differential signal lines form the USB3.0 interface.

Secondly, the mobile phone cover is reasonable in design, simple in structure, convenient to produce and manufacture, capable of reducing manufacturing cost, more beneficial to being used in mobile phones and tablet computers and capable of meeting use requirements.

Drawings

FIG. 1 is a circuit diagram of the present invention.

FIG. 2 is a schematic diagram of a circuit controlled by the conversion chip according to the present invention.

FIG. 3 is a schematic diagram of a boosted DCDC power supply circuit according to the present invention.

FIG. 4 is a schematic diagram of an LDO power supply circuit according to the present invention.

In the figure: 1, converting a chip; 2, a voltage boosting DCDC power supply circuit; 3, an LDO power supply circuit; 4, a line concentration controller; 11, three pairs of differential signal lines; 12, a first group of outgoing signal lines; 13, the second group turns out signal lines; 14, the third group turns out a signal line; and 15, the fourth group turns out the signal wire.

Detailed Description

In the description of the present invention, it should be noted that when an element is referred to as being "fixed" or "disposed" to another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

In the description of the present invention, it should be noted that the terms "center", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, or the orientations or positional relationships in which the products of the present invention are conventionally placed when used, and are merely used for convenience of describing and simplifying the description, but do not indicate or imply that the device or element to which the reference is made must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.

In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood, however, that the description herein of specific embodiments is only intended to illustrate the utility model and not to limit the scope of the utility model. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.

Referring to fig. 1 and 2, as shown in the figure, a USB3.0 conversion circuit includes a USB3.0 interface and a conversion chip 1 for interface conversion, where the USB3.0 interface includes USB2.0 signal lines (D +, D-, Vbus, and GND), three pairs of differential signal lines 11, and four sets of signal lines, and the conversion chip 1 respectively converts each pair of differential signal lines into four signals through the four sets of signal lines, and the three pairs of differential signal lines 11 form a USB3.0 interface. The utility model improves the utilization efficiency of the interface, has reasonable design and simple structure, is convenient to produce and manufacture, reduces the manufacturing cost, is more favorable for being used in mobile phones and tablet computers, can better meet the use requirement, is simultaneously downward compatible with USB2.0, has the transmission rate of a USB3.0 interface reaching 5Gbps, and is greatly improved compared with USB2.0480Mbps.

Further, as shown in fig. 1, fig. 2, fig. 3, and fig. 4, the conversion chip 1 is connected to the boost DCDC power supply circuit 2, the LDO power supply circuit 3, and the power management chip power supply circuit, wherein the boost DCDC power supply circuit 2, the LDO power supply circuit 3, and the power management chip power supply circuit are all electrically connected to the conversion chip 1, which is beneficial to implementing power supply of various circuits, and thus is more beneficial to the plugging of various interfaces. To be more specific, the boosted DCDC power supply circuit 2 is of a model number SGM6611C (saint nation microelectronics (beijing) gmbh), specifically, a 5V power supply is used by the boosted DCDC power supply circuit 2, a platform GPIO is connected to an EN control output of the DCDC, specifically, a pin 43 on the conversion chip 1 is connected to a pin VOUT on the boosted DCDC power supply circuit 2; the LDO power supply circuit 3 adopts a linear voltage regulator of SGM2031-1.8YUDH4G/TR model, 3.3V can be used for the external LDO power supply circuit 3, the LDO power supply circuit 3 can provide 300mA current at most, and particularly, the No. 43 pin on the conversion chip 1 is connected with the VOUT pin on the LDO power supply circuit 3; the power management chip power supply circuit is a power management chip power supply circuit of a high-pass platform, wherein the power supply is a power supply of the power management chip, and therefore the description is omitted one by one, and it is also described that the conversion chip 1 is connected with the power management chip power supply circuit through a SW pin, 1.2V uses the power management chip to supply power, and the conversion of three types of power supplies, namely 5V, 3.3V and 1.2V, can be realized through concrete, and then three types of power supplies are provided for power supply. It is to be noted that, the conversion chip 1 and the boost DCDC power supply circuit 2 are connected through the hub controller 4, wherein the hub controller 4 is of the model GL3523-QFN76, and the 20K resistor in the hub controller 4 is utilized, which is more favorable for the 5V power supply to use the boost DCDC power supply.

Further, as shown in fig. 1 and 2, the three pairs of differential signal lines 11 include a first differential signal line which uses TXPE _ UP (SSTX-)/TXNE _ UP (SSTX +), a second differential signal line which uses RXN _ UP (SSRX +)/RXP _ UP (SSRX-), a third differential signal line which uses DM _ HUB (D +)/DP _ HUB (D-), the first, second, and third differential signal lines switch out four signals through four sets of switch-out signal lines, the first differential signal line uses TXPE _ UP (SSTX-)/TXNE _ UP (SSTX +) and the second differential signal line uses RXN _ UP (SSRX +)/RXP (SSRX-) which all belong to differential signals, one set of differential pairs is used for transmitting signals, and the other set is used for receiving signals, so that full-duplex transmission is realized, and the USB3.0 signal transmission rate reaches 5 Gbps. To be further described, the four sets of outgoing signal lines include a first set of outgoing signal lines 12, a second set of outgoing signal lines 13, a third set of outgoing signal lines 14, and a fourth set of outgoing signal lines 15.

The first group of outgoing signal lines 12 is:

DM1/DP1,RXP_DS1/RXN_DS1,TXP_DS1/TXN_DS1；

the second group of outgoing signal lines 13 is:

DM2/DP2,RXP_DS2/RXN_DS2,TXP_DS2/TXN_DS2；

the third group of outgoing signal lines 14 is:

DM3/DP3,RXP_DS3/RXN_DS3,TXP_DS3/TXN_DS3；

the fourth group of outgoing signal lines 15 is:

DM4/DP4,RXP_DS4/RXN_DS4,TXP_DS4/TXN_DS4。

the conversion circuit converts four pairs of signals out of a signal wire DM _ HUB (D +)/DP _ HUB (D-), TXPE _ UP (SSTX-)/TXNE _ UP (SSTX +), RXN _ UP (SSRX +)/RXP _ UP (SSRX-) output by the platform respectively, and the conversion of multi-path USB interfaces is facilitated through the arrangement, so that a user can use each interface simultaneously, and the use requirement can be met more.

It is emphasized that, for the above-mentioned switching chip 1, there are 77 pins, and the pins are sequentially arranged from serial number 1 to pin 77, wherein the three pairs of differential signal lines 11 are from pin 65 to pin 76 disposed on the switching chip 1, the first group of outgoing signal lines 12 includes pin 58 to pin 64 disposed on the switching chip 1, the second group of outgoing signal lines 13 includes pin 12 to pin 19 disposed on the switching chip 1, the third group of outgoing signal lines 14 includes pin 20 to pin 26 disposed on the switching chip 1, and the fourth group of outgoing signal lines 15 includes pin 1 to pin 11 disposed on the switching chip 1, which is favorable for implementing switching out multiple USB interfaces, and a user can use each interface at the same time, and can further satisfy usage requirements. The circuit diagram of the control circuit from pin 39 to pin 57 on the conversion chip 1 is shown in fig. 2.

It should be noted that, although the above embodiments have been described herein, the utility model is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present patent.

Claims (8)

1. A USB3.0 conversion circuit, comprising a USB3.0 interface and a conversion chip (1) for interface conversion, characterized in that: the USB3.0 interface comprises a USB2.0 signal line, three groups of differential signal lines (11) and four groups of output signal lines, the conversion chip (1) respectively outputs four signals from each group of differential signal lines through the four groups of output signal lines, and the three groups of differential signal lines form the USB3.0 interface.

2. The USB3.0 conversion circuit of claim 1, wherein: conversion chip (1) is connected with step-up DCDC power supply circuit (2), LDO power supply circuit (3) and power management chip power supply circuit, wherein step-up DCDC power supply circuit (2), LDO power supply circuit (3) and power management chip power supply circuit all with conversion chip (1) adopts electric connection.

3. The USB3.0 conversion circuit of claim 2, wherein: the type of the boost DCDC power supply circuit (2) is SGM 6611C; the LDO power supply circuit (3) adopts a linear voltage regulator of SGM2031-1.8YUDH4G/TR model; the power supply circuit of the power management chip is a power supply circuit of the power management chip of the high-pass platform.

4. A USB3.0 conversion circuit as claimed in claim 3 wherein: the boost DCDC power supply circuit (2) is used for enabling a 5V power supply to use the boost DCDC power supply circuit (2), and a platform GPIO is connected with an EN control output of the DCDC; the LDO power supply circuit (3) adopts a 3.3V external LDO power supply circuit (3); the power supply circuit of the power management chip is a 1.2V power supply circuit of the power management chip of the high-pass platform.

5. A USB3.0 conversion circuit as claimed in claim 2 or 3 or 4 wherein: and a line concentration controller (4) is arranged between the conversion chip (1) and the boost DCDC power supply circuit (2).

6. The USB3.0 conversion circuit of claim 5, wherein: the type adopted by the line concentration controller (4) is GL3523-QFN 76.

7. The USB3.0 conversion circuit of claim 1, wherein: the three pairs of differential signal lines (11) include a first differential signal line, a second differential signal line, and a third differential signal line, the first differential signal line employs TXPE _ UP (SSTX-)/TXNE _ UP (SSTX +), the second differential signal line employs RXN _ UP (SSRX +)/RXP _ UP (SSRX-), the third differential signal line employs DM _ HUB (D +)/DP _ HUB (D-), and the first, second, and third differential signal lines relay four signals through the four sets of outgoing signal lines.

8. The USB3.0 conversion circuit of claim 7, wherein: the four groups of the outgoing signal lines comprise a first group of outgoing signal lines (12), a second group of outgoing signal lines (13), a third group of outgoing signal lines (14) and a fourth group of outgoing signal lines (15),

the first group of outgoing signal lines (12) is:

DM1/DP1,RXP_DS1/RXN_DS1,TXP_DS1/TXN_DS1；

the second group of outgoing signal lines (13) is:

DM2/DP2,RXP_DS2/RXN_DS2,TXP_DS2/TXN_DS2；

the third group of outgoing signal lines (14) is:

DM3/DP3,RXP_DS3/RXN_DS3,TXP_DS3/TXN_DS3；

the fourth group of outgoing signal lines (15) is:

DM4/DP4,RXP_DS4/RXN_DS4,TXP_DS4/TXN_DS4。

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