CN216162609U

CN216162609U - Linear rectifier

Info

Publication number: CN216162609U
Application number: CN202121837381.0U
Authority: CN
Inventors: 许其罗
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2021-08-06
Filing date: 2021-08-06
Publication date: 2022-04-01
Anticipated expiration: 2031-08-06

Abstract

The utility model provides a linear rectifier, comprising an amplifying stage; having first and second input terminals for amplifying a differential input signal to provide a first drive voltage on an output terminal; a driver stage having a control terminal connected to an output terminal of the amplifier stage to receive the first drive voltage to provide a rectified output voltage on the output terminal, wherein the differential input signal comprises a reference signal on the first input terminal and a feedback signal of the rectified output voltage on a second input terminal; and a variable zero-pole compensation circuit for providing a zero frequency that varies with the load on the output terminal to compensate for pole frequency variations of the rectified output voltage.

Description

Linear rectifier

Technical Field

The present invention relates to rectifiers, and more particularly to linear rectifiers that can adapt to load variations to provide stable outputs.

Background

In a large scale integrated circuit (ASIC), electronic components and components therein need to be powered, for example, to provide a dc operating voltage, while the load of a digital circuit therein generally has a large variation range, and therefore a rectifier is generally required to provide a relatively stable dc voltage to the digital circuit. However, conventional rectifiers can only provide an operating range with a limited current load range due to circuit loop stability problems.

Fig. 1 shows a conventional rectifier circuit schematic. As shown, the rectifier comprises a differential amplifier stage 100, a driver stage 200 and a frequency compensation circuit 300, wherein the amplifier stage 100 is formed by a differential amplifier EA, receives a differential input signal formed by a reference voltage Vref and a feedback voltage Vfb of an output voltage at an output terminal OUT of the rectifier, and the differential input signal is amplified and then provided to a control terminal of the driver stage for driving the amplifier stage 200 formed by a power MOS transistor MNpass. The drain of MNpass is connected to the driving power supply Vss, the source is connected to ground through resistors R1 and R2, and resistors R1 and R2 serve as a voltage divider to provide the feedback signal vfb for the amplifier stage EA. The source terminal of MNpass provides the output voltage Vout for driving the Load as the output terminal OUT of the overall rectifier. In such a rectifier circuit, two poles are usually formed at the output terminal of the amplifier EA and the output terminal OUT of the driver stage MNpass, which causes the possibility of self-oscillation of the EA output and a reduction in the output capability of the driver stage, for example, as a reduction in the rectified voltage output Vout, especially when the output load of the rectifier circuit varies.

In order to obtain a stable rectified output voltage Vout, a compensation circuit is usually introduced in the rectifier, whose zero is used to cancel a pole in the rectifier circuit design. A common frequency compensation strategy is to introduce a zero and the frequency of this zero is the frequency of the pole at the output OUT, thereby eliminating the pole formed at the output OUT of the rectifier. Therefore, as shown in fig. 1, the frequency compensation circuit 300 including the capacitor C0 and the resistor R0 is connected in series between the output terminal of the amplifier EA and the ground, so that the zero frequency f can be generated by the capacitor C0 and the resistor R0₀Wherein the zero frequency f₀Can be determined by the following formula:

however, it can be seen that the frequency compensation circuit formed by R0 and C0 can only provide a fixed zero frequency f₀And therefore can only accommodate smaller variations in load, and for larger variations in load current, for example, when charging a load such as a battery using a rectified voltage output, smaller charging currents may be required during the beginning and end of charging, and intermediate stages of chargingThe large current is required to charge, so the load variation range is large, which is represented by the pole frequency f on the output end OUT_pThe variation is large. The following equations (2) and (3) show the pole frequency f_pAnd the load current I_outThe relationship of (1):

wherein

Wherein R is_outIs the output impedance at the output terminal OUT, C_outλ is the channel length coefficient of MNpass, and I is the capacitance of the external capacitor connected to the output terminal OUT_outRepresenting the load current at the output terminal OUT. It can be seen that the pole frequency at the output OUT increases with the load (i.e. the load current I)_outIncrease) and increase. The fixed zero frequency f provided by the compensation circuit 300(R0, C0)₀Situations may occur where insufficient compensation for dynamic poles due to load variations occurs, thus resulting in the rectifier shown in fig. 1 not providing a stable charging voltage when load variations are large.

Furthermore, for the case of a sudden load change, such as a load current change from 0 to several tens of ma in a few nanoseconds, the dynamic response of the rectifier shown in fig. 1 is not fast enough, mainly due to the bandwidth constraints of the EA amplifier and the fact that the voltage change at the output OUT cannot be fed back to the input Vfb of the amplifier quickly.

Disclosure of Invention

The present invention provides an improved rectifier circuit that compensates for pole variations in the rectified output by tracking the pole frequency variations within the rectifier and providing a dynamic zero frequency to provide a stable power output.

According to an aspect of the present invention, there is provided a linear rectifier including: an amplifier stage having first and second input terminals for amplifying a differential input signal to provide a first drive voltage at an output terminal; a driver stage having a control terminal receiving the first drive voltage to provide a rectified output voltage on the output terminal, wherein the differential input signal comprises a reference signal on the first input terminal and a feedback signal of the rectified output voltage on the second input terminal; wherein the rectifier further comprises a variable zero-pole compensation circuit for providing a zero frequency that varies with the load on the output terminal to compensate for the pole frequency of the rectified output voltage.

According to the rectifier of the more preferred embodiment of the utility model, the dynamic response of the rectifier can be further improved, so that the stable rectified output can be provided in response to the change of the load current more quickly.

Drawings

FIG. 1 shows a schematic diagram of a prior art rectifier circuit;

FIG. 2 shows an improved rectifier configuration schematic of an example of the present invention;

FIG. 3 illustrates an exemplary circuit diagram of the rectifier shown in FIG. 2;

FIG. 4 shows a schematic diagram of another example improved rectifier circuit;

fig. 5 shows a schematic diagram of another exemplary improved rectifier circuit.

In the drawings, like reference numerals refer to like parts.

Detailed Description

The following describes embodiments of the present invention in detail with reference to the accompanying drawings. While the preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[ zero-pole frequency tracking ]

Fig. 2 shows a schematic diagram of a rectifier according to an example of the utility model. As shown, the rectifier includes an amplification stage 100, a driving stage 200, and a variable zero-pole compensation circuit 300'. As described above in connection with fig. 1, the amplifying stage 100 is configured to amplify a differential signal pair formed by the reference signal vref and the feedback signal Vfb from the rectified output voltage Vout and provide the amplified signal to the driving stage 200, thereby controlling the driving stage 200 to provide the rectified output voltage Vout with enhanced driving capability.

The variable zero-pole compensation circuit 300' is configured to be responsive to load variations occurring at the output of the driver stage 200, such as load variations at the rectified output causing the output pole frequency of the rectifier to change. The variable zero-pole compensation circuit 300' forms a variable zero frequency f with the capacitor by introducing a variable resistor_ZThe magnitude is still calculated as shown in equation (1). Because the variable resistor is adjusted by the load size of the rectifier, a dynamic variable resistor which can respond to the load change is formed. When the load current increases, the output resistance decreases and the pole frequency increases. If the resistance corresponding to the zero introduced at this time is also reduced due to the increase of the load current, the corresponding zero frequency at this time will keep the same direction as the pole frequency change. Similarly, when the load current of the rectifier is reduced, the output resistance is increased, the pole frequency is reduced, and if the resistance of the zero compensation is also increased along with the reduction of the load circuit, the change of the zero frequency and the change of the pole frequency keep the same direction. Finally a variable zero is implemented to compensate for the dynamically varying pole on the rectifier output OUT. As mentioned before, the pole frequency f at the output can be manifested due to load variations_pThus by a dynamically adaptive zero frequency f_ZThe pole at the output can be eliminated, thereby enhancing the rectifier output stability.

In the example shown in fig. 2, the output voltage V of the amplifier stage 100 is due to the rectified output voltage Vout being fed back to the input of the amplifier stage 100_EAThe variation represents a variation of the voltage Vout due to the output voltage V_EAFor controlling the driver stage 200, the zero-pole compensation circuit 300' can thus, in one example, dynamically adjust the zero frequency of the compensation network by detecting output load changes of the driver stage 200. As shown in FIG. 2, the circuit 300' includes a detection circuit 301 and a capacitive circuitA circuit 302, wherein the detection circuit 301 detects a load current of the driver stage and provides an equivalent variable resistance R controlled by the load current. The capacitive circuit 302 is coupled between the variable resistor R and the output of the amplifier stage 100, thereby exploiting the variable zero frequency f provided by the zero-pole compensation circuit 300_ZFrequency f of opposite pole_pCompensation is performed. Fig. 3 shows a detailed circuit schematic diagram of an implementation of a zero-pole compensation circuit 300' according to an example of the present invention.

As shown in fig. 3, the driver stage 200 includes a power MOS transistor MNpass, which is connected to the rectified output terminal OUT through a source terminal, and the voltage Vout at the output terminal OUT provides a negative feedback signal Vfb to the differential amplifier EA through a voltage divider network (R1, R2). The zero-pole compensation circuit 300' includes an internal compensation capacitor Cc and provides a load-dependent variable resistance R-R_MN4Wherein R is_MN4Is the impedance across the drain-source of the MOS transistor MN 4. From the foregoing, it can be seen that the zero frequency f is compensated for in order to better cancel the dynamic pole at the output end_zShould also correspond to the corresponding pole frequency f_pRather, namely:

f_p＝f_z＝1/(2π*R_MN4*Cc) (4)

combining the equations (2), (3) and (4), it can be known that R is controlled by the load current or the output voltage Vout_MN4So that R is_MN4Proportional to the output impedance Rout at OUT. Accordingly, in order to make the introduced zero frequency equal to the pole frequency, when the equivalent zero resistance is proportional to the output resistance during the adjustment period, the capacitance of the introduced compensation capacitor can be reduced in equal proportion to the external capacitor Cout. The structure and operation of the zero-pole compensation circuit 300' are explained in detail below.

The zero-pole compensation circuit 300' includes three pairs of mirror circuits MIR₁(MNpass，MNsense)、MIR₂(MP1, MP2) and MIR₃ A detection circuit 301 composed of (MN3, MN4) and a capacitor C_CThe capacitive circuit 302 is formed, in this example C_CThe capacitance can be a low capacitance value of 1pF to 5F.

As shown in fig. 3, the same type of N-type detection MOS transistor MNse as the driving power transistor MNpass is usednse form a mirror image circuit MIR together with the MNpass of the driving power tube₁Wherein the gate control terminals of MNsense and MNpass are connected together, while the source terminals are also connected to each other and to the rectifier output terminal OUT, the drain terminal of MNpass is connected to the supply voltage Vss, the mirror circuit MIR₁Has a mirror scale factor alpha and outputs a mirror current through the drain terminal of MNsense

By means of a mirror circuit MIR₁Sampling the load current of the power tube MNpass and amplifying the load current by alpha times, i.e. outputting

Here I_MNpassThe source output current represents MNpass. Electric current

Supplied to the mirror circuit MIR through the MNsense drain₂And the charge circuit is used for charging the grid control ends of the MP1 and the MP 2.

Mirror image circuit MIR₂Consists of two P-type MOS transistors MP1 and MP2, wherein the sources of MP1 and MP2 are connected to Vss, and the gate and drain of MP1 are connected together and respectively connected to the gate of MP2 and the drain of MNsense for receiving the mirror image output current

And outputs a mirror current through the drain of the MP2

For mirror image circuit MIR₃. Mirror image circuit MIR₂Is designed to have a mirror scale factor beta, so that the output mirror current

Mirror image circuit MIR₃By N type MOS tubeMN3 and MN4, wherein the sources S of MN3 and MN4 are grounded, and the gates and drains of MN3 are connected together and respectively connected to the gates G and the drains of MP2 of MN4, so as to receive the mirror image output current

And charges the gate G of MN 4. As shown, drain D of MN4 is via compensation capacitor C_CConnected to the output of the differential amplifier, the voltage between its drain-source is zero since no current flows into drain D of MN 4. Therefore, in the mirror circuit MIR₃At the gate terminal of MN4, mirror current

Driven to generate a working voltage V between the gate and the source_GSResistance R between drain D-source S of MN4_MN4Operating in a variable linear resistance region in which a resistance R between a drain D and a source S_MN4The resistance value is controlled by the gate-source voltage V_GS. According to the operating characteristics of MOS transistor, in the variable resistance region, when V is_GSAt a certain time, the resistance R between the drain D and the source S_MN4Remain unchanged and are different from V_GSWill result in different resistance values R_MN4. The utility model utilizes the characteristic that the MOS transistor MN4 can work in a variable resistance region, so that the resistance R between the drain and the source of the MN4_MN4And a capacitor C_CForm a dynamic zero-pole compensation circuit in which R is due to_MN4To be connected with V_GSControl is changed, and V_GSAnd charging current

Is dependent on and thus is dependent on the output current I of the driver stage MNpass_MNpassRelated, the zero-pole compensation circuit thus provides a zero frequency f that can be varied in response to load changes_Z. In a mirror circuit MIR₃When the mirror ratio of (2) is γ, although no mirror current is generated between the drain and the source of MN4, the resistance R between the drain D and the source S_MN4Is still affected by the mirror ratio y, where R_MN4The following relationship exists with the output impedance Rout:

the zero-pole compensation circuit operation is described below in conjunction with fig. 3. When the load of the output OUT on the driver stage MNpass increases, for example, a larger current I is required_outWhen outputting, according to the above formulas (2) and (3), the resistor R will be outputted at the output terminal OUT_outReduced, corresponding pole frequency f_pVariable resistance R, increased while provided by MN4_MN4And correspondingly reduced, zero frequency f_zAnd (4) increasing. And then zero frequency tracking pole frequency is realized, and zero pole offset is ensured.

For mirror circuit MIR₁Because the two N-type MOS tubes MNpass and MNsense share the same grid and source, namely, have the same grid-source voltage, the mirror current amplified by alpha times is generated on the output end of the mirror circuit, namely the MNsense drain

Mirror current

Into a mirror circuit MIR₂The gates of the P-type MOS transistors MP1 and MP2 are charged, so that a mirror current amplified by β times is output at the output terminal of the mirror circuit, i.e., the drain of MP2

Mirror current

Into a mirror circuit MIR₃The gates of the N-type MOS transistors MN3 and MN4 are charged. Since there is no current in MN4, the drain-source voltage drop of MN4 is zero, so that the current is mirrored

Under the action of (3), the drain-source electrode of MN4 works in the variable resistance region of the MOS tube, and the drain-source electrode can work asVariable resistance R_MN4The variable resistor R_MN4Forming a resistive portion of the variable zero-pole compensation circuit 300'. According to the variable resistance region characteristic of the MOS transistor, when the gate-source voltage V of MN4_GSWhen increased, the resistance R between drain and source_MN4The variation rule is determined by the manufacturing material and process of the MOS transistor.

As shown, is composed of a capacitor C_CAnd a variable equivalent resistance R_MN4The zero-pole compensation circuit is connected between the gate control terminal of MNpass and ground, so that the zero frequency f is generated as shown in the formula (1)_ZIs represented as follows:

when the load becomes large, because of R_MN4And R_OUTThe circuit has a fixed linear relation, the zero frequency is increased in proportion to the pole frequency, and the zero frequency is still equivalent to the pole frequency, so that the pole is offset by the zero, and the stable voltage output by the rectifier circuit is ensured.

On the other hand, when the load on the output of the rectifier becomes smaller, although the pole frequency f_pWill drop, compensating for the resistance R of the network_MN4An increase in equal proportion means an equal proportional decrease in the zero frequency. And further ensure that the zero frequency can track the change of the pole frequency well.

[ dynamic response improvement ]

In order to improve the dynamic load response of the rectifier, the utility model improves the rectifier from the front and back ends of the amplifier stage EA, and improves the response by improving both the feedback speed at the input end and the processing delay of the amplifier EA at the output end. For ease of illustration, fig. 4 illustrates a portion of a rectifier circuit showing a delay compensation circuit 400 for improving dynamic response, as shown in phantom. As shown, the delay compensation circuit 400 includes a front-end compensation circuit, in this example a feedback capacitor C1, connected between the output terminal OUT of the rectifier and the negative feedback input Vfb of the amplifier stage EA. Since the capacitor voltage has a characteristic of not being abruptly changed, when the voltage Vout at the output terminal OUT varies, it can be quickly fed back to the negative input terminal Vfb. In this example, although capacitor C1 is shown to feed back the output quickly, the utility model may be implemented using any other circuit.

Another improvement is that the delay compensation circuit 400 further includes a back-end compensation circuit for compensating for the processing delay due to EA by rapidly charging the gate of MNpass to thereby increase the output response of the driver stage MNpass to compensate for the dynamic response degradation caused by the processing delay of EA. To this end, as shown in fig. 4, a back-end compensation circuit including a mirror circuit formed of MN1 and MN2 (hereinafter referred to as MIR) is connected between the EA amplifier output terminal and the gate control terminal of MNpass₄) And MP3 and MP4 form another mirror circuit (hereinafter referred to as MIR)₅)。

In a mirror circuit MIR₄The drain of MN1 is connected with the gate and the gate of MN2, and the drain of MN1 and the drain of MN2 are both connected with the power supply Vss. In a mirror circuit MIR₅The drain of MP3 is connected to the gate of MP4, and the drains of MP3 and MP4 are both connected to ground. In addition, current sources ib1 and ib2 are provided at the drains of the MOS transistors MN1 and MP3 to provide a reference operating current to provide a bias voltage for the MOS transistors MN1 and MP 3. The source of MN1 and the source of MP3 are coupled to the EA amplifier output at node gate 1. Here, in order to match the EA amplifier with the MOS transistors MN1 and MP3, a buffer is further connected to the circuit, and the source of MN1 and the source of MP3 receive the output of the amplifier EA through the buffer. In addition, the MN2 and the MP4 are also arranged into a push-pull circuit, and the sources of the MN2 and the MP4 are connected to the GATE terminal GATE of the power MOS transistor MNpass. Therefore, by using the rear-end compensation circuit, when the output load changes, the charging and discharging speed of the GATE end GATE end of the MNpass can be increased (namely, the voltage V between the GATE end and the source end of the MNpass is shortened)_GSChange time) to improve the response time of MNpass and achieve the aim of improving dynamic response.

For example, a larger current I is required when the load on the output terminal OUT becomes larger_outWhen outputting, the output voltage Vout will be caused to be lowerDrop, due to the action of the feedback capacitor C1, rapidly causes the feedback voltage Vfb at the negative input of the amplifier EA to drop, so that the output voltage V of the EA amplifier_EARaised, i.e. voltage V on node gate1_gate1Will rise. Due to the mirror image circuit MIR₄Middle MN1 is configured as a source follower, so voltage V_gate1The increase results in gate voltages V of MN1 and MN2_G-MNRises accordingly, and accordingly the source output voltage V of MN2_S-MN2Will rise. At the same time, in the mirror circuit MIR₅The middle MP3 is configured as a source follower at a voltage V_gate1Under the condition of increasing, the gate voltages V of MP3 and MP4_G-MPWill also rise accordingly, causing the source output voltage V of MP4_S-MP4Will increase, thereby increasing, the source output voltage V of MN2_S-MN2Superposition occurs so that the voltage V at the gate terminal of MNpass_GATE＝V_S-MN2+V_S-MP4. And conventionally only using the EA amplifier output V_EA(＝V_gate1) Compared with the charging of the GATE GATE of MNpass directly, the charging voltage V provided by the back-end compensation circuit_GATEGreater than V_gate1Therefore, the charging speed of the grid of the MNpass is increased, and the response time of the MNpass to the load increase is improved.

Similarly, when the load on the output terminal OUT becomes small, the output voltage Vout will be caused to rise, and therefore the feedback voltage Vfb on the negative input terminal of the amplifier EA will be caused to rise, so that the output voltage V of the EA amplifier_EAFalling, i.e. voltage V on node gate1_gate1Will drop. Thereby resulting in gate voltages V of MN1 and MN2_G-MNDecreases accordingly, and accordingly the source output voltage V of MN2_S-MN2Will drop. At the same time, at a voltage V_gate1Under the condition of falling, the gate voltages V of MP3 and MP4_G-MPWill also drop accordingly, causing the source output voltage V of MP4_S-MP4Will drop, due to the superposition, at the gate terminal voltage V of MNpass_GATEThe falling amplitude is V_S-MN2+V_S-MP4. And conventionally only using the EA amplifier output V_gate1Direct gate charging of MNpass is compared due to V at this time_GATELarger descent (V)_S-MN2+V_S-MP2) Far less than V_gate1Therefore, the discharge speed of the grid electrode of the MNpass is accelerated, and the response time of the MNpass to the load reduction is improved.

Fig. 5 shows a rectifier circuit improved in both the improvement of the dynamic response and the zero-pole compensation frequency, which combines the circuits shown in fig. 3 and 4, and as shown, in addition to the amplifier stage EA and the driver stage MNpass, the rectifier circuit further includes a delay compensation circuit including a front-end compensation circuit (in this case, a feedback capacitor C1) connected between the output terminal OUT of the rectifier and the negative feedback input terminal of the amplifier stage EA, and a back-end compensation circuit coupled between the output terminal of the amplifier stage EA and the control terminal of MNpass for compensating for the processing delay due to the amplifier EA by rapidly charging/discharging the gate of the MNpass, thereby improving the output response of the driver stage MNpass. The back-end compensation circuit comprises N-type MOS tubes MN1 and MN2, and P-type MOS tubes MP3 and MP4, wherein MN1 and MN2, and MP3 and MP4 respectively form mirror circuits, and MN2 and MP4 form a push-pull circuit. The zero-pole compensation circuit comprises an MNsense, (MP1, MP2), (MN3, MN4) and a capacitor Cc, wherein (MP1, MP2), (MN3, MN4) and MNsense and MNpass respectively form a mirror circuit, the sensing of load change is realized by detecting the current change on the source electrode of the MNpass, and the variable resistance value R between the drain and the source of the MN4 is adjusted_MN4And outputs a zero frequency that varies with the pole frequency variation on the output terminal, thereby eliminating the pole frequency. The operation modes of the delay compensation circuit and the zero-pole compensation circuit in the rectifier circuit system are the same as those of the circuits shown in fig. 3 and 4, and therefore, the description thereof is omitted.

While the utility model has been shown and described in detail in the drawings and in the preferred embodiments, the utility model is not limited to the embodiments disclosed, and those skilled in the art will appreciate that various combinations of the above-described embodiments can be made into further embodiments of the utility model and that such embodiments are within the scope of the utility model.

Claims

1. A linear rectifier, comprising:

an amplifier stage having first and second input terminals for amplifying a differential input signal to provide a first drive voltage at an amplifier stage output terminal;

a driver stage having a control terminal receiving the first drive voltage to provide a rectified output voltage on a rectified output terminal, wherein the differential input signal comprises a reference signal on the first input terminal and a feedback signal of the rectified output voltage on the second input terminal;

characterized in that the rectifier further comprises:

a variable zero-pole compensation circuit for providing a zero frequency that varies with a load on the rectified output to compensate for a pole frequency of the rectified output voltage.

2. The linear rectifier of claim 1, wherein said zero-pole compensation circuit comprises:

a detection circuit for detecting a change in a load current of the driver stage to provide a variable resistance, wherein a resistance value of the variable resistance is indicative of the load change;

a first capacitor coupled between the variable resistor and the amplifier stage output.

3. The linear rectifier of claim 2, wherein said detection circuit comprises:

a first mirror circuit for detecting a change in a load current of the driver stage to provide a first mirror signal having a first mirror amplification ratio;

a second mirror circuit for amplifying the first mirror signal at a second mirror amplification ratio to provide the variable resistor having a variable resistance value.

4. The linear rectifier of claim 3, further comprising at least a third mirror circuit connected between said first mirror circuit and said second mirror circuit for further amplifying said first mirror signal at a third mirror amplification ratio to form a second mirror signal,

wherein the second mirror circuit amplifies the second mirror signal at the second mirror amplification ratio to provide the variable resistance.

5. The linear rectifier of claim 4,

the driving stage comprises a power MOS tube,

the first mirror image circuit comprises a detection MOS tube and a power MOS tube, wherein the grid electrode and the source electrode of the detection MOS tube and the power MOS tube are connected with each other, and the first mirror image signal is output at the drain electrode end of the detection MOS tube;

the third image circuit comprises a first MOS tube and a second MOS tube, wherein the grid electrodes of the first MOS tube and the second MOS tube and the drain electrode of the first MOS tube are connected to the drain electrode of the detection MOS tube to receive the first image signal, the drain electrode of the second MOS tube provides the second image signal, and the source electrodes of the first MOS tube and the second MOS tube are connected to a power supply;

the second mirror image circuit comprises a third MOS tube and a fourth MOS tube, wherein the grid electrodes of the third MOS tube and the fourth MOS tube and the drain electrode of the third MOS tube are connected to the drain electrode of the second MOS tube to receive the second mirror image signal, and the drain electrode of the second MOS tube is connected to the first capacitor so that the drain electrode-source electrode of the second MOS tube forms the variable resistor.

6. The linear rectifier of any one of claims 1-5, further comprising a delay compensation circuit for providing delay compensation to the amplifier stage in response to the load change.

7. The linear rectifier of claim 6, wherein said delay compensation circuit comprises: a front end compensation circuit connected between the rectified output of the driver stage and the second input of the amplifier stage for coupling voltage variations of the rectified output voltage to the second input.

8. The linear rectifier of claim 7, wherein said delay compensation circuit further includes a back-end compensation circuit coupled between said amplifier stage and a driver stage for providing a second drive voltage greater than or less than said first drive voltage to a control terminal of said driver stage during said load change,

wherein the back-end compensation circuit provides a second driving voltage greater than the first driving voltage when the load increases and provides a second driving voltage less than the first driving voltage when the load decreases.

9. The linear rectifier of claim 8,

the front end compensation circuit comprises a second capacitor connected between the rectification output end and the second input end;

the back-end compensation circuit includes:

the fourth mirror image circuit comprises a fifth MOS tube and a sixth MOS tube, wherein the grid electrode and the drain electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube are connected to a power supply, the source electrode of the fifth MOS tube is connected to the output end of the amplification stage, and the source electrode of the sixth MOS tube is connected to the control end of the driving stage;

the fifth mirror image circuit comprises a seventh MOS tube and an eighth MOS tube, wherein the grid electrode and the drain electrode of the seventh MOS tube are connected with the grid electrode of the eighth MOS tube, the source electrode of the seventh MOS tube is connected to the output end of the amplification stage, the source electrode of the eighth MOS tube is connected to the control end of the driving stage, and the drain electrode of the eighth MOS tube is grounded;

the sixth MOS tube and the eighth MOS tube form a push-pull circuit, and the push-pull circuit is used for outputting the second driving voltage to the control end of the driving stage at the source electrodes of the sixth MOS tube and the eighth MOS tube.