CN216160998U

CN216160998U - Program-controlled timing device

Info

Publication number: CN216160998U
Application number: CN202122147850.2U
Authority: CN
Inventors: 不公告发明人
Original assignee: Beijing Hanchen Dongyuan Technology Co ltd
Current assignee: Beijing Hanchen Dongyuan Technology Co ltd
Priority date: 2021-09-08
Filing date: 2021-09-08
Publication date: 2022-04-01
Anticipated expiration: 2031-09-08

Abstract

The utility model provides a program-controlled timing device. The clock control circuit comprises a filter circuit for inputting signals from outside, a clock control circuit for outputting timing signals, and a central processing unit (MCU) for programming the time of the output signals of the clock control circuit; the signal comparison circuit is used for processing the high-speed low-power push-pull output signal; and the voltage stabilizing circuit is used for providing stable electric energy for the clock control circuit and the central processing unit MCU. The circuit adopts a programmable clock control circuit with timing interrupt output, the electric quantity consumption is extremely low during dormancy, the problem of large power consumption of a common timing circuit is thoroughly solved, thereby realizing the extremely high-speed receiving and decoding capacity in a low-power mode, the power is as low as 35uA, one-time energy supply can be realized, the normal operation can be continued for at least 10s, the timing value of a timer can be set in an extremely short time under the condition of reducing the dependence of a module on a power supply, and the application scene of the device is greatly expanded.

Description

Program-controlled timing device

Technical Field

The utility model belongs to the technical field of electronics, and particularly relates to a program-controlled timing device.

Background

In the current society, the electronic automation and semiconductor technology are rapidly developed, more and more automatic monitoring equipment is available, the original manual monitoring or control work is replaced, and the monitoring accuracy and the working efficiency are greatly improved. Currently, automated monitoring equipment is almost ubiquitous, such as video monitoring, power monitoring, safety monitoring in the engineering field, and is growing at a geometric rate. With economic development and social progress, miniaturization and high performance of electric appliances become a development trend. At present, although many electrical appliances have intelligent functions such as timing, the electrical appliances are generally expensive, large in size, large in power consumption and poor in performance, how to optimize a timing circuit, so that the electrical appliances are miniaturized, low in cost and high in performance, the application fields of the electrical appliances are greatly expanded, and the electrical appliances become a great research make internal disorder or usurp direction of various electrical appliance manufacturers.

Energy conservation and environmental protection are subjects of development of all industries at present, and the current common practice for energy conservation and consumption reduction is to adopt two low-power consumption timing modules embedded in or externally embedded in a control chip to realize management, namely, after the electronic product finishes normal work (high-power consumption mode), the electronic product immediately enters a sleep state (low-power consumption mode), and after the timing time passes, the electronic product exits from the sleep state and enters the normal work state again, so that the energy conservation and consumption reduction to the maximum extent are realized. Most of low-power-consumption implementation schemes of electronic products on the market are in a 1mA level, or the timing precision of a timing module is insufficient, so that the specific requirements of specific occasions cannot be met. In addition, the existing intelligent timing device is fixedly installed on certain equipment, can only be fixed in an embedding mode and cannot be moved, and the trouble that different equipment is required to be provided with a timing function and the movement is inconvenient exists. Therefore, the technical field urgently needs to develop an intelligent timing device which can accurately time and output with low power consumption.

SUMMERY OF THE UTILITY MODEL

In view of the technical problems in the prior art, the present invention aims to provide a program-controlled timing device. The device adopts a programmable clock control circuit with timing interrupt output, the electric quantity consumption is extremely low during dormancy, the problem of large power consumption of a common timing circuit is thoroughly solved, the power is as low as 35uA, energy is given once, and the normal work can be continued for at least 10s, thereby realizing the extremely high-speed decoding and receiving capability in a low-power-consumption mode, and setting the timing value of a timer in an extremely short time under the condition of reducing the dependence of a module on a power supply.

In order to achieve the purpose, the utility model adopts the following technical scheme:

a program control timing device is characterized by comprising a filter circuit for inputting signals from outside, a clock control circuit for outputting timing signals, and a central processing unit (MCU) for programming and controlling the response state of the clock control circuit for outputting the timing signals; the signal comparison circuit is used for processing the high-speed low-power push-pull output signal; and the voltage stabilizing circuit is used for providing stable electric energy for the clock control circuit and the central processing unit MCU.

Preferably, the filter circuit of the external input signal comprises capacitors C2, C3 and C4, resistors R2, R3 and R9, signal input terminals J1, J3 and J5, signal output terminals J2, J4, J6, J7, J8, J9 and J10; the signal input terminal J1 includes pins 1, 2, 3, 4, 5, and 6; the signal input terminal J2 comprises pins 1, 2, 3, 4, 5 and 6, the signal input terminal J3 comprises pins 1, 2, 3, 4, 5 and 6, the signal output terminal J4 comprises pins 1, 2, 3, 4 and 5, and the signal input terminal J5 comprises pins 1, 2, 3, 4 and 5; pin 1 of the signal input terminal J1 is connected to pin 1 of the signal output terminal J2; pin 1 of the signal output terminal J2 is connected with one end of pin 1, C12 and D2 of the signal input terminal J3, and the other ends of C12 and D2 are grounded; pin 2 of signal input terminal J1 is grounded; pin 3 of the signal input terminal J1 is simultaneously connected with one end of C2, R2 and C3; pin 4 of the signal input terminal J1 is connected to the other ends of C2 and R2 and one end of C4 and R3; the other ends of the C4 and the R3 are connected with the ground; the other end of the C3 is connected with one end of the R9; the other end of R9 is connected with pin 2 of signal output terminal J4; pin 2 of the signal input J4 is connected to pin 2 of the signal input J5.

Preferably, the clock control circuit for outputting the timing signal includes a chip U2(C8051F411), a silicon oscillator chip U3, a resistor R7, R8, R13, a capacitor C8, C9, C10, C11, and C16, and the chip U2 includes

pins

1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, and 29; the chip U2 pin 22 is a Cnvstr pin, and the chip U3 comprises pins 1, 2, 3, 4 and 5; the model of the chip U3 is MAX7377, and a pin 1 of the chip U2 is connected with one end of R8 and J9; pins 2, 7 and 28 of U2 are connected with the other end of R8, one end of J10 and C16, pins 4 and 5 of U3 and pin 2 of J5; pin 3 of U2 connects to pins 1, J7 of U3; pins 4 and 14 of U2 are floating; pin 6 of U2 is connected to one end of C9 and C11; pin 8 of U2 connects to pin 1 of U4;

pins

5, 9, 10, 11, 12, 13, 15, 25, 26, 29 of U2 are grounded; pins 16, 17, 18, 19, 20 and 21 of U2 are connected with the other end of C9 and the ground; pin 22 of U2 is connected to the other end of R13; pins 23 and 24 of U2 are connected to one end of C15, the other end of R11 and pin 5 of U4; pin 27 of U2 is connected to J6; pin 2 of chip U3 is connected to J8; pin 3 of chip U3 is connected to ground.

Preferably, the voltage stabilizing circuit for providing stable electric energy for the clock control circuit and the central processing unit MCU comprises a voltage stabilizing chip U1, a capacitor C1, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C10, a capacitor C12, a resistor R1, a capacitor R5, a capacitor R6, a capacitor R8, a PNP chip triode D1, a voltage stabilizing diode D2, and a thyristor Q1; the chip U1 includes pins 1, 2 and 3; the voltage stabilizing chip U1 is XC6266P332MR IN model, a pin 1 of the chip U1 is an IN pin, the thyristor Q1 comprises an anode, a cathode and a control electrode, the PNP patch triode D1 is BAS316 IN model, the voltage stabilizing diode D2 is BZX84-C18 IN model, and the pin 1 of the U1 is connected with 3.3V power supply and one end of C6; pin 2 of U1 is connected to pin 2 of J3, one end of C6, C7, R5, C13, the negative pole of C5 and the cathode of Q1; the pin 3 of U1 is connected with the pin 1 of J3, the anode of D1, the other end of C13 and the anode of C5; the control electrode of Q1 is connected with one end of R6; the anode of Q1 is connected with the cathode of C1; pin 6 of J3 is connected to the positive pole of C1; the pin 5 of J3 is connected with the other ends of R5, R6 and C7; pins 3, 4 of J3 are connected to the 3.3V supply.

Preferably, when the pin IN of the XC6206P332MR chip outputs high level or the anode node output of the thyristor is high level and the pin Cnvstr of the C8051F411 chip outputs high level, the anode and the cathode of the thyristor are conducted; when the IN pin of the XC6206P332MR chip outputs low level or the anode node output of the thyristor is low level and the Cnvstr pin of the C8051F411 chip outputs low level, the anode and the cathode of the thyristor are disconnected;

preferably, the IN pin of the XC6206P332MR chip outputs high level or the anode node output of the silicon controlled thyristor is high level, and the Cnvstr pin of the C8051F411 chip outputs high level, which can be realized by the C8051F411 chip connected to the Cnvstr pin.

Preferably, the signal comparison circuit for high-speed low-power push-pull output signal processing comprises a signal processing chip U4, resistors R10, R11 and R12 and a capacitor C15, wherein the chip U4 comprises pins 1, 2, 3, 4 and 5; the signal processing chip has a U4 model of TLV3201, and pin 2 of U4 is grounded; pin 3 of U4 is connected to the other end of R12 and one end of R10, R11; the other end of the R10 is grounded, the pin 4 of the U4 is connected with the other end of the R4, and the other end of the C15 is grounded; pin 2 of J5 is connected to one end of R4.

Preferably, the voltage stabilizing chip U1 is connected with the Q1 to realize disposable narrow pulse large current output.

Preferably, the C8051F411 chip is connected to the signal processing chip U4, performs dual-channel signal comparison, and realizes high output driving current by low offset voltage through rail-to-rail input, thereby realizing extremely high speed decoding capability in a low power consumption mode, and setting a timer value of a timer in an extremely short time under the condition of reducing the dependence of the module on a power supply.

Preferably, the central processing unit MCU is a singlechip C8051F 411;

the singlechip C8051F411 is connected to the silicon oscillator chip MAX7377 and is used for inputting low-power frequency switching of a timing parameter control circuit;

the singlechip C8051F411 is connected to the control electrode of the thyristor Q1 and is used for driving the node of the singlechip to input high level or low level so as to control the response state of the circuit.

The utility model has the following beneficial effects:

1. the program-controlled timing device adopts the programmable clock control circuit with timing interrupt output, has extremely low electric quantity consumption during dormancy, thoroughly solves the problem of large power consumption of a common monitoring module, saves electric energy to the maximum extent, saves cost and has no pollution.

2. The utility model can realize extremely high timing precision.

3. The utility model has extremely high-speed decoding and receiving capability, can set the timing value of the timer in extremely short time, and expands the application scene of the device.

Drawings

The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.

Fig. 1 shows a schematic representation of the inventive programmable timing device.

Detailed Description

In order to more clearly illustrate the utility model, the utility model is further described below with reference to preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the utility model.

As shown in fig. 1, in an embodiment of the present invention, a novel program-controlled timing device is provided, which includes a filter circuit for external input signals, a clock control circuit for outputting timing signals, and a central processing unit MCU for programming the time of the output signals of the clock control circuit; the signal comparison circuit is used for processing the high-speed low-power push-pull output signal; and the linear voltage stabilizing circuit is used for providing stable electric energy for the clock control circuit and the central processing unit MCU.

The filter circuit of the external input signal ensures the smoothness of the external input signal and the voltage and ensures the stability of a circuit system. The filter circuit of the external input signal comprises capacitors C2, C3 and C4, resistors R2, R3 and R9, signal input ends J1, J3 and J5, and signal output ends J2, J4, J6, J7, J8, J9 and J10; the signal input terminal J1 includes pins 1, 2, 3, 4, 5, and 6; the signal input terminal J2 comprises pins 1, 2, 3, 4, 5 and 6, the signal input terminal J3 comprises pins 1, 2, 3, 4, 5 and 6, the signal output terminal J4 comprises pins 1, 2, 3, 4 and 5, and the signal input terminal J5 comprises pins 1, 2, 3, 4 and 5; pin 1 of the signal input terminal J1 is connected to pin 1 of the signal output terminal J2; pin 1 of the signal output terminal J2 is connected with one end of pin 1, C12 and D2 of the signal input terminal J3, and the other ends of C12 and D2 are grounded; pin 2 of signal input terminal J1 is grounded; pin 3 of the signal input terminal J1 is simultaneously connected with one end of C2, R2 and C3; pin 4 of the signal input terminal J1 is connected to the other ends of C2 and R2 and one end of C4 and R3; the other ends of the C4 and the R3 are connected with the ground; the other end of the C3 is connected with one end of the R9; the other end of R9 is connected with pin 2 of signal output terminal J4; pin 2 of the signal input J4 is connected to pin 2 of the signal input J5.

The clock control circuit consists of a clock chip with a programmable function and a peripheral circuit and is used for outputting a timing signal; the clock control circuit is responsible for outputting high and low level signals to drive the silicon controlled thyristor to open and close when the timing time is up, thereby controlling the start and stop of the circuit. The clock control circuit for outputting the timing signals comprises a chip U2, a silicon oscillator chip U3, resistors R7, R8, R13 and capacitors C8, C9, C10, C11 and C16, wherein the chip U2 comprises

pins

1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28 and 29; the chip U2 pin 22 is a Cnvstr pin, and the chip U3 comprises pins 1, 2, 3, 4 and 5; the model of the chip U3 is MAX7377, and a pin 1 of the chip U2 is connected with one end of R8 and J9; pins 2, 7 and 28 of U2 are connected with the other end of R8, one end of J10 and C16, pins 4 and 5 of U3 and pin 2 of J5; pin 3 of U2 connects to pins 1, J7 of U3; pins 4 and 14 of U2 are floating; pin 6 of U2 is connected to one end of C9 and C11; pin 8 of U2 connects to pin 1 of U4;

pins

5, 9, 10, 11, 12, 13, 15, 25, 26, 29 of U2 are grounded; pins 16, 17, 18, 19, 20 and 21 of U2 are connected with the other end of C9 and the ground; pin 22 of U2 is connected to the other end of R13; pins 23 and 24 of U2 are connected with one end of C15, the other end of R11 and pin 5 of U4; pin 27 of U2 is connected to J6; pin 2 of chip U3 is connected to J8; pin 3 of chip U3 is connected to ground.

And the voltage stabilizing circuit is used for providing stable electric energy for the clock control circuit and the central processing unit MCU. The circuit comprises a voltage stabilizing chip U1, capacitors C1, C5, C6, C7, C10, C12, resistors R1, R5, R6, R8, a PNP patch triode D1, a voltage stabilizing diode D2 and a thyristor Q1; the chip U1 includes pins 1, 2 and 3; the voltage stabilizing chip U1 is XC6266P332MR IN model, a pin 1 of the chip U1 is an IN pin, the thyristor Q1 comprises an anode, a cathode and a control electrode, the PNP patch triode D1 is BAS316 IN model, the voltage stabilizing diode D2 is BZX84-C18 IN model, and the pin 1 of the U1 is connected with one end of a 3.3V power supply and C6; pin 2 of U1 is connected to pin 2 of J3, one end of C6, C7, R5, C13, the negative pole of C5 and the cathode of Q1; the pin 3 of U1 is connected with the pin 1 of J3, the anode of D1, the other end of C13 and the anode of C5; the control electrode of Q1 is connected with one end of R6; the anode of Q1 is connected with the cathode of C1; pin 6 of J3 is connected to the positive pole of C1; the pin 5 of J3 is connected with the other ends of R5, R6 and C7; pins 3, 4 of J3 are connected to the 3.3V supply.

And the central processing unit MCU is used for programming the time of the output signal of the clock control circuit or directly controlling the on-off state of the circuit by inputting a signal to the control circuit. The central processing unit MCU is a singlechip C8051F 411; the singlechip C8051F411 is connected to the silicon oscillator MAX7377 and is used for inputting the switching state of the timing parameter control circuit; the singlechip C8051F411 is connected to the control electrode of the thyristor Q1 and is used for driving the control electrode node to input high level or low level so as to control the switching state of the circuit.

In the utility model, the singlechip C8051F411 performs programming control on the clock control circuit, the singlechip C8051F411 also has an external digital interface, and a user can input control parameters through the external digital interface to realize self-defined automatic starting time control. And the MCU writes the next interrupt time into the timer interrupter chip after each start according to the timing parameter value under the action of the timing parameter. The MCU is connected with the control electrode of the thyristor Q1, and after the equipment is started, the MCU drives the control electrode node of the thyristor Q1 to output high level, control the closing state of the circuit and output low level to disconnect the switch of the control circuit when necessary.

IN the utility model, when the IN pin of the XC6206P332MR chip outputs high level or the anode node output of the silicon controlled thyristor is high level and the Cnvstr pin of the C8051F411 chip outputs high level, the anode and the cathode of the silicon controlled thyristor are conducted; when the IN pin of the XC6206P332MR chip outputs low level or the anode node output of the thyristor is low level and the Cnvstr pin of the C8051F411 chip outputs low level, the anode and the cathode of the thyristor are disconnected;

the IN pin of the XC6206P332MR chip outputs high level or the anode node of the thyristor outputs high level, and the Cnvstr pin of the C8051F411 chip outputs high level can be driven by the C8051F411 chip connected to the Cnvstr pin.

The signal processing circuit adopts a program control mode, realizes high output driving current by two-channel signal analysis, rail-to-rail input and low offset voltage, thereby realizing extremely high-speed receiving and decoding capability by a low-power consumption mode, realizing signal comparison of high-speed low-power consumption push-pull output signal processing, and setting a timing value of a timer in an extremely short time under the condition of reducing the dependence of a module on a power supply. The circuit comprises a signal processing chip U4, resistors R10, R11, R12 and a capacitor C15, wherein the chip U4 comprises pins 1, 2, 3, 4 and 5; the signal processing chip has a U4 model of TLV3201, and pin 2 of U4 is grounded; pin 3 of U4 is connected to the other end of R12 and one end of R10, R11; the other end of the R10 is grounded, the pin 4 of the U4 is connected with the other end of the R4, and the other end of the C15 is grounded; pin 2 of J5 is connected to one end of R4.

It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.

Other parts in this embodiment are the prior art, and are not described herein again.

Claims

1. A program control timing device is characterized by comprising a filter circuit for inputting signals from outside, a clock control circuit for outputting timing signals, and a central processing unit (MCU) for programming and controlling the response state of the clock control circuit for outputting the timing signals; the signal comparison circuit is used for processing the high-speed low-power push-pull output signal; and the voltage stabilizing circuit is used for providing stable electric energy for the clock control circuit and the central processing unit MCU.

2. The programmable timing device as claimed in claim 1, wherein the filter circuit of the external input signal comprises capacitors C2, C3 and C4, resistors R2, R3 and R9, signal input terminals J1, J3 and J5, and signal output terminals J2, J4, J6, J7, J8, J9 and J10; the signal input terminal J1 includes pins 1, 2, 3, 4, 5, and 6; the signal input terminal J2 comprises pins 1, 2, 3, 4, 5 and 6, the signal input terminal J3 comprises pins 1, 2, 3, 4, 5 and 6, the signal output terminal J4 comprises pins 1, 2, 3, 4 and 5, and the signal input terminal J5 comprises pins 1, 2, 3, 4 and 5; pin 1 of the signal input terminal J1 is connected to pin 1 of the signal output terminal J2; pin 1 of the signal output terminal J2 is connected with one end of pin 1, C12 and D2 of the signal input terminal J3, and the other ends of C12 and D2 are grounded; pin 2 of signal input terminal J1 is grounded; pin 3 of the signal input terminal J1 is simultaneously connected with one end of C2, R2 and C3; pin 4 of the signal input terminal J1 is connected to the other ends of C2 and R2 and one end of C4 and R3; the other ends of the C4 and the R3 are connected with the ground; the other end of the C3 is connected with one end of the R9; the other end of R9 is connected with pin 2 of signal output terminal J4; pin 2 of the signal input J4 is connected to pin 2 of the signal input J5.

3. The programmable timing device of claim 2, wherein the clock control circuit for outputting the timing signal comprises a chip U2, a silicon oscillator chip U3, resistors R7, R8, R13, capacitors C8, C9, C10, C11, and C16, and the chip U2 comprises pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, and 29; the chip U2 pin 22 is a Cnvstr pin, and the chip U3 comprises pins 1, 2, 3, 4 and 5; the model of the chip U3 is MAX7377, and a pin 1 of the chip U2 is connected with one end of R8 and J9; pins 2, 7 and 28 of U2 are connected with the other end of R8, one end of J10 and C16, pins 4 and 5 of U3 and pin 2 of J5; pin 3 of U2 connects to pins 1, J7 of U3; pins 4 and 14 of U2 are floating; pin 6 of U2 is connected to one end of C9 and C11; pin 8 of U2 connects to pin 1 of U4; pins 5, 9, 10, 11, 12, 13, 15, 25, 26, 29 of U2 are grounded; pins 16, 17, 18, 19, 20 and 21 of U2 are connected with the other end of C9 and the ground; pin 22 of U2 is connected to the other end of R13; pins 23 and 24 of U2 are connected with one end of C15, the other end of R11 and pin 5 of U4; pin 27 of U2 is connected to J6; pin 2 of chip U3 is connected to J8; pin 3 of chip U3 is connected to ground.

4. The program-controlled timing device according to claim 3, wherein the voltage-stabilizing circuit for supplying stable power to the clock control circuit and the central processing unit MCU comprises a voltage-stabilizing chip U1, a capacitor C1, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C10, a capacitor C12, a resistor R1, a resistor R5, a resistor R6, a resistor R8, a PNP patch triode D1, a voltage-stabilizing diode D2, and a thyristor Q1; the chip U1 includes pins 1, 2 and 3; the voltage stabilizing chip U1 is XC6266P332MR IN model, a pin 1 of the chip U1 is an IN pin, the thyristor Q1 comprises an anode, a cathode and a control electrode, the PNP patch triode D1 is BAS316 IN model, the voltage stabilizing diode D2 is BZX84-C18 IN model, and the pin 1 of the U1 is connected with 3.3V power supply and one end of C6; pin 2 of U1 is connected to pin 2 of J3, one end of C6, C7, R5, C13, the negative pole of C5 and the cathode of Q1; the pin 3 of U1 is connected with the pin 1 of J3, the anode of D1, the other end of C13 and the anode of C5; the control electrode of Q1 is connected with one end of R6; the anode of Q1 is connected with the cathode of C1; pin 6 of J3 is connected to the positive pole of C1; the pin 5 of J3 is connected with the other ends of R5, R6 and C7; pins 3, 4 of J3 are connected to the 3.3V supply.

5. The program-controlled timing device as claimed in claim 4, wherein the signal comparison circuit for high-speed low-power push-pull output signal processing comprises a signal processing chip U4, resistors R10, R11 and R12, and a capacitor C15, wherein the chip U4 comprises pins 1, 2, 3, 4 and 5; the signal processing chip has a U4 model of TLV3201, and pin 2 of U4 is grounded; pin 3 of U4 is connected to the other end of R12 and one end of R10, R11; the other end of the R10 is grounded, the pin 4 of the U4 is connected with the other end of the R4, and the other end of the C15 is grounded; pin 2 of J5 is connected to one end of R4.

6. The program-controlled timing device according to claim 5, wherein when the IN pin of the XC6206P332MR chip outputs high level or the anode node output of the thyristor is high level and the Cnvstr pin of the C8051F411 chip outputs high level, the anode and the cathode of the thyristor are conducted; when the IN pin of the XC6206P332MR chip outputs low level or the anode node output of the thyristor is low level and the Cnvstr pin of the C8051F411 chip outputs low level, the anode and the cathode of the thyristor are disconnected.

7. The programmable timing device of claim 6, wherein the IN pin of the XC6206P332MR chip outputs high level or the anode node output of the silicon controlled thyristor is high level and the Cnvstr pin of the C8051F411 chip outputs high level, which can be both driven by the C8051F411 chip connected to the Cnvstr pin.

8. The program-controlled timing device as claimed in claim 7, wherein the voltage-stabilizing chip U1 is connected to the thyristor Q1 to realize a one-time narrow-pulse high-current output.

9. The program-controlled timing device according to claim 8, wherein a C8051F411 chip is connected to the signal processing chip U4, and performs dual-channel signal comparison, and realizes high output driving current with low offset voltage through rail-to-rail input, thereby realizing extremely high speed decoding and receiving capability with low power consumption mode, the power is as low as 35uA, one-time energy supply can last at least 10s normal operation, and the timing value of the timer can be set in extremely short time under the condition of reducing the dependence of the module on the power supply, thereby greatly expanding the application scenarios of the device.

10. The program-controlled timing device according to claim 9, wherein the central processing unit MCU is a single chip microcomputer C8051F 411;

the singlechip C8051F411 is connected to a control electrode of the thyristor Q1 and is used for driving a node of the singlechip to input high level or low level so as to control the response state of the circuit.