CN216160781U - Switch state detection circuit and switch state detection device - Google Patents
Switch state detection circuit and switch state detection device Download PDFInfo
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- CN216160781U CN216160781U CN202121166048.1U CN202121166048U CN216160781U CN 216160781 U CN216160781 U CN 216160781U CN 202121166048 U CN202121166048 U CN 202121166048U CN 216160781 U CN216160781 U CN 216160781U
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Abstract
The utility model provides a switch state detection circuit and a switch state detection device, wherein the switch state detection circuit comprises a first wiring port, a second wiring port, a first level conversion circuit, a second level conversion circuit and a processor, level signals output by the first level conversion circuit and the second level conversion circuit respectively represent the charged states of a first power supply end and a second power supply end of a switch to be detected, and a controller judges the switch state of the switch to be detected according to the received level signals, so that the current switch to be detected is in a closing state or a tripping state, and the reliability and the safety of load electricity utilization are improved.
Description
Technical Field
The utility model belongs to the technical field of switches, and particularly relates to a switch state detection circuit and a switch state detection device.
Background
At present, in an electric system, an air switch or a backup protection gate SCB is used for switching on and off a power supply in many occasions, the switch state needs to be acquired in real time in order to ensure that a load is electrified reliably, most of the switches have no remote signaling function, and therefore the switch cannot conveniently and timely detect whether the switch is in a tripping state or a closing state.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a switch state detection circuit, which aims to solve the problem that the switch state of a traditional switch cannot be detected due to the fact that the traditional switch has no remote signaling function.
A first aspect of embodiments of the present invention provides a switch state detection circuit, including a first connection port, a second connection port, a first level shift circuit, a second level shift circuit, and a processor, the signal input end of the first level switching circuit is respectively connected with a first power end and a zero line of the switch to be detected through the first wiring port, the signal output end of the first level conversion circuit is connected with the first signal end of the processor, the signal input end of the second level switching circuit is respectively connected with a second power supply end and a zero line of the switch to be detected through the second wiring port, the signal output end of the second level shift circuit is connected with the second signal end of the processor, a first power end and a second power end of the switch to be detected are connected in series with a live wire, and the live wire and the zero wire are used for transmitting an alternating current power supply;
the first level conversion circuit and the second level conversion circuit are used for converting the charged states of the first power supply end and the second power supply end of the switch to be detected into corresponding level signals respectively and outputting the level signals to the processor, so that the processor determines the switch state of the switch to be detected according to the level signals.
In one embodiment, the first level shift circuit includes a first buck rectifying circuit and a first voltage dividing circuit;
the power supply input end of the first voltage reduction rectification circuit is respectively connected with the first power supply end of the switch to be detected and the zero line through the first wiring port, the power supply output end of the first voltage reduction rectification circuit is connected with the power supply end of the first voltage division circuit, and the signal output end of the first voltage division circuit is connected with the first signal end of the processor;
the first voltage reduction and rectification circuit is used for carrying out voltage reduction and rectification conversion on the alternating current power supply between the first power end of the switch to be detected and the zero line and outputting a first low-voltage direct current power supply to the first voltage division circuit;
the first voltage division circuit is used for dividing the first low-voltage direct-current power supply and outputting a voltage signal representing high and low levels to the processor.
In one embodiment, the first step-down rectification circuit includes a first transformer, a first diode, and a first capacitor;
the primary side of the first transformer is connected with a first power end of the switch to be detected and the zero line through the first wiring port, the first end of the secondary side of the first transformer is connected with the anode of the first diode, the cathode of the first diode is connected with the first end of the first capacitor, the second end of the secondary side of the first transformer is connected with the second end of the first capacitor, and the first end and the second end of the first capacitor form a power output end of the first voltage reduction rectification circuit.
In one embodiment, the first voltage divider circuit includes a first resistor and a second resistor;
the first end of the first resistor is connected with the first end of the first capacitor, the second end of the first resistor and the first end of the second resistor are connected together to form a signal output end of the first voltage division circuit, and the second end of the second resistor is connected with the second end of the first capacitor.
In one embodiment, the first level shift circuit includes a second buck rectifying circuit and a second voltage dividing circuit;
the power supply input end of the second voltage reduction rectifying circuit is connected with a second power supply end of the switch to be detected and the zero line through the second wiring port respectively, the power supply output end of the second voltage reduction rectifying circuit is connected with the power supply end of the second voltage division circuit, and the signal output end of the second voltage division circuit is connected with a second signal end of the processor;
the second voltage reduction and rectification circuit is used for carrying out voltage reduction and rectification conversion on the alternating current power supply between the second power supply end of the switch to be detected and the zero line and outputting a second low-voltage direct current power supply to the second voltage division circuit;
and the second voltage division circuit is used for dividing the second low-voltage direct-current power supply and outputting a voltage signal representing high and low levels to the processor.
In one embodiment, the second buck rectifying circuit comprises a second transformer, a second diode and a second capacitor;
the primary side of the second transformer is connected with a second power supply end of the switch to be detected and the zero line through the second wiring port, the first end of the secondary side of the second transformer is connected with the anode of the second diode, the cathode of the second diode is connected with the first end of the second capacitor, the second end of the secondary side of the second transformer is connected with the second end of the second capacitor, and the first end and the second end of the second capacitor form a power supply output end of the second voltage reduction rectification circuit.
In one embodiment, the second voltage divider circuit includes a third resistor and a fourth resistor;
the first end of the third resistor is connected with the first end of the second capacitor, the second end of the third resistor and the first end of the fourth resistor are connected together to form a signal output end of the second voltage division circuit, and the second end of the fourth resistor is connected with the second end of the second capacitor.
In one embodiment, the first level shift circuit further comprises a first output filter circuit comprising a third capacitor;
the second level shift circuit further comprises a second output filter circuit, and the output filter circuit comprises a fourth capacitor;
the third capacitor is connected in parallel to two ends of the second resistor, and the fourth capacitor is connected in parallel to two ends of the fourth resistor.
In one embodiment, a first switch circuit is disposed in the first connection port, a second switch circuit is disposed in the second connection port, a first end of the first switch circuit is connected to the first power end and the zero line of the switch to be detected, a second end of the first switch circuit is connected to the signal input end of the first level conversion circuit, a first end of the second switch circuit is connected to the second power end and the zero line of the switch to be detected, a second end of the first switch circuit is connected to the signal input end of the second level conversion circuit, and controlled ends of the first switch circuit and the second switch circuit are respectively connected to the processor.
A second aspect of an embodiment of the present invention provides a switching state detection apparatus including the switching state detection circuit described above.
According to the utility model, the switch state detection circuit is composed of the first wiring port, the second wiring port, the first level conversion circuit, the second level conversion circuit and the processor, level signals output by the first level conversion circuit and the second level conversion circuit respectively represent the electrified states of the first power supply end and the second power supply end of the switch to be detected, and the controller judges the switch state of the switch to be detected according to the received level signals, so that whether the current switch to be detected is in a closing state or a tripping state is determined in real time, and the reliability and the safety of load electricity utilization are improved.
Drawings
Fig. 1 is a schematic diagram of a first structure of a switch state detection circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a second structure of the switch state detection circuit according to the embodiment of the present invention;
fig. 3 is a schematic diagram of a third structure of a switch state detection circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a fourth structure of the switch state detection circuit according to the embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the utility model and are not intended to limit the utility model.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
Fig. 1 shows a first structural schematic diagram of a switch state detection circuit according to a preferred embodiment of the present invention, and for convenience of description, only the relevant parts of the present embodiment are shown, and the detailed description is as follows:
in this embodiment, the switch state detection circuit includes a first connection port CN1, a second connection port CN2, a first level shift circuit 10, a second level shift circuit 20, and a processor 30, a signal input end of the first level shift circuit 10 is connected to a first power end and a zero line N of a switch K to be detected through a first connection port CN1, a signal output end of the first level shift circuit 10 is connected to a first signal end of the processor 30, a signal input end of the second level shift circuit 20 is connected to a second power end and a zero line N of the switch K to be detected through a second connection port CN2, a signal output end of the second level shift circuit 20 is connected to a second signal end of the processor 30, the first power end and the second power end of the switch K to be detected are connected in series to a live line L, and the live line L and the zero line N are used for transmitting an ac power;
the first level shift circuit 10 and the second level shift circuit 20 are configured to convert the charged states of the first power source terminal and the second power source terminal of the switch K to be detected into corresponding level signals respectively, and output the level signals to the processor 30, so that the processor 30 determines the switch state of the switch K to be detected according to the level signals.
In this embodiment, first connection port CN1 and second connection port CN2 are used for connecting to detect switch K, zero line N and the level converting circuit that corresponds, first connection port CN1 and second connection port CN2 can be reserved and set up, when it is necessary to treat to detect switch K and carry out the on-off state, directly connect the level converting circuit that corresponds with the connection port, when it is unnecessary to carry out the on-off state detection, the level converting circuit disconnection that corresponds will be connected, it is unnecessary to disconnect the power cord repeatedly on zero line N and live wire L, thereby satisfy different test demands and reduce work load.
When the switch K to be detected is in a closing state, the alternating current power supply flows through the switch K to be detected, the first power supply end and the second power supply end of the switch K to be detected are both electrified, at this time, the first level conversion circuit 10 and the second level conversion circuit 20 both output level signals representing electrification to the processor 30, and the processor 30 determines that the switch K to be detected is in the closing state at present according to the received level signals.
When the switch K to be detected is in the trip state, at least one power supply terminal of the switch K to be detected is uncharged, at this time, at least one of the first level conversion circuit 10 and the second level conversion circuit 20 outputs a level signal representing the uncharged state to the processor 30, and the processor 30 determines that the current switch K to be detected is in the trip state according to the received level signal.
The electrified level signal of the representation and the uncharged level signal of the representation are high and low levels, for example, the high level represents that the power supply end of the switch K to be detected is electrified, and the low level represents that the power supply end of the switch K to be detected is uncharged, and is specifically set correspondingly according to requirements.
The level conversion circuit can adopt a corresponding power conversion circuit, such as a rectification circuit, a voltage reduction circuit, a voltage stabilizing circuit and the like, and is specifically and correspondingly arranged according to requirements.
The processor 30 may be a single chip, a microprocessor, a central processing unit, or the like, and is configured according to the requirement.
According to the utility model, the first wiring port CN1, the second wiring port CN2, the first level conversion circuit 10, the second level conversion circuit 20 and the processor 30 are adopted to form the switch state detection circuit, level signals output by the first level conversion circuit 10 and the second level conversion circuit 20 respectively represent the charged states of the first power supply end and the second power supply end of the switch K to be detected, and the controller judges the switch state of the switch K to be detected according to the received level signals, so that the current switch K to be detected is determined to be in a closing state or a tripping state in real time, and the load electricity utilization reliability and safety are improved.
As shown in fig. 2, further, in order to meet different testing requirements, in an embodiment, a first switch circuit K1 is disposed in the first wiring port CN1, a second switch circuit K2 is disposed in the second wiring port CN2, a first end of the first switch circuit K1 is connected to a first power end and a neutral line N of the switch K to be tested, a second end of the first switch circuit K1 is connected to a signal input end of the first level shift circuit 10, a first end of the second switch circuit K2 is connected to a second power end and a neutral line N of the switch K to be tested, a second end of the first switch circuit K1 is connected to a signal input end of the second level shift circuit 20, and controlled ends of the first switch circuit K1 and the second switch circuit K2 are respectively connected to the processor 30.
When the switch state detection is needed, the processor 30 controls the first switch circuit K1 and the second switch circuit K2 to be turned on according to the trigger signal, the first level shifter circuit 10 and the second level shifter circuit 20 are respectively connected with the power supply terminal of the switch K to be detected through the first switch circuit K1 of the first wiring port CN1 and the second switch circuit K2 of the second wiring port CN2, and the processor 30 determines the current switch state of the switch K to be detected according to the received level signal.
When the switch state detection is not needed, the processor 30 controls the first switch circuit K1 and the second switch circuit K2 to be turned off according to another trigger signal, at the moment, the first level conversion circuit 10 and the second level conversion circuit 20 are disconnected with the switch K to be detected and the zero line N, and different test requirements can be adapted by setting the corresponding switch circuits.
Meanwhile, the corresponding switch circuit is equipped, the switch state detection circuit can be reserved, for example, the switch state detection circuit can be integrated with the switch K to be detected, so that when the switch K to be detected is debugged or installed in construction, the switch K to be detected and the switch state detection circuit can be installed in the corresponding power supply loop as an integral structure, extra wiring is not needed, and different testing requirements are met.
Wherein, first switch circuit K1 and second switch circuit K2 can adopt structures such as relay, circuit breaker, specifically correspond the setting according to the demand.
In one embodiment, as shown in fig. 3, the first level shift circuit 10 includes a first step-down rectifying circuit 11 and a first voltage dividing circuit 12;
the power supply input end of the first step-down rectifying circuit 11 is respectively connected with a first power supply end and a zero line N of the switch K to be detected through a first wiring port CN1, the power supply output end of the first step-down rectifying circuit 11 is connected with the power supply end of the first voltage division circuit 12, and the signal output end of the first voltage division circuit 12 is connected with a first signal end of the processor 30;
the first step-down rectifying circuit 11 is used for performing step-down rectifying conversion on an alternating current power supply between a first power supply end of the switch K to be detected and the zero line N, and outputting a first low-voltage direct current power supply to the first voltage division circuit 12;
the first voltage dividing circuit 12 is configured to divide the first low-voltage dc power supply and output a voltage signal representing a high level and a low level to the processor 30.
The first level shift circuit 10 includes a second step-down rectifying circuit 21 and a second voltage dividing circuit 22;
the power supply input end of the second voltage-reducing rectifying circuit 21 is respectively connected with a second power supply end of the switch K to be detected and the zero line N through a second wiring port CN2, the power supply output end of the second voltage-reducing rectifying circuit 21 is connected with the power supply end of the second voltage-dividing circuit 22, and the signal output end of the second voltage-dividing circuit 22 is connected with a second signal end of the processor 30;
the second step-down rectifying circuit 21 is used for performing step-down rectifying conversion on the alternating current power supply between the second power supply end of the switch K to be detected and the zero line N, and outputting a second low-voltage direct current power supply to the second voltage division circuit 22;
the second voltage dividing circuit 22 is configured to divide the second low-voltage dc power supply and output a voltage signal representing a high or low level to the processor 30.
In this embodiment, when the switch K to be detected is switched on and the front end power supply device normally works, the first step-down rectification circuit 11 and the second step-down rectification circuit 21 respectively receive the ac power through the first wiring port CN1 and the second wiring port CN2, the first step-down rectification circuit 11 and the second step-down rectification circuit 21 perform step-down rectification conversion, and respectively output the first low-voltage dc power and the second low-voltage dc power to the voltage dividing circuit at the rear end, the corresponding voltage dividing circuit then outputs a voltage signal with a certain voltage value to the processor 30, at this time, the processor 30 receives a high level with a certain voltage value, and the processor 30 determines that the switch K to be detected is in a switched-on state in the present.
When the switch K to be detected trips and the front-end power supply device works normally, one of the first buck rectifying circuit 11 and the second buck rectifying circuit 21 does not receive the alternating current power supply, if the first power end of the switch K to be detected is the power input end and the second power end of the switch K to be detected is the power output end, the first buck rectifying circuit 11 receives the alternating current power supply and the second buck rectifying circuit 21 does not receive the alternating current power supply, or vice versa, at this time, one of the voltage division circuits outputs a voltage signal with a certain voltage value to the processor 30, the processor 30 receives a high level, the other voltage division circuit does not output a voltage signal, the processor 30 receives a low level, and the processor 30 can determine that the switch K to be detected is in a trip state currently according to the received high and low levels.
The first buck rectifying circuit 11 and the second buck rectifying circuit 21 may adopt a rectifying circuit, a buck circuit, etc., as shown in fig. 4, in one embodiment, the first buck rectifying circuit 11 includes a first transformer T1, a first diode D1, and a first capacitor C1;
the primary side of a first transformer T1 is connected with a first power supply end and a zero line N of a switch K to be detected through a first wiring port CN1, the first end of the secondary side of the first transformer T1 is connected with the anode of a first diode D1, the cathode of the first diode D1 is connected with the first end of a first capacitor C1, the second end of the secondary side of the first transformer T1 is connected with the second end of a first capacitor C1, and the first end and the second end of the first capacitor C1 form a power supply output end of the first step-down rectifying circuit 11.
The second step-down rectifying circuit 21 includes a second transformer T2, a second diode D2, and a second capacitor C2;
the primary side of the second transformer T2 is connected with a second power supply end and a zero line N of the switch K to be detected through a second wiring port CN2, the first end of the secondary side of the second transformer T2 is connected with the anode of a second diode D2, the cathode of the second diode D2 is connected with the first end of a second capacitor C2, the second end of the secondary side of the second transformer T2 is connected with the second end of a second capacitor C2, and the first end and the second end of the second capacitor C2 form a power supply output end of the second step-down rectifying circuit 21.
In this embodiment, the first step-down rectification circuit 11 and the second step-down rectification circuit 21 have the same structure, the first transformer T1 and the second transformer T2 realize the step-down function, the first diode D1 and the second diode D2 respectively form a half-wave rectification circuit, and meanwhile, the first capacitor C1 and the second capacitor C2 are used for filtering.
The first voltage divider circuit 12 and the second voltage divider circuit 22 may adopt a structure of a resistor voltage divider circuit, a voltage regulator circuit, etc., and referring to fig. 4, in an embodiment, the first voltage divider circuit 12 includes a first resistor R1 and a second resistor R2;
a first end of the first resistor R1 is connected to a first end of the first capacitor C1, a second end of the first resistor R1 and a first end of the second resistor R2 are connected together to form a signal output end of the first voltage divider circuit 12, and a second end of the second resistor R2 is connected to a second end of the first capacitor C1.
The second voltage dividing circuit 22 includes a third resistor R3 and a fourth resistor R4;
a first end of the third resistor R3 is connected to a first end of the second capacitor C2, a second end of the third resistor R3 and a first end of the fourth resistor R4 are commonly connected to form a signal output end of the second voltage divider circuit 22, and a second end of the fourth resistor R4 is connected to a second end of the second capacitor C2.
In this embodiment, first resistance R1 and second resistance R2 constitute resistance bleeder circuit, third resistance R3 and fourth resistance R4 constitute resistance bleeder circuit, be used for carrying out resistance partial pressure with the low pressure DC power supply of input, and output satisfies the high-low voltage of rear-end processor 30 voltage demand, thereby make processor 30 acquire corresponding high level, when the power end of detecting switch K is electrified, the high level of certain voltage value is exported to corresponding resistance bleeder circuit, when the power end of detecting switch K is uncharged, corresponding resistance bleeder circuit then exports 0V low level.
Meanwhile, in order to avoid noise input to the processor 30, in one embodiment, the first level shifter circuit 10 further includes a first output filter circuit including a third capacitor C3;
the second level shifter circuit 20 further includes a second output filter circuit including a fourth capacitor C4;
the third capacitor C3 is connected in parallel to two ends of the second resistor R2, and the fourth capacitor C4 is connected in parallel to two ends of the fourth resistor R4.
The third capacitor C3 and the fourth capacitor C4 are used for filtering the high and low levels output by the corresponding voltage division circuit, so that the detection reliability is improved.
The present invention further provides a switch state detection device, which includes a switch state detection circuit, and the specific structure of the switch state detection circuit refers to the above embodiments.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A switch state detection circuit is characterized by comprising a first wiring port, a second wiring port, a first level conversion circuit, a second level conversion circuit and a processor, wherein a signal input end of the first level conversion circuit is connected with a first power end and a zero line of a switch to be detected through the first wiring port respectively, a signal output end of the first level conversion circuit is connected with a first signal end of the processor, a signal input end of the second level conversion circuit is connected with a second power end and a zero line of the switch to be detected through the second wiring port respectively, a signal output end of the second level conversion circuit is connected with a second signal end of the processor, the first power end and the second power end of the switch to be detected are connected with a live wire in series, and the live wire and the zero line are used for transmitting an alternating current power supply;
the first level conversion circuit and the second level conversion circuit are used for converting the charged states of the first power supply end and the second power supply end of the switch to be detected into corresponding level signals respectively and outputting the level signals to the processor, so that the processor determines the switch state of the switch to be detected according to the level signals.
2. The switch state detection circuit according to claim 1, wherein the first level shift circuit includes a first step-down rectification circuit and a first voltage dividing circuit;
the power supply input end of the first voltage reduction rectification circuit is respectively connected with the first power supply end of the switch to be detected and the zero line through the first wiring port, the power supply output end of the first voltage reduction rectification circuit is connected with the power supply end of the first voltage division circuit, and the signal output end of the first voltage division circuit is connected with the first signal end of the processor;
the first voltage reduction and rectification circuit is used for carrying out voltage reduction and rectification conversion on the alternating current power supply between the first power end of the switch to be detected and the zero line and outputting a first low-voltage direct current power supply to the first voltage division circuit;
the first voltage division circuit is used for dividing the first low-voltage direct-current power supply and outputting a voltage signal representing high and low levels to the processor.
3. The switch state detection circuit according to claim 2, wherein the first step-down rectification circuit includes a first transformer, a first diode, and a first capacitor;
the primary side of the first transformer is connected with a first power end of the switch to be detected and the zero line through the first wiring port, the first end of the secondary side of the first transformer is connected with the anode of the first diode, the cathode of the first diode is connected with the first end of the first capacitor, the second end of the secondary side of the first transformer is connected with the second end of the first capacitor, and the first end and the second end of the first capacitor form a power output end of the first voltage reduction rectification circuit.
4. The switch state detection circuit of claim 3, wherein the first voltage divider circuit comprises a first resistor and a second resistor;
the first end of the first resistor is connected with the first end of the first capacitor, the second end of the first resistor and the first end of the second resistor are connected together to form a signal output end of the first voltage division circuit, and the second end of the second resistor is connected with the second end of the first capacitor.
5. The switch state detection circuit according to claim 4, wherein the first level shift circuit includes a second step-down rectification circuit and a second voltage division circuit;
the power supply input end of the second voltage reduction rectifying circuit is connected with a second power supply end of the switch to be detected and the zero line through the second wiring port respectively, the power supply output end of the second voltage reduction rectifying circuit is connected with the power supply end of the second voltage division circuit, and the signal output end of the second voltage division circuit is connected with a second signal end of the processor;
the second voltage reduction and rectification circuit is used for carrying out voltage reduction and rectification conversion on the alternating current power supply between the second power supply end of the switch to be detected and the zero line and outputting a second low-voltage direct current power supply to the second voltage division circuit;
and the second voltage division circuit is used for dividing the second low-voltage direct-current power supply and outputting a voltage signal representing high and low levels to the processor.
6. The switch state detection circuit according to claim 5, wherein the second step-down rectification circuit includes a second transformer, a second diode, and a second capacitor;
the primary side of the second transformer is connected with a second power supply end of the switch to be detected and the zero line through the second wiring port, the first end of the secondary side of the second transformer is connected with the anode of the second diode, the cathode of the second diode is connected with the first end of the second capacitor, the second end of the secondary side of the second transformer is connected with the second end of the second capacitor, and the first end and the second end of the second capacitor form a power supply output end of the second voltage reduction rectification circuit.
7. The switch state detection circuit of claim 6, wherein the second voltage divider circuit comprises a third resistor and a fourth resistor;
the first end of the third resistor is connected with the first end of the second capacitor, the second end of the third resistor and the first end of the fourth resistor are connected together to form a signal output end of the second voltage division circuit, and the second end of the fourth resistor is connected with the second end of the second capacitor.
8. The switch-state detection circuit of claim 7, wherein the first level-shifting circuit further comprises a first output filter circuit, the output filter circuit comprising a third capacitor;
the second level shift circuit further comprises a second output filter circuit, and the output filter circuit comprises a fourth capacitor;
the third capacitor is connected in parallel to two ends of the second resistor, and the fourth capacitor is connected in parallel to two ends of the fourth resistor.
9. The switch state detection circuit according to any one of claims 1 to 8, wherein a first switch circuit is disposed in the first connection port, a second switch circuit is disposed in the second connection port, a first end of the first switch circuit is connected to the first power terminal of the switch to be detected and the neutral line, a second end of the first switch circuit is connected to the signal input end of the first level conversion circuit, a first end of the second switch circuit is connected to the second power terminal of the switch to be detected and the neutral line, a second end of the first switch circuit is connected to the signal input end of the second level conversion circuit, and controlled terminals of the first switch circuit and the second switch circuit are respectively connected to the processor.
10. A switching state detection device comprising the switching state detection circuit according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121166048.1U CN216160781U (en) | 2021-05-27 | 2021-05-27 | Switch state detection circuit and switch state detection device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121166048.1U CN216160781U (en) | 2021-05-27 | 2021-05-27 | Switch state detection circuit and switch state detection device |
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| CN216160781U true CN216160781U (en) | 2022-04-01 |
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| CN202121166048.1U Active CN216160781U (en) | 2021-05-27 | 2021-05-27 | Switch state detection circuit and switch state detection device |
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2021
- 2021-05-27 CN CN202121166048.1U patent/CN216160781U/en active Active
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