CN216145153U - Server mainboard, PCIE equipment and server - Google Patents

Abstract

The embodiment of the utility model relates to the technical field of servers, and discloses a server mainboard, PCIE equipment and a server, wherein the server mainboard comprises: the PCIE slot is used for being connected with the PCIE equipment in a matching way; the first connector is connected with the PCIE equipment through a first cable and is used for transmitting an in-place signal of the PCIE equipment; the CPLD is used for detecting the in-place signal to judge whether the PCIE equipment is in an independent working state; the power supply unit is used for supplying power to the PCIE equipment, and the clock unit comprises an external clock chip and is used for providing a clock signal for the PCIE equipment; when the PCIE equipment works independently, the power supply unit supplies power to the PCIE equipment when the server is powered off, and the clock unit provides clock signals to the PCIE equipment through the external time chip. Through the manner, the embodiment of the utility model enables the PCIE equipment to still normally work in the shutdown state of the server, is not influenced by the startup and shutdown of the server, and has independent working state.

Description

Server mainboard, PCIE equipment and server

Technical Field

The embodiment of the utility model relates to the technical field of servers, in particular to a server mainboard, PCIE equipment and a server.

Background

The server is a computer, and the internal structure of the server is not much different from the internal structure of a common computer, such as: CPU, hard disk, memory, system bus, etc. PCI-express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard. The PCIE interface device is a device that communicates with the CPU using a PCIE bus, such as a network card, a display card, an NVME SSD, a RAID card, and an FPGA accelerator card.

The server is usually called as the power-off state of S5 and the power-on state of S0. In the state of S5, a Standby power supply (Standby power) of the server is powered on to supply power to devices that need to operate in S5, such as CPLD, BMC, PCH, and other chips. And in the S0 state, the Main power supply (Main power) is powered on to supply power to the equipment needing to work in the S0 state, such as a CPU, an internal memory, a hard disk, a PCIE interface and the like. After the system is turned on (the power-on button or the remote BMC management software control), as shown in fig. 1, the voltage chip on the server motherboard supplies power to the PCIE device: 12V and 3.3V, which are Main power, and PCH (Platform Controller Hub, integrated south bridge chip) is provided for the PCIE device 100Mhz clock, and the CPU and the PCIE device communicate via the PCIE data link.

In the prior art, the working state of the PCIE device depends on the state of the server, and the PCIE device can work after the server is powered on. However, in some FPGA accelerator card designs, there are application scenarios where the accelerator card still can work normally after the server is powered off, with a CPU and a storage device, and with an independent operating system. Obviously, existing PCIE devices do not meet this requirement.

SUMMERY OF THE UTILITY MODEL

In view of the foregoing problems, embodiments of the present invention provide a server motherboard, a PCIE device, and a server, which overcome the foregoing problems or at least partially solve the foregoing problems.

According to an aspect of an embodiment of the present invention, there is provided a server board, including: the PCIE slot is used for being connected with the PCIE equipment in a matching way; the first connector is connected with the PCIE equipment through a first cable and is used for transmitting an in-place signal of the PCIE equipment; the CPLD is used for detecting the in-place signal to judge whether the PCIE equipment is in an independent working state; the power supply unit is used for supplying power to the PCIE equipment, and the clock unit comprises an external clock chip and is used for providing a clock signal for the PCIE equipment; when the PCIE equipment works independently, the power supply unit supplies power to the PCIE equipment when the server is powered off, and the clock unit provides clock signals to the PCIE equipment through the external time chip.

In an optional manner, the server motherboard further includes a second connector, which is connected to the PCIE device through a second cable, and configured to provide power to the PCIE device through the second connector when the power provided by the PCIE slot is not enough to support the power consumption of the PCIE device.

In an optional mode, the power supply unit comprises a power supply device, and the CPLD comprises a first programmable memory; when the PCIE equipment works independently, the power supply device supplies power to the CPLD, the CPLD outputs a first enabling signal to open the first programmable memory, and the power supply device supplies power to the PCIE equipment.

In an optional manner, when the CPLD outputs a first enable signal to open the first programmable memory, the CPLD also outputs a first clock control signal to the external clock chip, and controls the external clock chip to output a first clock signal to the PCIE device.

In an optional manner, the server motherboard further includes: the management unit at least comprises a baseboard management controller, and the baseboard management controller conducts power-on and power-off and reset control on the PCIE equipment through an I2C signal line passing through the PCIE slot and manages the working state of the PCIE equipment.

In an optional manner, the server motherboard further includes: the heat dissipation unit comprises a fan system formed by a plurality of fans, the fan system is powered by a standby power supply, and the rotating speed of each fan and the temperature of each unit in the PCIE equipment are acquired through the substrate management controller to control and adjust the rotating speeds of the plurality of fans.

In an optional manner, the CPLD is connected to the baseboard management controller, and performs heartbeat monitoring on the baseboard management controller, and if the baseboard management controller is down, the PCLD controls to adjust the rotation speeds of the plurality of fans to the maximum.

According to another aspect of the embodiments of the present invention, there is provided a PCIE device, where the PCIE device operates independently with respect to a server motherboard, and the PCIE device includes: and one end of the third connector is grounded, and the other end of the third connector is connected with the server mainboard through a first cable and is used for transmitting the in-place signal of the PCIE equipment with the server mainboard.

In an optional manner, the PCIE device further includes: and the fourth connector is connected with the server mainboard through a second cable and used for supplying power.

According to another aspect of the embodiment of the present invention, a server is provided, where the server includes the foregoing server motherboard and the foregoing PCIE device.

The server main board of the embodiment of the utility model comprises: the PCIE slot is used for being connected with the PCIE equipment in a matching way; the first connector is connected with the PCIE equipment through a first cable and is used for transmitting an in-place signal of the PCIE equipment; the CPLD is used for detecting the in-place signal to judge whether the PCIE equipment is in an independent working state; the power supply unit is used for supplying power to the PCIE equipment, and the clock unit comprises an external clock chip and is used for providing a clock signal for the PCIE equipment; when the PCIE equipment works independently, the power supply unit supplies power to the PCIE equipment when the server is powered off, and the clock unit provides clock signals to the PCIE equipment through the external time chip, so that the PCIE equipment can still work normally in the power-off state of the server, the PCIE equipment is not influenced by the power-on and power-off of the server, and the working state is independent.

The foregoing description is only an overview of the technical solutions of the embodiments of the present invention, and the embodiments of the present invention can be implemented according to the content of the description in order to make the technical means of the embodiments of the present invention more clearly understood, and the detailed description of the present invention is provided below in order to make the foregoing and other objects, features, and advantages of the embodiments of the present invention more clearly understandable.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the utility model. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

fig. 1 shows a connection diagram of a PCIE device in the prior art;

fig. 2 is a schematic structural diagram of a server provided in an embodiment of the present invention;

fig. 3 is a schematic power supply diagram of a power supply unit of a server motherboard according to an embodiment of the present invention;

fig. 4 is a schematic diagram illustrating an operation of a clock unit of a server motherboard according to an embodiment of the present invention;

fig. 5 is a schematic diagram illustrating a management unit of a server motherboard according to an embodiment of the present invention;

fig. 6 shows a schematic diagram of a heat dissipation unit of a server motherboard according to an embodiment of the present invention.

Detailed Description

Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the utility model are shown in the drawings, it should be understood that the utility model can be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the utility model to those skilled in the art.

Fig. 2 shows a schematic structural diagram of a server provided in an embodiment of the present invention. As shown in fig. 2, the server includes a server motherboard and PCIE devices that can operate independently. The server mainboard includes: the PCIE slot is used for being connected with the PCIE equipment in a matching way; the first connector J1 is connected to the PCIE device through a first cable, and is configured to transmit an in-place signal of the PCIE device; a CPLD (Complex Programmable Logic Device) configured to detect the on-site signal to determine whether the PCIE Device is in an independent operating state; the power supply unit is used for supplying power to the PCIE equipment, and the clock unit comprises an external clock chip and is used for providing a clock signal for the PCIE equipment; when the PCIE equipment works independently, the power supply unit supplies power to the PCIE equipment when the server is powered off, and the clock unit provides clock signals to the PCIE equipment through the external time chip.

The PCIE slot is a standard PCIE 16 slot. The server motherboard can also be connected with a second PCIE device in a common working state through different PCIE slots. The PCIE equipment capable of working independently can be used as an independent subsystem on the server, shares the power supply and the clock on the server, is not affected by other power supplies and clocks on the server, and can meet the heat dissipation and management requirements needed by the normal working of the PCIE equipment under the shutdown state of the server, and comprises the management functions of detecting the temperature, the current, abnormal alarm and the like on the PCIE equipment.

In the embodiment of the present invention, the first cable transmits the bit signal PRST _ N of the PCIE device. The PRST _ N signal line has a Pull-up (Pull up) resistor (not shown) on the server motherboard to 3.3V, which is connected to ground on the PCIE card. When the first cable is not connected, the PRST _ N signal is high (3.3V), and the PCIE device is not in an independent operating state. When the first cable is connected, the PRST _ N signal is at a low level (0V), and the PCIE device operates in an independent operating state.

The server motherboard further comprises a second connector J2, which is connected to the PCIE device through a second cable, and configured to provide an additional +12V power supply to the PCIE device through the second connector when the power supply provided by the PCIE slot does not support the power consumption of the PCIE device.

The power supply required by the second PCIE device is a Main power supply (Main power) provided by the server motherboard, and the Main power supply needs to be provided by the server motherboard after the server motherboard is powered on. If the PCIE equipment in the independent state is inserted, the server needs the mainboard to provide an independent power supply for the PCIE equipment in the independent working state, and the server does not need to be started. In the embodiment of the present invention, the power supply unit includes a Power Supply Unit (PSU), and the CPLD includes a first programmable memory Efuse3 therein. The power supply device is positioned in the original server, other additional power supply equipment is not needed, and only the logic in the original CPLD needs to be modified and the first programmable memory Efuse3 is added, wherein the first programmable memory is a one-time programmable memory chip (Efuse 3). The server judges whether the inserted PCIE equipment is the PCIE equipment with the independent working state or not and provides power supply. When the PCIE device works independently, the power supply device supplies power to the CPLD, the CPLD outputs a first enable signal enable _3 to open the first programmable memory Sfuse3, and the power supply device supplies power to the PCIE device. As shown in fig. 3, the power supply unit PSU is plugged into a power line and outputs a 12V power, and the Standby power supply Standby power is powered on through the second programmable memory Efuse1 to supply power to each device operating in the S5 state (power off state), including chips such as a CPLD, a BMC, and a PCH. After the CPLD is powered on, the on-position signal PRST _ N of the PCIE equipment is connected to the CPLD. The CPLD is used for detecting the in-place signal of the PCIE equipment in the independent state to judge the inserted equipment. If the PCIE device is in the independent state, the PRST _ N signal is pulled low (0V) by a pull-down resistor (not shown) on the PCIE device card, the CPLD immediately outputs the second enable signal enable _1, opens the first programmable memory Efuse3, outputs +12V _ NIC, and supplies power to the PICE device in the independent operating state. If a PCIE device in an independent state is not provided and a common second PCIE device is inserted, the PRST _ N signal is not pulled low, a default pull-up resistor is arranged on a server mainboard, the level is high (3.3V), the PCIE works in a common working state at the moment but not in an independent working state, the CPLD simultaneously outputs a second enable signal enable _1 and a third enable signal enable _2, the first programmable memory Efuse3 is opened through the second enable signal enable _1, and +12V _ NIC is output to supply power to the PICE device in the independent working state. The third enable signal enable _2 is a starting signal of a Main power supply (Main power) chip sent by the CPLD after the server is started, the third programmable memory Efuse2 is opened through the third enable signal enable _2, the Main power supply Main power is output, and power is supplied to devices needing to work in the S0 state (starting state), such as a CPU, a memory, a hard disk, a PCIE interface, and the like.

In the design of the universal server, the server needs to be powered on to provide the clock required by the PCIE device, and the clock cannot be obtained in the S5 state. The embodiment of the utility model adopts an external clock chip instead of an internal clock provided by a south bridge chip, and the CPLD is used for controlling and sending the starting signal of the clock required by the PCIE equipment. Alternatively, as shown in fig. 4, the CPLD detects the presence signal PRST _ N through the first cable connecting between the first connector and the third connector. If the bit signal PRST _ N is low level, that is, when the PCIE device operates independently, the CPLD outputs the first enable signal enable _3 to open the first programmable memory Efuse3, and also outputs the first clock control signal CLK _ GEN _ OE3 to the external clock chip, and controls the external clock chip to output the first clock signal 100M _ PCIE _ CLK _2 to the PCIE device in the independent operating state, so as to be used by the PCIE device in the independent operating state. The first clock signal 100M _ PCIE _ CLK _2 is the clock that the server provides to the PCIE devices at S5. The external clock chip turn-on signals emitted by the CPLD further include a second clock control signal CLK _ GEN _ OE1 and a third clock control signal CLK _ GEN _ OE 2. The second clock control signal CLK _ GEN _ OE1 and the third clock control signal CLK _ GEN _ OE2 are issued along with the third enable signal enable _2 that turns on the third programmable memory Efuse2, that is, the Main power supply Main power after the server is powered on, and the second clock control signal CLK _ GEN _ OE1 controls the second clock signal 100M _ BCLK to be issued to the CPU. The third clock control signal CLK _ GEN _ OE2 controls the third clock signal 100M _ PCIE _ CLK _1 to be asserted to PCIE devices in a normal operating state. The second clock signal 100M _ BCLK and the third clock signal 100M _ PCIE _ CLK _1 are both clocks of devices in the operating state of the server S0.

In this embodiment of the present invention, the server motherboard further includes: and the management unit at least comprises a baseboard management controller BMC. As shown in fig. 5, the BMC performs power-on and power-off, reset control and management on the operating state of the PCIE device through the I2C signal line of the PCIE slot. The power-on and power-off time sequence signals of the CPLD control card are controlled by a BMC IPMI (Intelligent Platform Management Interface) command read-write CPLD register on the PCIE equipment. For example, if the PCIE device is to be powered off through the server, the SOL management interface of the BMC is accessed first, and the PWRBTN _ N signal of the CPLD on the PCIE device card is pulled down by a lower IPMI command, so that the PCIE device card is powered off. For example, the shutdown command is ipmitool, exe-I lan-H192.168.1.123-U admin-Padmin raw 0x3c 0xf 70 x02//0x01 power-on 0x02 power-off 0x03 restart.

The BMC chip of the server, as a Master, manages Slave devices, such as Soc, an FPGA chip, and a power chip on the card, through I2C/SMBUS signals via SMBUS (System Management Bus) signal lines on the PCIE slot. The BMC chip can monitor the state of the PCIE equipment, including power consumption, temperature, abnormal state alarm and the like. The method specifically comprises the steps of reading the temperature and the power consumption of an SOC and an FPGA on a PCIE equipment card and the temperature and the current of a power management chip. This function is implemented by reading and writing the I2C register of the accessing slave device. For example, the slave address of the CPLD is 0X80, and the state of the card, such as the signal state of Soc VR hot \ Prohot, can be obtained by reading the corresponding register location. And firmware upgrading can be performed on the CPLD of the PCIE equipment card through the BMC chip. And reading and writing the register of the CPLD on the PCIE equipment through a BMC IPMI command.

The power supplied to the FAN by the conventional system design is 12V _ FAN power provided by the motherboard when the motherboard is turned on (S0 state), which is the Main power source Main power generated after the power key of the server motherboard is triggered. The fan cannot operate in the off state (S5 state), and cannot dissipate heat for the PCIE device in the independent operating state. In this embodiment of the present invention, the server motherboard further includes: and a heat dissipation unit. As shown in fig. 6, the heat dissipation unit includes a fan system formed by a plurality of fans, the fan system is powered by a standby power supply, and the BMC obtains the rotation speed of each fan and the temperature of each unit in the PCIE device to control and adjust the rotation speeds of the plurality of fans. Namely, the power (12V _ FAN) of the FAN system is modified to the Standby power in the state of S5, that is, the 12V _ FAN power can be generated without starting up, and the power can dissipate heat for the PCIE devices which normally operate when the system is shut down. That is, the fans in the fan system are powered by the Standby power supply Standby power in the off state (S5 state) to supply +12V _ STBY. The server reads the rotating speed of the fan and the temperature of key elements on the PCIE equipment through the BMC, and dynamically adjusts the rotating speed of the fan according to a heat dissipation strategy. As shown in fig. 6, the BMC reads the Tach signal (FAN speed) of each FAN (FAN), and the BMC reads the temperature of the key chip on the PCIE device card through the I2C signal, and according to the heat dissipation strategy, when the temperature exceeds a set threshold, for example, the internal junction temperature of the SOC chip on the PCIE device reaches 100 degrees, the BMC adjusts the speed of each FAN to the highest 90% through the PWM signal. And meanwhile, the CPLD is connected with the baseboard management controller BMC to monitor the heartbeat of the baseboard management controller BMC, namely, the BMC continuously sends a low-frequency clock signal to the CPLD. And if the BMC is down and a clock signal is not sent out, the PCLD controls to adjust the rotating speeds of the fans to the maximum.

The embodiment of the utility model provides independent power supplies and clocks for the PCIE equipment which works independently, the power supplies and the clocks can be continuously provided under the condition that the server is powered off, and the system heat dissipation and the equipment management under the condition that the server is powered off are provided, so that the PCIE equipment can still work normally under the condition of power off, the PCIE equipment is not influenced by the power on and power off of the server, the working state is independent, and the application scene of the product is wider. For example, the method can be applied to PCIE acceleration card design with a CPU and an operating system, and can still run cloud platform management software under the condition that a server is shut down.

The present invention also provides a PCIE device, referring to fig. 2, the PCIE device may independently operate with respect to a server motherboard, and the PCIE device includes: and one end of the third connector J3 is grounded, and the other end of the third connector J3 is connected with the server motherboard through a first cable, and is used for transmitting an in-place signal PRST _ N of the PCIE device with the server motherboard. When the PCIE device works independently, the first cable connecting the first connector J1 and the third connector J3 is connected, and the PCIE device transmits the low-level in-place signal PRST _ N to the server motherboard through the first cable. The PCIE device further includes: a fourth connector J4, the fourth connector J4 is connected with the server main board through a second cable for supplying power. The fourth connector J4 is connected to the second connector J2 of the server motherboard via a second cable, and receives an additional +12V power supply provided by the server motherboard via the second cable when the power supply provided by the PCIE slot does not sufficiently support the power consumption of the PCIE device.

The server main board of the embodiment of the utility model comprises: the PCIE slot is used for being connected with the PCIE equipment in a matching way; the first connector is connected with the PCIE equipment through a first cable and is used for transmitting an in-place signal of the PCIE equipment; the CPLD is used for detecting the in-place signal to judge whether the PCIE equipment is in an independent working state; the power supply unit is used for supplying power to the PCIE equipment, and the clock unit comprises an external clock chip and is used for providing a clock signal for the PCIE equipment; when the PCIE equipment works independently, the power supply unit supplies power to the PCIE equipment when the server is powered off, and the clock unit provides clock signals to the PCIE equipment through the external time chip, so that the PCIE equipment can still work normally in the power-off state of the server, the PCIE equipment is not influenced by the power-on and power-off of the server, and the working state is independent.

In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the utility model may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the utility model, various features of the embodiments of the utility model are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that the utility model as claimed requires more features than are expressly recited in each claim.

Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

It should be noted that the above-mentioned embodiments illustrate rather than limit the utility model, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The utility model may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names. The steps in the above embodiments should not be construed as limiting the order of execution unless specified otherwise.

Claims (10)

1. A server board, comprising:

the PCIE slot is used for being connected with the PCIE equipment in a matching way;

the first connector is connected with the PCIE equipment through a first cable and is used for transmitting an in-place signal of the PCIE equipment;

the CPLD is used for detecting the in-place signal to judge whether the PCIE equipment is in an independent working state;

the power supply unit is used for supplying power to the PCIE equipment, and the clock unit comprises an external clock chip and is used for providing a clock signal for the PCIE equipment;

when the PCIE equipment works independently, the power supply unit supplies power to the PCIE equipment when the server is powered off, and the clock unit provides clock signals to the PCIE equipment through the external time chip.

2. The server motherboard of claim 1, further comprising a second connector connected to the PCIE device through a second cable, and configured to provide power to the PCIE device through the second connector when the power provided through the PCIE slot is not enough to support the power consumption of the PCIE device.

3. The server motherboard according to claim 1, wherein the power supply unit includes a power supply device, and the CPLD includes a first programmable memory therein;

when the PCIE equipment works independently, the power supply device supplies power to the CPLD, the CPLD outputs a first enabling signal to open the first programmable memory, and the power supply device supplies power to the PCIE equipment.

4. The server motherboard of claim 3 wherein when the CPLD outputs a first enable signal to turn on the first programmable memory, the CPLD further outputs a first clock control signal to the external clock chip to control the external clock chip to output a first clock signal to the PCIE device.

5. The server motherboard according to claim 1, wherein the server motherboard further comprises: the management unit at least comprises a baseboard management controller, and the baseboard management controller conducts power-on and power-off and reset control on the PCIE equipment through an I2C signal line passing through the PCIE slot and manages the working state of the PCIE equipment.

6. The server motherboard according to claim 5, wherein the server motherboard further comprises: the heat dissipation unit comprises a fan system formed by a plurality of fans, the fan system is powered by a standby power supply, and the rotating speed of each fan and the temperature of each unit in the PCIE equipment are acquired through the substrate management controller to control and adjust the rotating speeds of the plurality of fans.

7. The server motherboard of claim 6 wherein the CPLD is coupled to the baseboard management controller to monitor the heartbeat of the baseboard management controller, and the PCLD is configured to control the plurality of fans to have the maximum rotational speed if the baseboard management controller is down.

8. A PCIE device, wherein the PCIE device operates independently with respect to a server motherboard, the PCIE device includes: and one end of the third connector is grounded, and the other end of the third connector is connected with the server mainboard through a first cable and is used for transmitting the in-place signal of the PCIE equipment with the server mainboard.

9. The PCIE device of claim 8, wherein the PCIE device further comprises: and the fourth connector is connected with the server mainboard through a second cable and used for supplying power.

10. A server, comprising a server motherboard according to any one of claims 1 to 7 and a PCIE device according to claim 8 or 9.

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