CN216134297U - External battery module supporting charging and discharging different ports - Google Patents
External battery module supporting charging and discharging different ports Download PDFInfo
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- CN216134297U CN216134297U CN202122433555.3U CN202122433555U CN216134297U CN 216134297 U CN216134297 U CN 216134297U CN 202122433555 U CN202122433555 U CN 202122433555U CN 216134297 U CN216134297 U CN 216134297U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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Abstract
The utility model relates to an external battery module supporting charging and discharging different ports, wherein a battery management unit U1 is provided with a primary protection circuit, a secondary protection circuit, a sampling circuit, a battery PACK, a communication module, a temperature detection circuit, a current equalization circuit and a voltage sampling circuit at the periphery, and is also provided with a battery charging interface J2 and a battery discharging interface J1, a CHG signal port and a PACK _ N signal port are arranged on the battery charging interface J2 and are respectively matched and connected with a PACK _ P signal port and a PACK _ N signal port arranged in the battery discharging interface J1, and a CHS signal port in a battery management unit U1 is also matched and connected with the PACK _ P signal port. Whether the charging wire is connected in this kind of structure's setting passes through the CHS signal port to the battery interface J2 that charges detects, and protects the heavy current in the twinkling of an eye that probably appears in the power return circuit through one-level protection circuit and second grade protection circuit, through voltage sampling circuit, current equalizer circuit, temperature detection circuit and sampling circuit, the flexibility and the expansibility of reinforcing circuit prevent that the fuselage from generating heat.
Description
Technical Field
The utility model relates to the technical field of battery power supply circuits in electronic equipment powered by a lithium battery, in particular to an external battery module supporting charging and discharging of different ports.
Background
In the prior art, most of the charging chips of the electronic equipment supporting the lithium battery power supply are installed in the equipment, the stored electric quantity in the equipment is reduced, and when charging is needed, because the energy conversion loss generated by a charging management circuit arranged in the equipment due to factors such as conversion efficiency, circuit impedance and the like is reflected on electronic elements in the circuit in the form of heat loss, the machine body of the equipment is heated; the lower the conversion efficiency in the charging process is, the larger the temperature rise generated on the electronic element is, and the battery in the equipment cannot be detached, so that the maintainability of the equipment is reduced, and the later maintenance cost is improved.
In the battery charging system of the external charging control mode in patent document CN201611206900.7, by setting the battery monitoring and protecting module and the communication module inside the mobile device, and simultaneously externally installing the circuit part of the large-size and high-temperature-rise high-power charging management module into the charging controller, the problem of heat generation of the body of the mobile device is prevented, and the manufacturing volume of the mobile device is optimized, but the manufacturing cost is increased by externally installing the circuit part of the high-temperature-rise high-power charging management module into the charging controller, and the later maintenance cost is high.
Disclosure of Invention
In order to solve the problems, the utility model provides an external battery with charging modules arranged in a battery module, which can unify standards, reduce cost, improve flexibility and expansibility of a circuit, reduce heat generation of an equipment body and support charging and discharging different ports for charging at any time.
In order to achieve the above purpose, the external charging module supporting charging and discharging of different ports, which is designed by the utility model, comprises a battery management unit U1, a battery PACK U4, a schottky diode D1, a power tube U2, a battery charging interface J2 and a battery discharging interface J1, wherein a PACK _ P signal port and a PACK _ N signal port are arranged on the battery discharging interface J1, a CHG signal port and a PACK _ N signal port are arranged on the battery charging interface J2, the CHG signal port and the PACK _ P signal port are connected through the schottky diode D1, the PACK _ N signal port is connected with the PACK _ N signal port, and a PRES signal port, a SDA signal port and an SCL signal port are further arranged in the battery discharging interface J1; a CHS signal pin arranged in the battery management unit U1 is connected with a PACK _ P signal port in a matching way; the PRES signal port, the SDA signal port and the SCL signal port respectively correspond to a PRES signal pin, an SDA signal pin and an SCL signal pin which are arranged in the battery management unit U1; an I2C communication interface is arranged between the SCL signal pin and the SCL signal port, and between the SDA signal pin and the SDA signal port; the battery management unit U1 is all around still be provided with one-level protection circuit, secondary protection circuit, sampling circuit, group battery, communication module, temperature detection circuit, current equalizer circuit and voltage sampling circuit. The arrangement of the structure detects the insertion of the charger by matching and connecting a CHS signal pin arranged in the battery management unit U1 with a PACK _ P signal port, and meanwhile, a primary protection circuit, a secondary protection circuit, a sampling circuit, a battery PACK, a communication module, a temperature detection circuit, a current equalization circuit and a voltage sampling circuit are also arranged around the battery management unit U1, so that a power supply loop can be protected.
The further scheme is that an NMOS tube Q3 is connected to the PACK _ P signal port in a matching manner, an NMOS tube Q4 is arranged between the source electrode of the NMOS tube Q3 and the PACK _ P signal port, and a resistor R10 is arranged on the grid electrode of the NMOS tube Q4 and is grounded; the grid electrode of an NMOS tube Q3 is connected with a DSG signal pin arranged in a battery management unit U1, a resistor R8 is arranged between the grid electrode of an NMOS tube Q3 and the DSG signal pin, a resistor R9 is arranged between the source electrode of the NMOS tube Q3 and the drain electrode of the NMOS tube Q4, one side of the drain electrode of the NMOS tube Q3 is respectively connected with the source electrode of a PMOS tube Q1 and the drain electrode of an NMOS tube Q2, the grid electrode of the PMOS tube Q1 is connected with a PCHG signal pin arranged in the battery management unit U1, a resistor R4 is arranged between the grid electrode of the PMOS tube Q1 and the PCHG signal pin, the source electrode of the PMOS tube Q1 is connected with a VCC signal pin arranged in the battery management unit U1, a resistor R7 is arranged between the source electrode of the PMOS tube Q1 and the VCC signal pin, and a resistor R6 is arranged between the source electrode of the PMOS tube Q1 and the gate electrode; the grid electrode of the NMOS tube Q2 is connected with a CHG signal pin arranged in the battery management unit U1, a resistor R3 is arranged between the grid electrode of the NMOS tube Q2 and the CHG signal pin, and a resistor R2 is arranged on a connecting line between the resistor R3 and the source electrode of the NMOS tube Q2; a resistor R1 is arranged between the resistor R2 and the drain electrode of the PMOS tube Q1, and a capacitor C1 and a capacitor C2 are arranged between the resistor R2 and the resistor R9 to form a primary protection circuit; the primary protection circuit is provided with a three-terminal fuse F1 towards the source electrode direction of an NMOS tube Q2; an NMOS tube Q5 is arranged at the 3-phase end of the three-terminal FUSE F1, a grid electrode of the NMOS tube Q5 is connected with a FUSE signal pin arranged in the battery management unit U1, and a resistor R5 is arranged between the grid electrode of the NMOS tube Q5 and a grounding end on a source electrode of the NMOS tube Q5, so that a secondary protection circuit is formed. The arrangement of the structure provides a large-current discharge path for ESD through the arrangement of the capacitor C1 and the capacitor C2 in the primary protection circuit, the PMOS tube Q1 and the NMOS tube Q2 are prevented from being damaged due to current impact, the NMOS tube Q4 can be reversely connected at the battery discharge interface J1, and when the voltage of a PACK _ P signal port is a negative value, the NMOS tube Q4 is conducted to protect the NMOS tube Q3; the three-terminal fuse in the secondary protection circuit can be fused when a large current appears in a power supply loop instantly, so that the power supply loop is protected.
Further, a battery pack U4 is disposed at the phase 1 end of the three-terminal fuse F1, a VBAT signal pin is disposed in the battery management unit U1, and the VBAT signal pin is disposed between the phase 1 end of the three-terminal fuse F1 and the positive electrode of the battery pack U4; the battery pack U4 is divided into two groups of batteries B2 and B1, the positive pole of the battery B2 is connected with a VC2 signal pin arranged in a battery management unit U1 in a matching way, and a resistor R11 is arranged between the positive pole of the battery B2 and the VC2 signal pin arranged in the battery management unit U1; the positive electrode of the B1 battery is connected with a VC1 signal pin arranged in the battery management unit U1 in a matching way, and a resistor R12 is arranged between the positive electrode of the B1 battery and a VC1 signal pin arranged in the battery management unit U1; a capacitor C3 is connected between the VC2 signal pin and the VC1 signal pin, a capacitor C4 is connected between the VC1 signal pin and a VSS signal pin arranged in the battery management unit U1, and a capacitor C3 is connected with a capacitor C4 in series to form a voltage sampling circuit and a current balancing circuit; a resistor R15 is arranged between the cathode of the B1 battery and a PACK _ n signal port, one end of the resistor R15 is connected with a SENSEP signal pin arranged in the battery management unit U1 in a matching way, and the other end of the resistor R15 is connected with a SENSEN signal pin arranged in the battery management unit U1 in a matching way; a resistor R13 is arranged between the SENSEP signal pin and a VSS signal pin of a grounding signal of the battery management unit U1, and a resistor R14 is arranged between the SENSEN signal pin and a PACK _ n signal port; a capacitor C5 is connected between the SENSEP signal pin and the SENSEN signal pin, and the capacitor C5 is a differential mode capacitor, so that a sampling circuit is formed; a TSI signal pin is arranged in the battery management unit U1, a resistor R16 is arranged on the TSI signal pin, and the resistor R16 is an NTC resistor and forms a temperature detection circuit; the battery management unit U1 is divided into a charging mode and a discharging mode, when the voltage value of the SENSEP signal pin is greater than that of the SENSEN signal pin, the system is in the charging mode, and when the voltage value of the SENSEP signal pin is less than that of the SENSEN signal pin, the system is in the discharging mode, the battery management unit U1 has three different charging stages in the charging mode, namely a pre-charging stage, a constant-current charging stage and a constant-voltage charging stage, and voltage thresholds entering the three different charging stages respectively correspond to a pre-charging voltage V1, a constant-current charging voltage V2 and a constant-voltage charging voltage V3.
The utility model relates to an external battery module supporting charging and discharging different ports, wherein a primary protection circuit, a secondary protection circuit, a sampling circuit, a battery PACK, a communication module, a temperature detection circuit, a current equalization circuit and a voltage sampling circuit are respectively arranged around a battery management unit U1, a battery charging interface J2 and a battery discharging interface J1 are simultaneously arranged, a CHG signal port and a PACK _ N signal port which are arranged in the battery charging interface J2 are respectively matched and connected with a PACK _ P signal port and a PACK _ N signal port which are arranged in the battery discharging interface J1, and a CHS signal port in a battery management unit U1 is also matched and connected with the PACK _ P signal port. Whether the setting of this kind of structure is connected with the charging wire through CHS signal port in to battery charge interface J2 and detects, and the heavy current in the twinkling of an eye that probably appears in to power supply loop through the setting of one-level protection circuit and secondary protection circuit protects, and the setting through voltage sampling circuit, current equalizer circuit, temperature detection circuit and sampling circuit has reduced generating heat of equipment fuselage when improving the flexibility and the expansibility of circuit.
Drawings
Fig. 1 is a schematic circuit diagram of an external battery module supporting charging and discharging of different ports.
Fig. 2 is a circuit block diagram of an external battery module supporting a charging/discharging outlet.
Fig. 3 is a circuit diagram of an external battery module supporting a charging/discharging outlet.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of the embodiments, structures, features and effects according to the present invention will be made with reference to the accompanying drawings and preferred embodiments.
Example 1.
As shown in fig. 1 and fig. 2, the external charging module supporting charging and discharging of different ports described in this embodiment includes a battery management unit U1, a battery PACK U4, a schottky diode D1, a power tube U2, a battery charging interface J2 and a battery discharging interface J1, a PACK _ P signal port and a PACK _ N signal port are disposed on the battery discharging interface J1, a CHG signal port and a PACK _ N signal port are disposed on the battery charging interface J2, the CHG signal port and the PACK _ P signal port are connected by a schottky diode D1, the PACK _ N signal port is connected with the PACK _ N signal port, and a PRES signal port, an SDA signal port and an SCL signal port are further disposed in the battery discharging interface J1; a CHS signal pin arranged in the battery management unit U1 is connected with a PACK _ P signal port in a matching way; the PRES signal port, the SDA signal port and the SCL signal port respectively correspond to a PRES signal pin, an SDA signal pin and an SCL signal pin which are arranged in the battery management unit U1; an I2C communication interface is arranged between the SCL signal pin and the SCL signal port, and between the SDA signal pin and the SDA signal port; the battery management unit U1 is all around still be provided with one-level protection circuit, secondary protection circuit, sampling circuit, group battery, communication module, temperature detection circuit, current equalizer circuit and voltage sampling circuit.
As shown in fig. 1, 2 and 3, the PACK _ P signal port is connected with an NMOS transistor Q3 in a matching manner, an NMOS transistor Q4 is arranged between the source of the NMOS transistor Q3 and the PACK _ P signal port, and the gate of the NMOS transistor Q4 is provided with a resistor R10 and is grounded; the grid electrode of the NMOS tube Q3 is connected with a DSG signal pin arranged in the battery management unit U1, a resistor R8 is arranged between the grid electrode of the NMOS tube Q3 and the DSG signal pin, and a resistor R9 is arranged between the source electrode of the NMOS tube Q3 and the drain electrode of the NMOS tube Q4; one side of the drain of the NMOS tube Q3 is respectively connected with the source of a PMOS tube Q1 and the drain of an NMOS tube Q2, the grid of the PMOS tube Q1 is connected with a PCHG signal pin arranged in the battery management unit U1, a resistor R4 is arranged between the grid of the PMOS tube Q1 and the PCHG signal pin, the source of the PMOS tube Q1 is connected with a VCC signal pin arranged in the battery management unit U1, a resistor R7 is arranged between the source of the PMOS tube Q1 and the VCC signal pin, and a resistor R6 is arranged between the source of the PMOS tube Q1 and the grid; the grid electrode of the NMOS tube Q2 is connected with a CHG signal pin arranged in the battery management unit U1, a resistor R3 is arranged between the grid electrode of the NMOS tube Q2 and the CHG signal pin, and a resistor R2 is arranged on a connecting line between the resistor R3 and the source electrode of the NMOS tube Q2; a resistor R1 is arranged between the resistor R2 and the drain electrode of the PMOS tube Q1, and a capacitor C1 and a capacitor C2 are arranged between the resistor R2 and the resistor R9 to form a primary protection circuit; the primary protection circuit is provided with a three-terminal fuse F1 towards the source electrode direction of an NMOS tube Q2; an NMOS tube Q5 is arranged at the 3-phase end of the three-terminal FUSE F1, a grid electrode of the NMOS tube Q5 is connected with a FUSE signal pin arranged in the battery management unit U1, and a resistor R5 is arranged between the grid electrode of the NMOS tube Q5 and a grounding end on a source electrode of the NMOS tube Q5, so that a secondary protection circuit is formed.
A battery pack U4 is arranged at the phase 1 end of the three-end fuse F1, a VBAT signal pin is arranged in the battery management unit U1, and the VBAT signal pin is arranged between the phase 1 end of the three-end fuse F1 and the anode of the battery pack U4; the battery pack U4 is divided into two groups of batteries B2 and B1, the positive pole of the battery B2 is connected with a VC2 signal pin arranged in a battery management unit U1 in a matching way, and a resistor R11 is arranged between the positive pole of the battery B2 and the VC2 signal pin arranged in the battery management unit U1; the positive electrode of the B1 battery is connected with a VC1 signal pin arranged in the battery management unit U1 in a matching way, and a resistor R12 is arranged between the positive electrode of the B1 battery and a VC1 signal pin arranged in the battery management unit U1; a capacitor C3 is connected between the VC2 signal pin and the VC1 signal pin, a capacitor C4 is connected between the VC1 signal pin and a VSS signal pin arranged in the battery management unit U1, and a capacitor C3 is connected with a capacitor C4 in series to form a voltage sampling circuit and a current balancing circuit; a resistor R15 is arranged between the cathode of the B1 battery and a PACK _ n signal port, one end of the resistor R15 is connected with a SENSEP signal pin arranged in the battery management unit U1 in a matching way, and the other end of the resistor R15 is connected with a SENSEN signal pin arranged in the battery management unit U1 in a matching way; a resistor R13 is arranged between the SENSEP signal pin and a VSS signal pin of a grounding signal of the battery management unit U1, and a resistor R14 is arranged between the SENSEN signal pin and a PACK _ n signal port; a capacitor C5 is connected between the SENSEP signal pin and the SENSEN signal pin, and the capacitor C5 is a differential mode capacitor, so that a sampling circuit is formed; the battery management unit U1 is provided with a TSI signal pin, the TSI signal pin is provided with a resistor R16, and the resistor R16 is an NTC resistor and forms a temperature detection circuit.
The charge storage capacity of the capacitor C1 and the capacitor C2 is 1UF, and the charge storage capacity of the capacitor C3, the capacitor C4 and the capacitor C5 is 0.1 UF; the resistor R1 is equal to 300 omega, the resistors R2, R6 and R9 are equal to 10^6 omega, the resistors R3, R4, R5, R7, R8 and R10 are equal to 4700 omega, the resistors R11, R12, R13 and R14 are equal to 100 omega, the resistor R15 is equal to 0.001 omega, and the resistor R16 is equal to 10000 omega.
The battery management unit U1 is divided into a charging mode and a discharging mode, when the voltage value of the SENSEP signal pin is greater than that of the SENSEN signal pin, the system is in the charging mode, and when the voltage value of the SENSEP signal pin is less than that of the SENSEN signal pin, the system is in the discharging mode, the battery management unit U1 has three different charging stages in the charging mode, namely a pre-charging stage, a constant-current charging stage and a constant-voltage charging stage, and voltage thresholds entering the three different charging stages respectively correspond to a pre-charging voltage V1, a constant-current charging voltage V2 and a constant-voltage charging voltage V3.
In case one, when the VBAT battery voltage is less than the pre-charge voltage V1 set by the system, the working flow at this time is:
first, the CHS signal pin of the battery management unit U1 detects that a charger is inserted into the battery charging interface J2.
The battery charging interface J2 passes through the schottky diode D1, and the DSG signal in the battery management unit U1 outputs a high level, the voltage of the gate relative to the source in the NMOS transistor Q3 is greater than the turn-on threshold voltage of the NMOS transistor Q3, and the NMOS transistor Q3 is turned on.
The PCHG signal in the battery management unit U1 is output at low level, the PMOS tube Q1 is conducted, the CHG signal in the battery management unit U1 is output at low level, and the NMOS tube Q2 is disconnected; after the PMOS tube Q1 is conducted, the battery B1 and the battery B2 are pre-charged through the current-limiting resistor R1 and the three-terminal fuse F1.
In case two, when the VBAT battery voltage is greater than the constant-current charging voltage V2 set by the system and is less than the constant-voltage charging voltage V3, the work flow at this time is:
first, the CHS signal pin of the battery management unit U1 detects that a charger is inserted into the battery charging interface J2.
The battery charging interface J2 passes through the schottky diode D1, and the DSG signal in the battery management unit U1 outputs a high level, the voltage of the gate relative to the source in the NMOS transistor Q3 is greater than the turn-on threshold voltage of the NMOS transistor Q3, and the NMOS transistor Q3 is turned on.
The PCHG signal in the battery management unit U1 is output high and the PMOS transistor Q1 is turned off.
The CHG signal in the battery management unit U1 is output at a high level, the voltage of a gate relative to a source electrode in the NMOS tube Q2 is larger than the conduction threshold voltage of the NMOS tube Q2, the NMOS tube Q2 is conducted, after the magnitude of constant current charging current is determined through setting in a software program, the batteries B1 and B2 are subjected to constant current charging through a three-terminal fuse F1, when the battery management unit U1 detects that the charging current is too large, the battery management unit U1 adjusts the output voltages of the CHG signal and the DSG signal, the Vgs voltage difference of the NMOS tubes Q2 and Q3 is reduced, the path impedance is increased, and the current is reduced. In the constant current charging stage, the charging current in the battery module has the largest and basically stable current value in the whole charging process, and the charging voltage continuously rises.
In case three, when the VBAT battery voltage is greater than the constant voltage charging voltage V3 set by the system, the work flow at this time is:
first, the CHS signal pin of the battery management unit U1 detects that a charger is inserted into the battery charging interface J2.
The battery charging interface J2 passes through the schottky diode D1, and the DSG signal in the battery management unit U1 outputs a high level, the voltage of the gate relative to the source in the NMOS transistor Q3 is greater than the turn-on threshold voltage of the NMOS transistor Q3, and the NMOS transistor Q3 is turned on.
The PCHG signal in the battery management unit U1 is output high and the PMOS transistor Q1 is turned off.
The CHG signal in the battery management unit U1 is output at a high level, the voltage of a gate in an NMOS tube Q2 relative to a source is larger than the conduction threshold voltage of an NMOS tube Q2, the NMOS tube Q2 is conducted, after the magnitude of constant current charging current is determined through the setting in a software program, the batteries B1 and B2 are subjected to constant current charging through a three-terminal fuse F1, when the battery management unit U1 detects that the charging current is too large, the battery management unit U1 adjusts the output voltages of the CHG signal and the DSG signal, the Vgs voltage difference of the NMOS tube Q2 and the Q3 is reduced, the path impedance is increased, and the current is reduced; in the constant voltage charging stage, the charging current in the battery module is continuously reduced, and the charging voltage has the maximum voltage value and is basically stable in the whole charging process.
The charging current of the three charging conditions is detected and controlled by a current sampling circuit; the battery management unit U1 detects the voltage at the two ends of the resistor R15 and divides the voltage by the resistance value of the resistor R15 to calculate the current, and then adjusts the output voltage of the DSG signal, the CHG signal and the PCHG signal in the battery management unit U1 to change the voltage value of the grid electrode relative to the source electrode in the MOS tube, thereby adjusting the path impedance and controlling the current of the whole system; when the voltage value of the SENSEP signal pin is larger than that of the SENSEN signal pin, the system is in a charging mode.
Working process of the discharging mode:
the battery discharge interface J1 is in load contact with the battery management unit U1, and detects whether a load is connected through a PRES signal pin in the battery management unit U1.
The SDA signal port and the SCL signal port in the battery discharging interface J1 communicate with the SDA signal pin and the SCL signal pin in the battery management unit U1 through the I2C communication interface of the load, and parameter setting, electric quantity display control and the like are carried out.
In the discharging mode, the PCHG signal in the battery management unit U1 is output at a high level, and the PMOS transistor Q1 is turned off.
The battery pack U4 outputs a high level through the three-terminal fuse F1 and the CHG signal in the battery management unit U1, the voltage of the gate relative to the source in the NMOS tube Q2 is larger than the conduction threshold voltage of the NMOS tube Q2, and the NMOS tube Q2 is conducted.
The DSG signal in the battery management unit U1 outputs high level, the voltage of the grid electrode relative to the source electrode in the NMOS tube Q3 is larger than the conduction threshold voltage of the NMOS tube Q3, the NMOS tube Q3 is conducted, and the battery is discharged to a load through a battery discharge interface J1.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the utility model as defined by the appended claims.
Claims (8)
1. An external battery module supporting charging and discharging of different ports comprises a battery management unit U1, a battery PACK U4, a Schottky diode D1, a power tube U2, a battery charging interface J2 and a battery discharging interface J1, and is characterized in that a PACK _ P signal port and a PACK _ N signal port are arranged on the battery discharging interface J1, a CHG signal port and a PACK _ N signal port are arranged on the battery charging interface J2, the CHG signal port is connected with the PACK _ P signal port through the Schottky diode D1, the PACK _ N signal port is connected with the PACK _ N signal port, and a PRES signal port, a PRES signal port and an SCL signal port are further arranged in a battery discharging interface SDA J1; a CHS signal pin arranged in the battery management unit U1 is connected with a PACK _ P signal port in a matching way; the PRES signal port, the SDA signal port and the SCL signal port respectively correspond to a PRES signal pin, an SDA signal pin and an SCL signal pin which are arranged in the battery management unit U1; an I2C communication interface is arranged between the SCL signal pin and the SCL signal port, and between the SDA signal pin and the SDA signal port; the battery management unit U1 is all around still be provided with one-level protection circuit, secondary protection circuit, sampling circuit, group battery, communication module, temperature detection circuit, current equalizer circuit and voltage sampling circuit.
2. The external battery module supporting different charging and discharging ports according to claim 1, wherein the PACK _ P signal port is connected with an NMOS transistor Q3 in a matching manner, an NMOS transistor Q4 is arranged between the source of the NMOS transistor Q3 and the PACK _ P signal port, and the grid of the NMOS transistor Q4 is provided with a resistor R10 and is grounded; the grid electrode of an NMOS tube Q3 is connected with a DSG signal pin arranged in a battery management unit U1, a resistor R8 is arranged between the grid electrode of an NMOS tube Q3 and the DSG signal pin, a resistor R9 is arranged between the source electrode of the NMOS tube Q3 and the drain electrode of the NMOS tube Q4, one side of the drain electrode of the NMOS tube Q3 is respectively connected with the source electrode of a PMOS tube Q1 and the drain electrode of an NMOS tube Q2, the grid electrode of the PMOS tube Q1 is connected with a PCHG signal pin arranged in the battery management unit U1, a resistor R4 is arranged between the grid electrode of the PMOS tube Q1 and the PCHG signal pin, the source electrode of the PMOS tube Q1 is connected with a VCC signal pin arranged in the battery management unit U1, a resistor R7 is arranged between the source electrode of the PMOS tube Q1 and the VCC signal pin, and a resistor R6 is arranged between the source electrode of the PMOS tube Q1 and the gate electrode; the grid electrode of the NMOS tube Q2 is connected with a CHG signal pin arranged in the battery management unit U1, a resistor R3 is arranged between the grid electrode of the NMOS tube Q2 and the CHG signal pin, and a resistor R2 is arranged on a connecting line between the resistor R3 and the source electrode of the NMOS tube Q2; a resistor R1 is arranged between the resistor R2 and the drain electrode of the PMOS tube Q1, and a capacitor C1 and a capacitor C2 are arranged between the resistor R2 and the resistor R9; the PMOS tube Q1, the NMOS tube Q2, the NMOS tube Q3, the NMOS tube Q4, the capacitor C1 and the capacitor C2 jointly form a primary protection circuit.
3. The external battery module supporting different charging and discharging ports as claimed in claim 2, wherein a three-terminal fuse F1 is disposed in the primary protection circuit towards the source of the NMOS transistor Q2; an NMOS tube Q5 is arranged at the phase-3 end of the three-end FUSE F1, a grid electrode of the NMOS tube Q5 is connected with a FUSE signal pin arranged in the battery management unit U1, and a resistor R5 is arranged between the grid electrode of the NMOS tube Q5 and a grounding end on a source electrode of the NMOS tube Q5; the NMOS tube Q5 and the three-terminal fuse F1 jointly form a secondary protection circuit.
4. The external battery module supporting charging and discharging of different ports as claimed in claim 3, wherein the battery pack U4 is disposed at the phase 1 terminal of the three-terminal fuse F1, the VBAT signal pin is disposed in the battery management unit U1, and the VBAT signal pin is disposed between the phase 1 terminal of the three-terminal fuse F1 and the positive electrode of the battery pack U4; the battery pack U4 is divided into two groups of batteries B2 and B1, the positive pole of the battery B2 is connected with a VC2 signal pin arranged in a battery management unit U1 in a matching way, and a resistor R11 is arranged between the positive pole of the battery B2 and the VC2 signal pin arranged in the battery management unit U1; the positive electrode of the B1 battery is connected with a VC1 signal pin arranged in the battery management unit U1 in a matching way, and a resistor R12 is arranged between the positive electrode of the B1 battery and a VC1 signal pin arranged in the battery management unit U1; a capacitor C3 is connected between the VC2 signal pin and the VC1 signal pin, a capacitor C4 is connected between the VC1 signal pin and a VSS signal pin arranged in the battery management unit U1, and a capacitor C3 is connected with a capacitor C4 in series to form a voltage sampling circuit and a current balancing circuit.
5. The external battery module supporting different charging and discharging ports according to claim 4, characterized in that a resistor R15 is arranged between the cathode of the B1 battery and the PACK _ n signal port, one end of the resistor R15 is connected with a SENSEP signal pin arranged in the battery management unit U1 in a matching manner, and the other end of the resistor R15 is connected with a SENSEN signal pin arranged in the battery management unit U1 in a matching manner; a resistor R13 is arranged between the SENSEP signal pin and a VSS signal pin of a grounding signal of the battery management unit U1, and a resistor R14 is arranged between the SENSEN signal pin and a PACK _ n signal port; a capacitor C5 is connected between the SENSEP signal pin and the SENSEN signal pin, and the capacitor C5 is a differential mode capacitor, so that a sampling circuit is formed.
6. The external battery module supporting different charging and discharging ports according to claim 5, wherein a TSI signal pin is arranged in the battery management unit U1, and a resistor R16 is arranged on the TSI signal pin; the resistor R16 is an NTC resistor and forms a temperature detection circuit.
7. The external battery module supporting different charging and discharging ports according to claim 1, wherein the battery management unit U1 is divided into a charging mode and a discharging mode, and when the voltage value of the SENSEP signal pin is greater than the voltage value of the SENSEN signal pin, the system is in the charging mode, and when the voltage value of the SENSEN signal pin is less than the voltage value of the SENSEN signal pin, the system is in the discharging mode.
8. The external battery module supporting different charging and discharging ports according to claim 6, wherein the charge storage amount of the capacitor C1 and the capacitor C2 is 1UF, and the charge storage amount of the capacitor C3, the capacitor C4 and the capacitor C5 is 0.1 UF; the resistor R1 is equal to 300 omega, the resistors R2, R6 and R9 are equal to 10^6 omega, the resistors R3, R4, R5, R7, R8 and R10 are equal to 4700 omega, the resistors R11, R12, R13 and R14 are equal to 100 omega, the resistor R15 is equal to 0.001 omega, and the resistor R16 is equal to 10000 omega.
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| CN202122433555.3U CN216134297U (en) | 2021-10-09 | 2021-10-09 | External battery module supporting charging and discharging different ports |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117154897A (en) * | 2023-10-30 | 2023-12-01 | 广东高普达集团股份有限公司 | Battery pack processing device and electronic equipment |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117154897A (en) * | 2023-10-30 | 2023-12-01 | 广东高普达集团股份有限公司 | Battery pack processing device and electronic equipment |
| CN117154897B (en) * | 2023-10-30 | 2024-04-09 | 广东高普达集团股份有限公司 | Battery pack processing device and electronic equipment |
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