CN216086648U

CN216086648U - Active combiner-divider with feed clock feeding function

Info

Publication number: CN216086648U
Application number: CN202122107295.0U
Authority: CN
Inventors: 沈金海; 徐海强
Original assignee: Nanjing Kongwei Communication Technology Co ltd
Current assignee: Nanjing Kongwei Communication Technology Co ltd
Priority date: 2021-09-02
Filing date: 2021-09-02
Publication date: 2022-03-18
Anticipated expiration: 2031-09-02

Abstract

The utility model relates to an active combiner-divider with feed clock function, which comprises: the device comprises an uplink combiner, an uplink amplifier, an uplink filter, a downlink amplifier, a downlink splitter, an LNB feeder, a constant temperature crystal oscillator and a feed clock switch. In the actual communication process, an uplink is formed by an uplink combiner, an uplink amplifier, an uplink filter, an LNB feeder and a constant temperature crystal oscillator; the downlink filter, the downlink amplifier, the downlink shunt, the LNB feeder and the constant temperature crystal oscillator form a downlink. In addition, the branching unit compensates the combination of signals and the attenuation value of a transmission link in an uplink and a downlink, and simultaneously effectively avoids the problem caused by the fact that a plurality of modems simultaneously provide the feed clocks.

Description

Active combiner-divider with feed clock feeding function

Technical Field

The utility model relates to an active shunt, in particular to an active combined shunt with a feed clock feeding function.

Background

Satellite communication terrestrial master stations often deploy multiple modems for multi-traffic communication. At an uplink transmitting end, transmitting ports of a plurality of modems are connected to an input port of an external BUC block converter after passing through a passive combiner; and at a downlink receiving end, an output port of the external LNB high-frequency head is connected to input ports of all the modems after passing through the passive splitter. In the actual use process, the combination of the transmitting ends of a plurality of modems can reduce the output signal power, and the signal output power is insufficient after entering the BUC block converter, so that the receiving signal-to-noise ratio of a remote station is reduced, and the link communication failure can be seriously caused. At a receiving end, the LNB tuner output signal is branched to reduce the input power of the modem, so that the received signal does not meet the receiving level range of the modem, thereby affecting the communication effect. In addition, if a plurality of modulation and demodulation exist at the transmitting end and the receiving end and simultaneously provide 10M feed clocks for the BUC block converter and the LNB high frequency head, the BUC block converter and the LNB high frequency head can not work normally, and link communication failure is caused. Furthermore, when multiple modems feed the BUC block converter and LNB tuner at the output and input, there is a risk of burning out the modems.

SUMMERY OF THE UTILITY MODEL

Utility model purpose: an active combiner-splitter with a feed clock function is provided, which is used for isolating a 10M feed clock and a feed of a transmitting end and a receiving end of each modem during operation, separately providing the feed and the 10M feed clock required by a BUC and an LNB, and simultaneously providing a fixed power gain to compensate signal attenuation caused by an uplink combiner and a downlink splitter, so as to solve the problems provided above.

The technical scheme is as follows: an active combiner-divider with a feed clock function specifically comprises:

an amplifier; the filter is connected with the amplifier and is used for filtering the received signal; a combiner connected with the amplifier for receiving the output signal of the external modem in the uplink and inputting the combined signal into the amplifier; the splitter is connected with the filter and used for receiving the output signal in the filter in a downlink and accessing an external modem receiving end after splitting; the constant temperature crystal oscillator is connected with the amplifier and the filter and is used for eliminating the harmonic wave of the signal and then combining the signal with the received signal and outputting the signal; the feed is connected with the constant-temperature crystal oscillator and used for converting the voltage of an external power supply and supplying power; the clock feed switch is connected with the constant temperature crystal oscillator and is used for providing a working 10M clock source for the BUC equipment in an uplink and the LNB equipment in a downlink; and the amplifier is used for receiving the combined signal output by the combiner in an uplink when being connected with the combiner and the filter, and inputting the signal into the filter for filtering after compensating the signal gain.

In a further embodiment, an uplink is formed by the uplink combiner, the uplink amplifier, the uplink filter, the LNB feeder and the constant temperature crystal oscillator; the downlink filter, the downlink amplifier, the downlink shunt, the LNB feeder and the constant temperature crystal oscillator form a downlink.

In a further embodiment, the input port of the combiner is connected with the signal output end of the external modem through a CL high-pass circuit, and is used for filtering out a direct-current voltage and a feed clock carried in the signal.

In a further embodiment, the amplifier is connected with the filter for removing out-of-band spurious harmonics, and further comprises a pi-failure circuit formed by a resistor R35, a resistor R36 and a resistor R37, wherein the pi-failure circuit is used for adjusting a link gain value; the capacitor C60, the inductor L11 and the capacitor C58 are electrically connected to form a high-pass filter for preventing the transmission clock from entering the output end of the amplifier.

In a further embodiment, the constant temperature crystal oscillator is further connected with two clock feed switches, and then connected with a low-pass filter circuit for eliminating the harmonic wave of the signal, and combining the processed signal with the received signal and outputting the combined signal.

In a further embodiment, in the downlink, a first high pass filter is formed by electrically connecting the capacitor C35, the inductor L4 and the capacitor C37, and is used for preventing the receiving terminal clock from entering the input terminal of the amplifier.

The resistor R47, the resistor R48 and the resistor R49 are electrically connected to form a pi-failure circuit for adjusting the gain value of the link.

Has the advantages that: the utility model provides an active combiner-divider with a feed clock function, which supports eight-transmitter and eight-receiver and has the feed clock function, can isolate 10M feed clocks and feeds of a transmitting end and a receiving end of each modem during working, independently provides the feeds and 10M feed clocks required by a BUC and an LNB, and simultaneously provides a fixed power gain to compensate signal attenuation caused by an uplink combiner and a downlink divider. Not only compensates the attenuation values of the combination of signals and the transmission link in the uplink and the downlink, but also effectively avoids the problem caused by the simultaneous supply of the feed clocks by a plurality of modems when the single feed clock is provided.

Drawings

Fig. 1 is a schematic diagram of the novel active combiner-splitter.

Fig. 2 is a schematic diagram of the uplink signal combining part of the present invention.

Fig. 3 is a schematic diagram of the output part of the novel uplink combining circuit.

Fig. 4 is a schematic circuit diagram of the uplink clock portion of the present invention.

Fig. 5 is a schematic diagram of a downlink receiving part of the present invention.

Fig. 6 is a circuit schematic diagram of a portion of the novel downlink receive feed clock.

Fig. 7 is a schematic diagram of a downlink reception splitting part of the present novel invention.

Fig. 8 is a schematic diagram of the power supply portion switching of the novel device.

Fig. 9 is a schematic diagram of a part of the structure of the novel clock.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the utility model.

The embodiment provides an active combiner-splitter with a feed clock function, aiming at the condition that a BUC block converter and an LNB high-frequency head are not working normally, which causes link communication failure, and when a plurality of modems provide feed for the BUC block converter and the LNB high-frequency head at an output end and an input end, the condition that the risk of burning the modems occurs, the feed and the 10M feed clock required by the BUC and the LNB are provided separately by isolating the 10M feed of the sending end and the receiving end of each modem, and meanwhile, a fixed power gain is provided to compensate signal attenuation caused by an uplink combiner and a downlink splitter. The specific technical scheme is as follows:

as shown in fig. 1, the active combiner-splitter with the function of feeding a clock includes: the device comprises an uplink combiner, an uplink amplifier, an uplink filter, a downlink amplifier, a downlink splitter, an LNB feeder, a constant temperature crystal oscillator and a feed clock switch. In the actual communication process, an uplink is formed by an uplink combiner, an uplink amplifier, an uplink filter, an LNB feeder and a constant temperature crystal oscillator; the downlink filter, the downlink amplifier, the downlink shunt, the LNB feeder and the constant temperature crystal oscillator form a downlink.

In the preferred embodiment, the type of the uplink and downlink combiner-divider is selected as SEPS-8-272+, the corresponding data is converted into a pair of eight, and the selected frequency range is 700 MHz-2700 MHz; the model of the uplink and downlink filter is selected to be LFCN-2250, and the filtering range is selected to be DC-2200 MHz; the model of the uplink and downlink amplifier is ADL5611, the frequency range is 30 MHz-6 GHz, and the fixed gain is 22.2 dB. The model of the LNB feeder is LNBH25PQR, and the output voltage range is 13-21V; the model of the 10M constant temperature crystal oscillator is JTM 2006; 10M feed clock switch HMC 349A.

In the uplink of actual communication, the output signal of the external modem is connected to the input end of the uplink combiner, after being combined and output, the signal gain is compensated by the fixed gain amplifier, then the signal gain is filtered by the low pass filter, and the signal gain is combined with the uplink feed clock and output.

In the downlink of actual communication, an LNB output signal is accessed into a downlink low-pass filter, then is amplified by a power amplifier, compensates the signal attenuation on a receiving link, and then is accessed into the receiving end of an external modem after being split by an eight-splitting splitter. In addition, the provision of the clock and LNB feed at the downlink input ensures that the external LNB can operate correctly.

IN a further embodiment, IN an uplink during actual communication, as shown IN fig. 2, an external modem outputs a signal TX1_ IN, which is passed through a CL high-pass circuit to filter dc voltage and 10M feed clock possibly carried IN the signal, so as to obtain a signal TX1_ B, and the signal TX1_ B is input into the uplink combiner through an input port, and the other 7 signals TX2_ IN to TX8_ IN are similarly processed. The type of the upper combiner-divider is selected to be SEPS-8-272+, and the combiner can be used as an 8-path combiner, and the frequency range of the combiner-divider is 700 MHz-2700 MHz. And 8 paths of signals TX1_ B-TX 8_ B are connected into 8 input ends of the uplink combiner SEPS-8-272+ for combination and then are converted into signals TX _ B to be output.

In a further embodiment, as shown in fig. 3, which is a schematic diagram of the combined output part of the uplink schematic diagram, the combined signal TX _ B of the uplink combiner/splitter SEPS-8-272+ is compensated by the fixed gain amplifier ADL5611 for signal combining attenuation, and the output signal of the fixed gain amplifier is then passed through the low pass filter LFCN-2250 for removing out-of-band spurs and harmonics. In addition, the resistor R35, the resistor R36 and the resistor R37 form a pi-failure circuit for adjusting the link gain value. Capacitor C60, inductor L11 and capacitor C58 form a first high pass filter that prevents the transmit 10M clock from entering the amplifier output. Where ADL5611 is a high dynamic gain amplifier with a fixed gain of 22 dB.

In a further embodiment, as shown in fig. 4, a schematic diagram of a part of a circuit of an uplink intermediate clock is shown, wherein an output of the constant temperature crystal oscillator 10M passes through two HMC349A switches, and then is combined with a transmission signal after eliminating a harmonic of a 10M signal through a low-pass circuit, and is transmitted to an external BUC unit.

In a further embodiment, in the downlink during actual communication, as shown in fig. 5, the external LNB output signal is connected to a downlink low pass filter, wherein a first high pass filter is formed by a capacitor C35, an inductor L4 and a capacitor C37, and is used for preventing the receiving terminal 10M from feeding clock into the amplifier input terminal. The resistor R47, the resistor R48 and the resistor R49 form a pi-failure circuit for adjusting the gain value of the link. When the signal is attenuated by the compensation signal branch circuit of the fixed gain amplifier ADL5611, the signal is input into a low-pass filter LFCN-2250 for filtering out the stray outside the band.

In a further embodiment, as shown in fig. 6, a schematic diagram of a part of a downlink middle-feed clock circuit is shown, wherein after the output of the constant temperature crystal oscillator 10M passes through two HMC349A switches, the output of the constant temperature crystal oscillator passes through a low-pass circuit, and then is combined with a transmission signal after eliminating the harmonic of the 10M signal, and is sent to a fixed gain amplifier ADL 5611.

IN a further embodiment, as shown IN fig. 7, after compensating for the signal attenuation on the receiving link IN the downlink, the received signal RX _ B is split into eight signals RX1_ B-RX 8_ B through an eight-split splitter, and the eight signals are passed through a CL high-pass circuit to obtain corresponding signals RX2_ IN-RX 8_ IN, and then accessed to the external modem receiving end through the output port RX1_ RX 8.

In a further embodiment, as shown in fig. 8, the external input power is 12V, and the external power voltage is converted to 5V for power supply by the LT1529 LDO power regulator. In addition, the model of the LNB feeder is selected to be LNBH25PQR, and the output voltage range of the LNB feeder is 13-21V.

In a further embodiment, as shown in fig. 9, the 10M oven crystal is model JTM2006, and the 10M signal output is used to provide a feed clock for transceiving.

In conclusion, compared with the prior art, the utility model has the following remarkable effects:

the multi-channel parallel port multi-input multi-output dual-input multi-output modem has the function of feeding a clock, can isolate 10M feeding clocks and feeding feeds of a transmitting end and a receiving end of each modem during working, independently provides the feeding clocks and the 10M feeding clocks needed by the BUC and the LNB, and simultaneously provides fixed power gain to compensate signal attenuation caused by an uplink combining path and a downlink splitting path. Not only compensates the attenuation values of the combination of signals and the transmission link in the uplink and the downlink, but also effectively avoids the problem caused by the simultaneous supply of the feed clocks by a plurality of modems when the single feed clock is provided.

As noted above, while the present invention has been shown and described with reference to certain preferred embodiments, it is not to be construed as limited thereto. Various changes in form and detail may be made therein without departing from the spirit and scope of the utility model as defined by the appended claims.

Claims

1. An active combiner-divider with feed clock function is characterized by comprising:

an amplifier;

the filter is connected with the amplifier and is used for filtering the received signal;

a combiner connected with the amplifier for receiving the output signal of the external modem in the uplink and inputting the combined signal into the amplifier;

the splitter is connected with the filter and used for receiving the output signal in the filter in a downlink and accessing an external modem receiving end after splitting;

the constant temperature crystal oscillator is connected with the amplifier and the filter and is used for eliminating the harmonic wave of the signal and then combining the signal with the received signal and outputting the signal;

the feed is connected with the constant-temperature crystal oscillator and used for converting the voltage of an external power supply and supplying power;

the clock feed switch is connected with the constant temperature crystal oscillator and is used for providing a working 10M clock source for the BUC equipment in an uplink and the LNB equipment in a downlink;

and the amplifier is used for receiving the combined signal output by the combiner in an uplink when being connected with the combiner and the filter, and inputting the signal into the filter for filtering after compensating the signal gain.

2. An active combiner-divider with feed clock function according to claim 1, characterized in that: an uplink is formed by the uplink combiner, the uplink amplifier, the uplink filter, the LNB feeder and the constant temperature crystal oscillator; the downlink filter, the downlink amplifier, the downlink shunt, the LNB feeder and the constant temperature crystal oscillator form a downlink.

3. An active combiner-divider with feed clock function according to claim 1, characterized in that:

and the input port of the combiner is connected with the signal output end of the external modem through a CL high-pass circuit and is used for filtering direct-current voltage and a feed clock carried in the signal.

4. An active combiner-divider with feed clock function according to claim 1, characterized in that:

when the amplifier is connected with the filter for carrying out-of-band stray harmonic wave removal, the amplifier also comprises a pi attenuation circuit which is composed of a resistor R35, a resistor R36 and a resistor R37 and is used for adjusting a link gain value; the capacitor C60, the inductor L11 and the capacitor C58 are electrically connected to form a high-pass filter for preventing the transmission clock from entering the output end of the amplifier.

5. An active combiner-divider with feed clock function according to claim 1, characterized in that:

the constant temperature crystal oscillator is further connected with two feed clock switches and then connected with a low-pass filter circuit for eliminating the harmonic wave of the signal and combining the processed signal with the received signal and then outputting the combined signal.

6. An active combiner-divider with feed clock function according to claim 1, characterized in that:

in a downlink, a capacitor C35, an inductor L4 and a capacitor C37 are electrically connected to form a first high-pass filter for preventing a receiving end feed clock from entering an input end of the amplifier;