CN216084865U - Chip module - Google Patents
Chip module Download PDFInfo
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- CN216084865U CN216084865U CN202122238423.5U CN202122238423U CN216084865U CN 216084865 U CN216084865 U CN 216084865U CN 202122238423 U CN202122238423 U CN 202122238423U CN 216084865 U CN216084865 U CN 216084865U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
Abstract
The embodiment of the application discloses a chip component. The chip assembly includes: a chip, a printed circuit board, and a wiring substrate; a chip bonding pad is arranged on the top surface of the chip; the top surface of the printed circuit board is provided with a bonding pad; the bottom surface of the wiring substrate is provided with a first substrate pad and a second substrate pad which are electrically connected through a conducting circuit of the wiring substrate; the printed circuit board comprises a groove area, and the chip is positioned in the groove area; the chip bonding pad is electrically connected with the first substrate bonding pad through the conductive bonding layer; the bonding pad is electrically connected with the second substrate pad through the conductive adhesive layer. The chip assembly provided by the embodiment of the application has the advantages of being small, light and thin, and the manufacturing cost is low.
Description
Technical Field
The embodiment of the application relates to the technical field of chip assembly, in particular to a chip assembly.
Background
As electronic products are increasingly miniaturized and thinned, internal structures of the electronic products become more compact. Currently, in the semiconductor industry, Wire Bonding is mostly used to realize electrical connection between a chip and an FPC (Flexible Printed Circuit board), but this processing method is not favorable for reducing the size of the chip assembly, and also causes the manufacturing cost of the chip assembly to be very high.
SUMMERY OF THE UTILITY MODEL
The embodiment of the application provides a chip assembly, which can reduce the manufacturing cost of the chip assembly while realizing the miniaturization and the lightness and thinness of the chip assembly.
An embodiment of the present application provides a chip assembly, including: a chip, a printed circuit board, and a wiring substrate; a chip bonding pad is arranged on the top surface of the chip; the top surface of the printed circuit board is provided with a bonding pad; a first substrate pad and a second substrate pad are arranged on the bottom surface of the wiring substrate, and the first substrate pad and the second substrate pad are electrically connected through a conducting circuit of the wiring substrate; the printed circuit board comprises a groove area, and the chip is positioned in the groove area; the chip bonding pad is electrically connected with the first substrate bonding pad through a conductive bonding layer; the bonding pad is electrically connected with the second substrate pad through the conductive adhesive layer.
The chip is placed in the groove area of the printed circuit board and is inversely installed on the bottom surface of the wiring substrate, so that the miniaturization, the lightness and the thinness of the chip assembly are realized. The chip is electrically connected to the printed circuit board by using the wiring substrate, the processing technology is simple, the manufacturing cost is low, and the stability of the whole structure is high.
Optionally, a safety distance greater than 0.1mm is provided between the bottom surface of the chip and the bottom surface of the groove region.
Optionally, a spacing between an edge of the chip and an edge of the recessed area is greater than 0.17 mm.
Optionally, a surface of the chip pad is plated with a layer of nickel gold.
Optionally, the chip bonding pads are connected with the first substrate bonding pads in a one-to-one correspondence manner; the bonding pads are connected with the second substrate pads in a one-to-one correspondence mode.
Optionally, the wiring substrate further includes: a substrate layer and a reinforcing layer; the bottom surface of substrate layer laminate in the top surface of strengthening layer, the substrate layer is provided with the opening district, the opening district with the top surface of strengthening layer constitutes the recess district.
Optionally, the conductive bonding layer is a tin paste layer, a conductive silver paste layer or a silver paste layer printed by a steel mesh printing process.
Optionally, the top surface of the conductive adhesive layer and the top surface of the conductive adhesive layer are at the same level.
Optionally, the chip further comprises: an active identification area for receiving an optical signal; the effective identification area is arranged on the top surface of the chip, and the chip bonding pad is arranged outside the effective identification area.
Optionally, the wiring substrate is a light-transmissive wiring substrate.
Drawings
One or more embodiments are illustrated by the corresponding figures in the drawings, which are not meant to be limiting. The following description refers to the accompanying drawings in which the same numbers in different drawings identify the same or similar elements. The drawings in the drawings are not to scale unless specifically noted.
Fig. 1 is a schematic cross-sectional view of a chip assembly according to an embodiment of the present disclosure;
FIG. 2 is a schematic view of a processing step of the method of fabricating the chip assembly shown in FIG. 1;
FIG. 3 is a schematic cross-sectional view of another chip assembly provided in an embodiment of the present application;
FIG. 4 is a schematic view of a processing step of the method of fabricating the chip assembly shown in FIG. 3;
fig. 5 is a schematic cross-sectional view of another chip assembly provided in an embodiment of the present application;
FIG. 6(a-d) is a schematic diagram of the processing steps of the method of fabricating the chip assembly shown in FIG. 5;
fig. 7 is a schematic cross-sectional view of another chip assembly provided in an embodiment of the present application;
fig. 8(a-d) is a schematic view of the processing steps of the method of fabricating the chip assembly shown in fig. 7.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
Unless a specified order is explicitly stated in the context of the present application, the process steps described herein may be performed in a different order than specified, i.e., each step may be performed in the specified order, substantially simultaneously, in the reverse order, or in a different order.
Furthermore, the terms "first," "second," and the like, are used solely to distinguish between similar objects and are not intended to indicate or imply relative importance or to implicitly indicate a number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature.
Fig. 1 is a schematic cross-sectional view of a chip assembly according to an embodiment of the present disclosure. The chip assembly 10 includes: a chip 101, a printed circuit board 102, and a wiring substrate 103. Wherein, a chip pad 104 is disposed on the top surface of the chip 101; the top surface of the printed circuit board 102 is provided with a bonding pad 105; the bottom surface of the wiring substrate is provided with a first substrate pad 106a and a second substrate pad 106b, and the first substrate pad 106a and the second substrate pad 106b are electrically connected by a conductive line 107 of the wiring substrate 103. The printed circuit board 102 includes a recessed area within which the chip 101 is located. The chip pad 104 is electrically connected to the first substrate pad 106a through the conductive adhesive layer 108; the bonding pad 105 is electrically connected to the second substrate pad 106b through the conductive adhesive layer 109.
The chip assembly provided by the embodiment of the application has the advantages that the chip and the printed circuit board are electrically connected through the wiring substrate to form the inverted structure, the structural stability is high, and in addition, as the traditional chip packaging process such as Wire Bonding (Wire Bonding) is not needed, the Bonding Wire is not needed to be additionally arranged to realize the electrical connection between the chip Bonding pad and the Bonding pad of the printed circuit board, and the volume of the external packaging material of the chip is not needed to be increased in order to ensure the stability of the structure and the performance of the Bonding Wire; the groove area is arranged on the printed circuit board, and the chip is placed in the groove area, so that the section height of the chip assembly is reduced, and the miniaturization and the lightness and thinness of the chip assembly are realized; in addition, the bonding wires used in the conventional wire bonding process are usually gold wires, and the chip assembly provided by the embodiment of the application does not need to use expensive gold wires and DB machines, so that the cost can be significantly reduced in comparison.
Specifically, the chip 101 may be a semiconductor die (die), the chip may be flip-chip Mounted on a wiring substrate by Surface Mount Technology (SMT), and the chip pads are connected to the substrate pads in a one-to-one correspondence. In order to ensure that the chip can be stably flip-chip mounted on the wiring substrate, it is necessary to keep the surface of the wiring substrate flat.
Wherein, the conductive bonding layer can be a tin paste layer, a conductive silver adhesive layer or a silver paste layer; firstly, a conductive adhesive (tin paste, conductive silver adhesive or silver paste) can be printed on the surface of a chip bonding pad connected with a first substrate bonding pad through a steel screen printing process, and then the conductive adhesive is cured by heating; because steel screen printing process's printing precision is higher, can print the tin cream that length or width are less than 50 mu m, conductive silver glue or silver thick liquid fritter, and printing thickness is about 50 mu m, consequently, its precision can guarantee that tin cream, conductive silver glue or silver thick liquid fritter are located corresponding chip pad, and can not spill over the region of chip pad, lead to the material interconnection between the different chip pads to avoid the risk of taking place the short circuit between the chip pad.
Specifically, when the solder paste is selected as the conductive adhesive, the solder paste can be solidified by adopting a vacuum reflow soldering process at 180-260 ℃; when the conductive silver adhesive is selected as the conductive adhesive, the conductive silver adhesive can be cured by heating at the high temperature of 150-200 ℃; when silver paste is selected as the conductive adhesive, the silver paste can be solidified at a high temperature of 150-220 ℃ through a sintering process; thereby, a close and stable electrical connection between the chip and the wiring substrate can be formed.
The Conductive adhesive layer can be made of Anisotropic Conductive Film (ACF) to realize electrical conduction in the vertical direction and insulation in the horizontal direction; the electric connection between the printed circuit board and the wiring substrate is realized through the conductive adhesive layer, and the electric conduction between the chip and the power supply can be further realized. The line width of the conductive line of the wiring substrate may be 10 μm at the minimum.
In this embodiment, the Printed Circuit board 102 may be a Flexible Printed Circuit (FPC) including a substrate layer 102a and a reinforcing layer 102 b. When the printed circuit board 102 is grooved, the base material layer 102a may be formed in a window structure. Specifically, the base material layer 102a may be a Polyimide (PI) layer; the reinforcing layer 102b may be a reinforcing steel plate, and the minimum thickness of the reinforcing steel plate may be 0.1 mm.
As a possible implementation, a safety distance of more than 0.1mm is provided between the bottom surface of the chip 101 and the bottom surface of the recess region of the printed circuit board 102.
When the printed circuit board 102 is a flexible circuit board, the safety distance is greater than 0.1mm between the bottom surface of the chip 101 and the top surface of the stiffening layer 102b of the flexible circuit board. Through setting up safe distance can effectively avoid leading to the chip cracked because of external force strikes at the in-process of encapsulation laminating.
As a possible implementation, the distance between the edge of the chip 101 and the edge of the recessed area of the printed circuit board 102 is greater than 0.17 mm.
In order to ensure that the chip can still be arranged in the recess area of the printed circuit board in the presence of extreme tolerances, a distance can be provided between the edge of the chip and the edge of the recess area. The limit tolerance may include a db (die bonding) positioning tolerance, a chip contour machining tolerance and a chip position tolerance, and a printed circuit board recess area contour machining tolerance and a printed circuit board position tolerance.
As a possible implementation, the surface of the chip pad 104 is plated with a layer of nickel-gold 110.
When the chip bonding pad is made of aluminum, in order to enhance the electrical interconnection between the chip bonding pad and the first substrate bonding pad, a layer of nickel and gold can be plated on the surface of the chip bonding pad in a chemical mode, so that the phenomenon that a non-conductive aluminum oxide film is formed due to the oxidation of aluminum in the air is avoided, and the electrical connection performance between the chip bonding pad and the first substrate bonding pad is further influenced. Specifically, the thickness of the nickel layer may be about 2 μm.
As a possible embodiment, in order to ensure that the wiring substrate can be connected between the chip pad and the bonding pad in a flat manner, the top surface of the conductive adhesive layer 108 may be disposed at the same level as the top surface of the conductive adhesive layer 109.
As a possible implementation, the chip 101 further includes an Active Area (AA Area) 111 for receiving an optical signal; the effective identification area 111 is disposed on the top surface of the chip 101, and the chip pad 104 is disposed outside the effective identification area 111; the wiring substrate 103 is a light-transmitting wiring substrate.
When the chip is an optical chip which can be used for imaging, such as an image sensor chip or a fingerprint identification chip, the top surface of the chip is provided with an effective identification area for receiving an optical signal reflected by an object to be detected so as to perform image or fingerprint identification; for example, the effective identification area 111 may be a pixel array area. In order not to block the optical signal, the wiring substrate may be made of a light-transmitting material, and specifically, the light-transmitting wiring substrate may be made of a transparent substrate material such as a glass substrate.
As shown in fig. 2, a schematic view of processing steps of the manufacturing method of the chip assembly shown in fig. 1 specifically includes the following steps:
in the processing step (a), the first substrate pad 106a and the second substrate pad 106b are provided on the bottom surface of the wiring substrate 103, and the first substrate pad 106a and the second substrate pad 106b are electrically connected through the conductive line 107 of the wiring substrate 103.
In the processing step (b), the conductive adhesive layer 108 is printed on the surface of the first substrate pad 106a, and the printed circuit board 103 is grooved to form a groove region.
Specifically, the conductive adhesive can be printed on the surface of the chip pad connected with the first substrate pad through a steel screen printing process, and then the conductive adhesive is cured by heating, wherein the conductive adhesive can comprise tin paste, conductive silver paste or silver paste and the like.
In the processing step (c), the chip 101 is disposed in the recessed area of the wiring substrate 102, and the chip pad 104 is electrically connected to the first substrate pad 106a through the conductive adhesive layer 108, and the conductive adhesive layer is cured by heating.
When the tin paste is selected as the conductive adhesive, the tin paste can be solidified by adopting a vacuum reflow soldering process at 180-260 ℃; when the conductive silver adhesive is selected as the conductive adhesive, the conductive silver adhesive can be cured by heating at the high temperature of 150-200 ℃; when silver paste is selected as the conductive adhesive, the silver paste can be solidified at a high temperature of 150-220 ℃ through a sintering process; thereby, a close and stable electrical connection between the chip and the wiring substrate can be formed.
Specifically, the chip may be flip-chip mounted on the wiring substrate by a surface mounting technique, and the chip pads are connected to the first substrate pads in a one-to-one correspondence. In order to ensure that the chip can be stably flip-chip mounted on the wiring substrate, it is necessary to keep the surface of the wiring substrate flat.
In the processing step (d), the conductive adhesive layer 109 is attached to the surface of the second board pad 106 b.
In the processing step (e), the bonding pads 105 of the printed circuit board 102 are electrically connected to the second substrate pads 106b through the conductive adhesive layer 109.
Specifically, when the printed circuit board 102 is a flexible circuit board, the bonding pad 105 is disposed on the surface of the base material layer 102a, and the base material layer 102a is electrically connected to the second substrate pad 106b through the conductive adhesive layer 109.
In the processing step (f), the reinforcing layer 102b is bonded to the bottom surface of the base layer 102 a.
The reinforcing layer may be a reinforcing steel sheet. The strengthening layer is added at the bottom of the chip assembly, so that the reliability and the bending resistance of the chip assembly can be improved.
The manufacturing method of the chip assembly provided by the embodiment of the application is not only beneficial to realizing the miniaturization and the lightness and thinness of the chip assembly, but also can realize full-page large-batch operation in various processes, and is high in manufacturing efficiency and low in manufacturing cost.
Fig. 3 is a schematic cross-sectional view of another chip assembly provided in the embodiments of the present application. The chip assembly 20 includes: chip 201, printed circuit board 202, and wiring substrate 203. Wherein, a chip pad 204 is disposed on the top surface of the chip 201; the top surface of the printed circuit board 202 is provided with bonding pads 205; the bottom surface of the wiring substrate is provided with a first substrate pad 206a and a second substrate pad 206b, and the first substrate pad 206a and the second substrate pad 206b are electrically connected by a conductive line 207 of the wiring substrate 203. The printed circuit board 202 includes a recessed area within which the chip 201 is located. The chip pad 204 is electrically connected to the first substrate pad 206a through the conductive adhesive layer 108; the bonding pad 205 is electrically connected to the second substrate pad 206b through the conductive paste layer 209.
In this embodiment, the printed Circuit board 202 may be a rigid pcb (printed Circuit board) board. Therefore, when the PCB is grooved, the groove with a certain depth can be directly formed.
In addition, in the chip assembly 20 provided in the present embodiment, the chip 201, the wiring substrate 203, the chip pad 204, the bonding pad 205, the first substrate pad 206a, the second substrate pad 206b, the conductive trace 207, the conductive adhesive layer 208, and the conductive adhesive layer 209 may be the same as those of the corresponding components in the chip assembly 10 shown in fig. 1 in terms of structure, material, size, and positional relationship, and the chip assembly 20 may adopt the same processing technology as that of the chip assembly 10 described above.
As a possible implementation, a safety distance of more than 0.1mm is provided between the bottom surface of the chip 201 and the bottom surface of the recess area of the printed circuit board 202.
Through setting up safe distance can effectively avoid leading to the chip cracked because of external force strikes at the in-process of encapsulation laminating.
As a possible implementation, the distance between the edge of the chip 201 and the edge of the recessed area of the printed circuit board 202 is greater than 0.17 mm.
In order to ensure that the chip can still be arranged in the recess area of the printed circuit board in the presence of extreme tolerances, a distance can be provided between the edge of the chip and the edge of the recess area. The limit tolerance may include a db (die bonding) positioning tolerance, a chip contour machining tolerance and a chip position tolerance, and a printed circuit board recess area contour machining tolerance and a printed circuit board position tolerance.
As a possible implementation, the surface of the chip pad 204 is plated with a layer of nickel-gold 210.
When the chip bonding pad is made of aluminum, in order to enhance the electrical interconnection between the chip bonding pad and the first substrate bonding pad, a layer of nickel and gold can be plated on the surface of the chip bonding pad in a chemical mode, so that the phenomenon that a non-conductive aluminum oxide film is formed due to the oxidation of aluminum in the air is avoided, and the electrical connection performance between the chip bonding pad and the first substrate bonding pad is further influenced. Specifically, the thickness of the nickel layer may be about 2 μm.
As a possible implementation, the chip 201 further includes an effective identification area 211, where the effective identification area 211 is used for receiving an optical signal; the effective identification area 211 is arranged on the top surface of the chip 201, and the chip pad 204 is arranged outside the effective identification area 211; the wiring substrate 203 is a light-transmitting wiring substrate.
When the chip is an optical chip that can be used for imaging, for example, an image sensor chip or a fingerprint recognition chip, an effective recognition area is disposed on the top surface of the chip for receiving an optical signal reflected by an object to be detected to perform image or fingerprint recognition, and in order to not shield the optical signal, the wiring substrate may be made of a light-transmitting material, specifically, the light-transmitting wiring substrate may be made of a transparent substrate material such as a glass substrate.
As shown in fig. 4, a schematic view of processing steps of the manufacturing method of the chip assembly shown in fig. 3 specifically includes the following steps:
in the processing step (a), the first substrate pad 206a and the second substrate pad 206b are provided on the bottom surface of the wiring substrate 203, and the first substrate pad 206a and the second substrate pad 206b are electrically connected through the conductive line 207 of the wiring substrate 203.
In the processing step (b), the conductive adhesive layer 208 is printed on the surface of the first substrate pad 206a, and the printed circuit board 203 is grooved to form a groove region.
In the processing step (c), the chip 201 is disposed in the recessed area of the wiring substrate 202, and the chip pad 204 is electrically connected to the first substrate pad 206a through the conductive adhesive layer 208, and the conductive adhesive layer is cured by heating.
When the tin paste is selected as the conductive adhesive, the tin paste can be solidified by adopting a vacuum reflow soldering process at 180-260 ℃; when the conductive silver adhesive is selected as the conductive adhesive, the conductive silver adhesive can be cured by heating at the high temperature of 150-200 ℃; when silver paste is selected as the conductive adhesive, the silver paste can be solidified at a high temperature of 150-220 ℃ through a sintering process; thereby, a close and stable electrical connection between the chip and the wiring substrate can be formed.
In the processing step (d), the conductive adhesive layer 209 is attached to the surface of the second substrate pad 206 b.
In the processing step (e), the bonding pads 205 of the printed circuit board 202 are electrically connected to the second substrate pads 206b through the conductive paste layer 209.
Fig. 5 is a schematic cross-sectional view of another chip assembly provided in an embodiment of the present application. The chip assembly 30 includes: a chip 301 and an FPC 302; the top surface of chip 301 is provided with chip pads 303 and the top surface of FPC 302 is provided with FPC pads 304. The FPC 302 includes a substrate layer 302a and a reinforcing layer 302b which are stacked, the substrate layer 302a has a hollow opening, and the chip 301 is located in the opening of the substrate layer 302 a; specifically, the base material layer 302a may be a Polyimide (PI) layer; the reinforcing layer 302b may be a reinforcing steel plate, and the minimum thickness of the reinforcing steel plate may be 0.1 mm. The bottom surface of the chip 301 is bonded to the top surface of the reinforcing layer 302b via an adhesive layer 305, and the bottom surface of the base layer 302a is bonded to the top surface of the reinforcing layer 302b via a conductive adhesive layer 306. The wiring substrate 307 includes: third substrate pad 307a and fourth substrate pad 307b, and third substrate pad 307a and fourth substrate pad 307b are electrically connected by conductive line 307 c. The third substrate pad 307a is electrically connected to the chip pad 303 through a conductive adhesive layer 308a, and the fourth substrate pad 307b is electrically connected to the FPC pad 304 through a conductive adhesive layer 308 b.
The wiring substrate may be a glass substrate, a high-precision FPC flexible board, a PCB rigid board, or a plastic substrate that can be wired by an LDS (Laser-Direct-structuring) process, and the like.
Specifically, the adhesive layer may be a DB paste layer or a Die Attach Film (DAF) layer. The conductive bonding layer can be a tin paste layer, a conductive silver adhesive layer or a silver paste layer; firstly, a conductive adhesive (tin paste, conductive silver paste or silver paste) can be printed on the surface of a chip bonding pad or an FPC bonding pad through a steel screen printing process, and then the conductive adhesive is cured by heating to form close and stable electrical interconnection between the chip bonding pad and a third substrate bonding pad and between the FPC bonding pad and a fourth substrate bonding pad.
When the tin paste is selected as the conductive adhesive, the tin paste can be solidified by adopting a vacuum reflow soldering process at 180-260 ℃; when the conductive silver adhesive is selected as the conductive adhesive, the conductive silver adhesive can be cured by heating at the high temperature of 150-200 ℃; when silver paste is selected as the conductive adhesive, the silver paste can be solidified at a high temperature of 150-220 ℃ through a sintering process.
When the die pad 303 or the FPC pad 304 is made of aluminum, in order to enhance the electrical interconnection between the die pad 303 and the third substrate pad 307a or between the FPC pad 304 and the fourth substrate pad 307b, a nickel layer 309a may be chemically plated on the surface of the die pad 303, or a nickel layer 309b may be chemically plated on the surface of the FPC pad 304, so as to prevent the formation of a nonconductive aluminum oxide film due to oxidation of aluminum in air, thereby affecting the electrical connection performance. Specifically, the thickness of the nickel layer may be about 2 μm.
By adjusting the thickness of the base material layer 302a, the pressure of the chip 301 attached (DB) to the top surface of the reinforcing layer 302b, or the amount of the adhesive material or the conductive adhesive, the chip pad 303 and the FPC pad 304 can be at the same level, so that the structure of the wiring substrate 307 connected between the chip pad 303 and the FPC pad 304 is more flat, which is advantageous for improving the stability of the electrical connection structure.
When the chip 301 is an image sensor chip or a fingerprint recognition chip, the top surface of the chip 301 may be provided with an effective recognition area 310, for example, the effective recognition area 310 may be a pixel array area for receiving a detection optical signal incident from outside the chip assembly to perform image or fingerprint recognition.
In order to ensure that the chip can still be arranged in the groove area of the printed circuit board under the condition that the limit tolerance exists, a certain distance can be arranged between the edge of the chip and the edge of the groove area; preferably, this distance is greater than 0.17 mm. The limit tolerance may include a db (die bonding) positioning tolerance, a chip contour machining tolerance and a chip position tolerance, and a printed circuit board recess area contour machining tolerance and a printed circuit board position tolerance.
As shown in fig. 6, which is a schematic view of the processing steps of the manufacturing method of the chip assembly shown in fig. 5, the method specifically includes the following steps:
in the processing step (a), an adhesive layer 305 is attached to the top surface of the reinforcing layer 302 b.
For example, a layer of DB glue is spot-coated.
In the processing step (b), the chip 301 is bonded to the reinforcing layer 302b through the adhesive layer 305, and nickel layers 309a and 309b are plated on the surfaces of the chip pad 303 and the FPC pad 304, respectively.
The thickness of the nickel layer may be about 2 μm.
In the processing step (c), the conductive adhesive layers 308a and 308b are printed on the surfaces of the chip pad 303 and the FPC pad 304 by a steel mesh printing process.
The conductive bonding layer can be a tin paste layer, a conductive silver glue layer or a silver paste layer. The chip bonding pad and the FPC bonding pad after the conductive bonding layer is printed are preferably at the same level.
In the processing step (d), the wiring substrate 307 is electrically connected to the chip 301 and the FPC 302 by SMT, and the conductive adhesive layer is cured by heating.
When the tin paste is selected as the conductive adhesive, the tin paste can be solidified by adopting a vacuum reflow soldering process at 180-260 ℃; when the conductive silver adhesive is selected as the conductive adhesive, the conductive silver adhesive can be cured by heating at the high temperature of 150-200 ℃; when silver paste is selected as the conductive adhesive, the silver paste can be solidified at a high temperature of 150-220 ℃ through a sintering process.
If the bottom surface of the chip 301 is provided with DAF paste, the processing step (a) is not required.
Fig. 7 is a schematic cross-sectional view of another chip assembly provided in an embodiment of the present application. The chip assembly 40 includes: chip 401 and PCB 402; the top surface of chip 401 is provided with chip pads 403 and the top surface of PCB 402 is provided with PCB pads 404. PCB 402 has a recessed area and chip 401 is located within the recessed area of PCB 402. The bottom surface of the chip 401 is attached to the bottom surface of the recessed area of the PCB 402 by an adhesive layer 405. The wiring substrate 406 includes: fifth substrate pad 406a and sixth substrate pad 406b, and fifth substrate pad 406a and sixth substrate pad 406b are electrically connected by conductive trace 406 c. Wherein the fifth substrate pad 406a is electrically connected to the chip pad 402 through a conductive adhesive layer 407a, and the sixth substrate pad 406b is electrically connected to the PCB pad 404 through a conductive adhesive layer 407 b.
When the die pad 403 or the FPC pad 404 is made of aluminum, in order to enhance the electrical interconnection between the die pad 403 and the fifth substrate pad 406a or between the FPC pad 404 and the sixth substrate pad 406b, a nickel layer 408a may be chemically plated on the surface of the die pad 403, or a nickel layer 408b may be chemically plated on the surface of the FPC pad 404, so as to avoid forming a nonconductive aluminum oxide film due to oxidation of aluminum in air, thereby affecting the electrical connection performance. Specifically, the thickness of the nickel layer may be about 2 μm.
When the chip 401 is an image sensor chip or a fingerprint recognition chip, the top surface of the chip 401 may be provided with an effective recognition area 409, for example, the effective recognition area 409 may be a pixel array area for receiving a detection optical signal incident from outside the chip assembly to perform image or fingerprint recognition.
Specifically, the chip 401, the chip pad 403, the adhesive layer 405, the wiring substrate 406, the conductive adhesive layer 407a, the conductive adhesive layer 407b, the nickel layer 408a, the nickel layer 408b, and the effective identification area 409 in the chip assembly 40 may be the same as those of the corresponding components in the chip assembly 30 shown in fig. 5 in terms of structure, material, size, and positional relationship, and the chip assembly 40 may adopt the same processing technology as that of the chip assembly 30 described above.
As shown in fig. 8, a schematic view of processing steps of the manufacturing method of the chip assembly shown in fig. 7 specifically includes the following steps:
in the processing step (a), an adhesive layer 405 is attached to the bottom surface of the recessed area of the PCB 402.
For example, a layer of DB glue is spot-coated.
In the processing step (b), the chip 401 is attached to the bottom surface of the recessed area of the PCB 402 by the adhesive layer 405, and the surfaces of the chip pad 403 and the PCB pad 404 are plated with nickel layers 408a and 408b, respectively.
The thickness of the nickel layer may be about 2 μm.
In the process step (c), the conductive adhesive layers 407a and 407b are printed on the surfaces of the chip pad 403 and the PCB pad 404 by a steel mesh printing process.
The conductive bonding layer can be a tin paste layer, a conductive silver glue layer or a silver paste layer. The chip bonding pad and the FPC bonding pad after the conductive bonding layer is printed are preferably at the same level.
In the processing step (d), the wiring substrate 406 is electrically connected to the chip 401 and the PCB 402 by SMT, and heated to cure the conductive adhesive layer.
Conductive traces 406c inside wiring substrate 406 may connect die pads 403 to FPC pads 404 in a one-to-one correspondence.
When the tin paste is selected as the conductive adhesive, the tin paste can be solidified by adopting a vacuum reflow soldering process at 180-260 ℃; when the conductive silver adhesive is selected as the conductive adhesive, the conductive silver adhesive can be cured by heating at the high temperature of 150-200 ℃; when silver paste is selected as the conductive adhesive, the silver paste can be solidified at a high temperature of 150-220 ℃ through a sintering process.
It should be understood that the detailed description in the embodiments of the present application is only for helping those skilled in the art better understand the embodiments of the present application, and not for limiting the scope of the embodiments of the present application, and those skilled in the art can make various modifications and variations on the above embodiments, and these modifications and variations fall into the protection scope of the present application.
Claims (10)
1. A chip assembly, comprising: a chip, a printed circuit board, and a wiring substrate;
a chip bonding pad is arranged on the top surface of the chip;
the top surface of the printed circuit board is provided with a bonding pad;
a first substrate pad and a second substrate pad are arranged on the bottom surface of the wiring substrate, and the first substrate pad and the second substrate pad are electrically connected through a conducting circuit of the wiring substrate;
the printed circuit board comprises a groove area, and the chip is positioned in the groove area;
the chip bonding pad is electrically connected with the first substrate bonding pad through a conductive bonding layer; the bonding pad is electrically connected with the second substrate pad through the conductive adhesive layer.
2. The chip assembly of claim 1, wherein a safety distance of greater than 0.1mm is provided between the bottom surface of the chip and the bottom surface of the recessed region.
3. The chip assembly of claim 1, wherein a spacing between an edge of the chip and an edge of the recessed area is greater than 0.17 mm.
4. The chip assembly according to claim 1, wherein the surface of the chip pad is plated with a layer of nickel-gold.
5. The chip assembly of claim 1, wherein the chip pads are connected in a one-to-one correspondence with the first substrate pads; the bonding pads are connected with the second substrate pads in a one-to-one correspondence mode.
6. The chip assembly according to claim 1, wherein the wiring substrate further comprises: a substrate layer and a reinforcing layer;
the bottom surface of substrate layer laminate in the top surface of strengthening layer, the substrate layer is provided with the opening district, the opening district with the top surface of strengthening layer constitutes the recess district.
7. The chip assembly of claim 1, wherein the conductive adhesive layer is a solder paste layer, a conductive silver paste layer, or a silver paste layer printed by a steel mesh printing process.
8. The chip assembly according to any one of claims 1 to 7, wherein a top surface of the conductive adhesive layer is at the same level as a top surface of the conductive adhesive layer.
9. The chip assembly according to any one of claims 1 to 7, wherein the chip further comprises: an active identification area for receiving an optical signal;
the effective identification area is arranged on the top surface of the chip, and the chip bonding pad is arranged outside the effective identification area.
10. The chip assembly according to claim 9, wherein the wiring substrate is a light-transmissive wiring substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122238423.5U CN216084865U (en) | 2021-09-14 | 2021-09-14 | Chip module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122238423.5U CN216084865U (en) | 2021-09-14 | 2021-09-14 | Chip module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216084865U true CN216084865U (en) | 2022-03-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122238423.5U Active CN216084865U (en) | 2021-09-14 | 2021-09-14 | Chip module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216084865U (en) |
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2021
- 2021-09-14 CN CN202122238423.5U patent/CN216084865U/en active Active
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