CN216083441U

CN216083441U - Startup and shutdown control circuit and electronic equipment

Info

Publication number: CN216083441U
Application number: CN202121461400.4U
Authority: CN
Inventors: 散华杰
Original assignee: Beijing Goertek Technology Co Ltd
Current assignee: Beijing Goertek Technology Co Ltd
Priority date: 2020-07-29
Filing date: 2021-06-29
Publication date: 2022-03-18
Anticipated expiration: 2031-06-29

Abstract

The utility model discloses a startup and shutdown control circuit and electronic equipment. The electronic device includes: the power supply key, a first processor of the main control system of the operating equipment and a second processor of the auxiliary control system of the operating equipment are connected, the on-off control circuit is connected with the input/output end of the first processor and the starting signal line, the on-off control circuit is connected with the power supply key, the power supply key outputs an electric signal, the on-off control circuit is also connected with the input/output end of the second processor and the starting signal line, and the on-off control circuit responds to different trigger events when the power supply key is pressed and correspondingly controls the first processor and the second processor to be started or shut down. The on-off control circuit of the embodiment of the utility model can save the power consumption of the first processor, prolong the endurance time of the device, and improve the competitiveness of the electronic device and the user experience by controlling the on-off of the first processor and the second processor without increasing the size of the wearable device.

Description

Startup and shutdown control circuit and electronic equipment

Technical Field

The utility model relates to the technical field of electronic equipment, in particular to a startup and shutdown control circuit and electronic equipment.

Background

Electronic equipment especially wearable equipment develops rapidly in recent years, and wearable equipment is intelligent wearing again to name, is to use wear formula technique to carry out intelligent design, develop the general term of the equipment that can dress to daily wearing, like glasses, gloves, wrist-watch and bracelet etc.. Smart watches have developed rapidly in recent years with more and more integrated functions. The smart watch has the design requirements and trends of miniaturization, lightness and thinness, and as the capacity of the battery of the smart watch is basically in direct proportion to the size of the battery and the capacity of the small-sized battery is small, the smart watch can contact various smart watches, and the smart watch has the unified characteristic of short endurance. Therefore, how to save the power consumption of the system more without increasing the size of the battery is an urgent technical problem to be solved.

SUMMERY OF THE UTILITY MODEL

The utility model provides a startup and shutdown control circuit and electronic equipment, which aim to solve the technical problem that how to save the system power consumption of the electronic equipment on the premise of not increasing the size of a battery is urgent to solve.

According to an aspect of the present application, there is provided a power on/off control circuit applied to an electronic device, the electronic device including: power key, first processor for operating equipment master control system and second processor for operating equipment secondary control system

The on-off control circuit is connected with the input/output end of the first processor and the power-on signal line,

the switch control circuit is connected with the power supply key, the power supply key outputs a power-on signal,

the switch control circuit is also connected with the input/output end of the second processor and a starting signal line,

and in response to different trigger events of the power key being pressed, the on-off control circuit correspondingly controls the first processor and the second processor to be turned on and off.

According to another aspect of the present application, there is provided an electronic apparatus including: a power on/off control circuit according to one aspect of the present application.

The power on/off control circuit applied to the electronic equipment has the advantages that the power on/off control circuit is connected with the first processor running the main control system, the power supply key and the second processor running the auxiliary control system, and when the power supply key is pressed, the power on/off control circuit can correspondingly control the first processor to be powered on or powered off and the second processor to be powered on or powered off. Therefore, the starting and the shutdown of the two processors can be controlled through the triggering of one power key, the problems that the first processor is powered off once the whole system is closed due to the fact that the power key can only switch on and off one first processor, simple interaction cannot be achieved, the first processor is always started, the power consumption of the system is greatly consumed, the endurance time is short are solved, the power consumption of the system is saved, and the user requirements are met. The electronic equipment has higher market competitiveness due to the fact that the electronic equipment is provided with the on-off control circuit.

Drawings

FIG. 1 is a logic circuit diagram of a power on/off control circuit according to an embodiment of the present invention;

FIG. 2A is a hardware circuit diagram of a switching circuit according to one embodiment of the utility model;

FIG. 2B is a hardware circuit diagram of a switching circuit according to one embodiment of the utility model;

FIG. 3 is a schematic diagram of the operation of the power on/off control circuit according to one embodiment of the present invention;

FIG. 4 is a block diagram of an electronic device of one embodiment of the utility model.

Detailed Description

The design concept of the utility model is as follows: the battery capacity of electronic equipment such as intelligent wrist-watch is limited to intelligent wrist-watch size and can't be done very greatly among the prior art, and then leads to the problem that intelligent wrist-watch duration can not satisfy the demand. The utility model provides a startup and shutdown control scheme applied to wearable equipment in order to realize longer endurance time and start from the aspect of optimizing system power consumption. One hardware platform of the smart watch is a mode in which a CPU (Central Processing Unit) and an MCU (Micro control Unit) are combined, the CPU runs a main control system, and the CPU is also called an AP (Application processor) because the CPU manages and controls applications. The MCU runs the secondary control system, manages various sensors, and performs some simple storage and event management after the CPU is in a dormant state or is shut down.

A startup and shutdown scheme of a CPU and an MCU is as follows: the power supply key can only switch on and off the CPU, and in order to maintain the normal interaction and control processing functions, the CPU needs to be normally opened, so that the power consumption is high, if the CPU is closed, the whole system is shut down, and the operation of a user cannot be responded in time.

Therefore, the embodiment of the utility model provides a power on/off control scheme, which is applied to electronic equipment, and the reasonable switching of the power on or off of the CPU and the MCU is realized through a power on/off control circuit, so that the purposes of optimally configuring the power consumption of a system and improving the user experience are achieved.

One embodiment of the present invention provides a power on/off control circuit, which is applied to an electronic device, and the electronic device includes: power key, first processor for operating equipment master control system and second processor for operating equipment secondary control system

the power-on and power-off control circuit is connected with the power supply key, the power supply key outputs a power-on signal,

the switch control circuit is also connected with the input/output end of the second processor and the starting signal wire,

the power on/off control circuit correspondingly controls the first processor and the second processor to be powered on and off in response to different trigger events of the power key.

Here, in response to the trigger event that the power key is pressed, the power on/off control circuit correspondingly controls the first processor and the second processor to be powered on and powered off specifically includes the following conditions: the method comprises the steps of controlling the first processor and the second processor to be started, controlling the first processor and the second processor to be shut down, and controlling the first processor to be shut down and the second processor to be started.

For example, in response to a first trigger event that the power key is pressed for a first preset time, the on-off control circuit controls the second processor which is powered on after being powered on to be powered off, and switches a response main body of a power-on signal output by the power key into the first processor;

and responding to a second trigger event that the power key is pressed for a second preset time, controlling the first processor to start by the on-off control circuit, and resetting the second processor after the first processor is started so as to start the second processor.

That is to say, the power on/off control circuit of this embodiment can control the MCU to be powered on and the CPU to be powered off, or control the MCU to be powered on and the CPU to be powered on.

And responding to a third trigger event that the power key is pressed for a third preset time, the on-off control circuit controls the first processor which is started to reset so as to enable the first processor to be shut down and controls the second processor to be started, and the power key is switched from pointing to the first processor to pointing to the second processor;

the power-on/power-off control circuit is further used for responding to a fourth trigger event that the power key is pressed for a fourth preset time in the state that the first processor is powered off and the second processor is powered on, controlling the first processor to be powered off and controlling the second processor to be powered off.

That is to say, the power on/off control circuit of this embodiment can control the CPU to power off and the MCU to power on, or control both the MCU and the CPU to power off.

Next, the configuration of the on-off control circuit of the present embodiment will be described by taking a wearable device such as a smart watch as an example.

It should be emphasized that, in this embodiment, the first processor is a central processing unit CPU, and the second processor is a micro control unit MCU. The CPU functions are mainly to interpret machine instructions and to process calculations. For example, a received setting instruction input by a user through an input device of the smart watch is processed, and the current time of the smart watch is set according to the instruction. The MCU properly reduces the frequency and specification of the CPU and performs different combination control for different application occasions. The function of the MCU in this embodiment is mainly to process some simple operations and responses, for example, to control the smart watch to turn on or off the screen. Because the power consumption of the MCU is low, the startup and shutdown control circuit of the embodiment can achieve the purposes of saving power (shutting down the CPU and running the MCU under certain conditions) and prolonging the endurance time.

Fig. 1 is a logic circuit diagram of a power on/off control circuit according to an embodiment of the present invention, and referring to fig. 1, the power on/off control circuit is applied to a smart watch including a CPU for operating a main control system, an MCU for operating a sub-control system, and a power button,

the power key of this embodiment can be used for controlling the start or close of CPU and MCU, has avoided the extravagant problem of system power consumption, can realize under the circumstances that CPU shut down, MCU continues to work, and MCU low power dissipation does not need to open CPU at all times thereby has saved system power consumption.

The power on/off control circuit comprises a first switch and a second switch, and the first switch and the second switch are digital single-pole double-throw switches. The first switch is connected with the second switch;

the first switch is connected with the input/output end of the first processor and the starting signal line;

the first switch is connected with the power supply key, and the power supply key outputs a power-on signal;

the second switch is connected with the input/output end of the second processor and the starting signal wire,

the first switch and the second switch respectively control the first processor and the second processor to be turned on and off in response to different trigger events of the power key being pressed.

The control level input end (namely the IN end of the first switch IN figure 1) of the first switch is connected with the general purpose input/output port (namely GPIO _ AP IN figure 1) of the first processor (namely the CPU IN figure 1); GPIO (General Purpose Input Output) is actually pins through which a high-low level can be Output, or through which the state of a read-in pin is a high level or a low level, each GPIO port can be configured as an Input or an Output, respectively.

The common terminal of the first switch (i.e. the COM terminal of the first switch in fig. 1) is connected with the power key; the power button outputs a power-ON signal PHONE _ ON,

the normally open end of the first switch (i.e., the NO end of the first switch in fig. 1) is connected to the line of the power-on signal (i.e., the AP power-on signal in fig. 1) of the first processor (i.e., the CPU in fig. 1);

the normally closed end of the first switch (namely the NC end of the first switch in FIG. 1) is connected with the common end of the second switch (namely the COM end of the second switch in FIG. 1);

the control level input end (i.e. the IN end of the second switch IN fig. 1) of the second switch is connected with the general purpose input/output port (i.e. GPIO _ MCU IN fig. 1) of the second processor (i.e. MCU IN fig. 1);

the normally open end of the second switch (i.e., the NO end of the second switch in fig. 1) is connected to the line of the power-on signal (i.e., the AP power-on signal in fig. 1) of the first processor (i.e., the CPU in fig. 1);

the normally-closed end of the second switch (i.e., the NC end of the second switch in fig. 1) is connected to a power-on signal line (i.e., the MCU power-on signal in fig. 1) of the second processor (i.e., the MCU in fig. 1).

In the on-off control circuit of this embodiment, when the control level of the power-on signal of the power button is high, the common terminal of the first switch and the common terminal of the second switch are both connected to the normally open terminal, and when the control level of the power-on signal is low, the common terminal of the first switch and the common terminal of the second switch are both connected to the normally closed terminal.

Fig. 2 is a hardware circuit diagram of a switch control circuit according to an embodiment of the present invention, and it can be known from fig. 2 that the first switch 201 is an analog switch implemented by a digital circuit, the analog switch 201 is implemented by a MOS transistor in a switching manner to turn off or on a signal link, the analog switch 201 includes six pins, and the circuit connections of the six pins are as follows: the VCC pin is connected to a power supply VDD _ MCU. The IN pin is connected to a general purpose input/output port of the CPU, i.e., GPIO _ AP. The COM pin is connected with an electrical signal, namely PHONE _ ON. The NO (normally Open) pin is connected with a starting signal of the CPU, namely PHONE _ ON _ N. The NC (normally closed) pin outputs a second switch turn-ON control signal, i.e., PHONE _ ON _ a, to the second switch. The GND pin is grounded.

The second switch 202 may also be an analog switch implemented by a digital circuit, and includes six pins, and the circuit connections of the six pins are as follows: the VCC pin is connected to a power supply VDD _ MCU. The IN pin is connected with a general input/output port of the MCU, namely GPIO _ MCU. The COM pin is connected to a second switch power-ON control signal, namely a PHONE _ ON _ a signal, and is connected to the first switch through the PHONE _ ON _ a signal. The NO (normally Open) pin is connected with a starting signal of the CPU, namely PHONE _ ON _ N. The NC (normally closed) pin is connected with a starting signal of the MCU, namely the PHONE _ ON _ MCU. The GND pin is grounded.

Referring to fig. 3, the power on/off control circuit further includes an anti-shake circuit, which includes a first resistor 2021 (R1724) and a first capacitor 2022 (C1731),

one end of the first resistor 2021 is connected to the normally-closed end NC of the second switch 202,

the other end of the first resistor 2021 is connected to one end of the first capacitor 2022 and a power-ON signal line PHONE _ ON _ MCU of the second processor (MCU),

the other terminal of the first capacitor 2022 is grounded.

The startup and shutdown control circuit of the embodiment eliminates the jitter of the switch contact by arranging the anti-jitter circuit and utilizing the RC filtering function.

Referring to fig. 2, the normally-off terminal NC of the first switch 201 is connected to one terminal of a voltage regulator resistor (R1702 in the figure), and the other terminal of the voltage regulator resistor is connected to the second switch ON control signal, i.e., PHONE _ ON _ a. The stability of system power-on is guaranteed by arranging the voltage stabilizing resistor.

Fig. 3 is a schematic diagram of an operation mode of the on/off control circuit according to an embodiment of the present invention, and referring to fig. 3, the operation mode of the on/off control circuit according to this embodiment is as follows:

firstly, the intelligent watch is in an initial state;

the initial state refers to a state that the AP is not powered on or connected with the battery, and in the state, the AP is OFF and the MCU is OFF, namely the AP is in a power-OFF state and the MCU is in a power-OFF state. The operation process of the power-on/off control circuit is explained by dividing the circuit into two parts, one part is the power-on process, and the other part is the power-off process.

The boot process includes steps S301 to S303,

step S301, after power-on, no operation is performed, AP is OFF and MCU is automatically started, GPIO _ AP is low, and GPIO _ MCU is pulled low;

when the power supply is in an initial state, after the power supply is powered on (a battery is installed), the AP is in a power-off state, the GPIO _ AP is low, the power supply VDD _ MCU is connected with the battery, the circuit is communicated after the battery is plugged, the MCU is automatically started, and the GPIO _ MCU is pulled down, wherein the pulling down refers to the fact that the GPIO _ MCU end is configured to be low level (0 represents low level).

Table 1 is a logic truth table of the switch control circuit according to the embodiment of the present invention, and is described with reference to table 1.

The fifth column in table 1 indicates an abnormal condition, which may not be considered.

The process of step S301 corresponds to the penultimate column of table 1, i.e., GPIO _ AP is 0, GPIO _ MCU is 0, and Power _ Key to MCU (Power Key pointing to MCU). The state of the AP is AP _ OFF (AP OFF), and the state of the MCU is MCU _ ON (MCU ON).

Step S302, the AP is OFF, the MCU is in an ultra-low power consumption state, and the GPIO _ MCU is pulled high after being released;

in this step, in response to a first trigger event that the Power Key is pressed for a first preset time (for example, 3 seconds), the switch control circuit controls the second processor that is powered on after Power-on to shut down (i.e., controls the MCU to enter the ultra-low Power consumption state), and switches the response body of the Power-on signal output by the Power Key to the first processor, i.e., switches the Power _ Key to MCU to the Power _ Key to AP. At this point, the first processor is still in a shutdown state. With reference to table 1, the execution result of step S302 corresponds to the second column in table 1, i.e., GPIO _ AP is 0, GPIO _ MCU is 1, and Power _ Key to AP. At this time, the corresponding states of the AP and the MCU are AP OFF and MCU OFF, respectively, that is, both the AP and the MCU are in the OFF state.

It should be noted that as long as there is a battery in the smart watch, the MCU is not powered off in the true sense, so in this step, the MCU is in the ultra low power (ultra low power) state or the sleep (standby) state.

After the MCU is in the ultra-low power consumption state, referring to fig. 2, since the GPIO _ MCU is connected to the power supply VDD _ MCU after being connected to a pull-up resistor in series, when the GPIO _ MCU is released, the GPIO _ MCU is pulled up under the action of the pull-up resistor, where the pull-up is to configure the GPIO _ MCU terminal to a high level (1 represents a high level).

Step S303, the AP is ON, in the starting process of the AP, the AP pulls up the GPIO _ AP, resets and starts the MCU, and the MCU pulls down the GPIO _ MCU after starting;

in this step, in response to a second trigger event that the power key is pressed for a second preset time (for example, 5 seconds), the ON-off control circuit controls the first processor to be turned ON (i.e., AP ON), and resets the second processor after the first processor is turned ON, so that the second processor is turned ON (i.e., MCU ON). Specifically, after the AP is started, the MCU is reset through the MCU _ NRST pin (not shown in fig. 2), the MCU is started, and the MCU is pulled down the GPIO _ MCU after being started, so that the MCU is turned on.

With reference to table 1, the execution result of step S303 corresponds to the third column in table 1, i.e., GPIO _ AP is 1, GPIO _ MCU is 0, and Power _ Key to AP. At this time, the states corresponding to the AP and the MCU are AP ON and MCU ON, respectively, i.e., both the AP and the MCU are in a power-ON state.

Referring to fig. 3, the shutdown process includes steps S304 to S308.

Step S304, the AP is powered off;

in practical application, the AP may be powered off due to various reasons, and in this embodiment, three situations of the AP powering off are set, the first is to press the Power _ key for a long time or to cause an AP abnormality. For this situation, in response to a third trigger event that the power key is pressed for a third preset time (e.g., 6 seconds), the on-off control circuit controls the first processor (AP) to be reset to turn off the first processor (AP), and controls the second processor (MCU) to remain in the on state. Namely, step S305 is executed, and the AP is reset. And then returns to S303 to wait for the execution of the boot process.

The second is to receive a shutdown command on the interactive interface of the smart watch. For this case, step S306 is executed to control the AP to be OFF (AP power OFF) and the MCU enters an ultra-low power consumption state (which is equivalent to MCU power OFF). And then returns to S302 to wait for the execution of the boot process.

The third mode is that the intelligent watch is used as a common watch according to an instruction for switching to a common watch mode received on an interactive interface of the intelligent watch, for example, the intelligent watch can perform simple responses such as screen on, screen off and time display. For this case, step S307 is executed.

Step S307, the AP is OFF and the MCU is ON, the GPIO _ AP defaults to low after the AP is shut down, and the MCU is still kept low.

The MCU still keeps low means that GPIO _ MCU of the MCU keeps low level.

In this step, the response body of the Power-on signal output by the Power Key is also controlled to be switched to the second processor, that is, the Power _ Key to AP is switched to the Power _ Key to MCU. At this time, the AP is in the off state and the MCU is in the on state. Corresponding to the second last column in table 1.

In this state, if the Power key (Power key) is pressed for a short time when the intelligent watch is on the screen, the screen can be turned off under the control of the MCU, and if the Power key (Power key) is pressed for a short time when the intelligent watch is turned off the screen, the screen can be turned on under the control of the MCU; here, the short press is, for example, a power key for 1 second. And then step S308 is executed when a fourth trigger event of long pressing of the power key is received.

And step S308, keeping the GPIO _ AP low, pulling the GPIO _ MCU high by the outside, and entering the state of AP OFF and MCU ultra-low power consumption.

That is, the power on/off control circuit in this embodiment is further configured to, in a state where the first processor is powered off and the second processor is powered on, control the first processor to be powered off and control the second processor to be powered off in response to a fourth trigger event that the power key is pressed for a fourth preset time (for example, for 3 seconds).

With reference to table 1, the result executed in step S308 corresponds to the second column of table 1, that is, GPIO _ AP is 0, GPIO _ MCU is 1, and the response body of the Power-on signal output by the Power Key is switched to the first processor, that is, Power _ Key to AP.

After the step S308 is completed, the process returns to step S302 to wait for the boot process.

Therefore, the startup and shutdown control circuit controls and finishes the shutdown process of the AP and the MCU in the intelligent watch.

The startup and shutdown control circuit shown in fig. 3 can realize the screen-off effect by pressing the power key for a short time when the smart watch is on the screen, and control the MCU to enter the ultra-low power consumption state by pressing the power key for a long time (for example, 3 seconds) when the screen is off, and restart the AP if the power key is pressed for a long time (for example, 5 seconds). When the intelligent watch is turned off, the power supply key is pressed for a short time to achieve the screen-on effect; and when the screen is bright, if the power key is pressed for a long time (for example, 3 seconds), the MCU is controlled to enter an ultra-low power consumption state, and if the power key is pressed for a long time (for example, 5 seconds), the AP is restarted.

Therefore, the on-off control circuit of the embodiment can simultaneously control the on-off of the CPU and the MCU, so that the CPU can be turned off according to requirements, the MCU is responsible for some necessary operations, the MCU has low power consumption, and the purpose of power saving can be achieved. The problem that the CPU can only be controlled to be turned on and turned off in the prior art, and the CPU needs to be kept in a turned-on state all the time and is relatively power-consuming is solved.

Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. As shown in fig. 4, the electronic device is the above-mentioned on/off control circuit.

In the description of the present invention, numerous specific details are set forth. It is understood, however, that embodiments of the utility model may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description. Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the utility model, various features of the utility model are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that the utility model as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

While the foregoing is directed to embodiments of the present invention, other modifications and variations of the present invention may be devised by those skilled in the art in light of the above teachings. It should be understood by those skilled in the art that the foregoing detailed description is for the purpose of illustrating the utility model rather than the foregoing detailed description, and that the scope of the utility model is defined by the claims.

Claims

1. The utility model provides a switching on and shutting down control circuit which is applied to electronic equipment, electronic equipment includes: the system comprises a power supply key, a first processor for operating a main control system of the equipment and a second processor for operating a secondary control system of the equipment;

the startup and shutdown control circuit is connected with the input and output end of the first processor and a startup signal line;

the switch control circuit is connected with the power supply key, and the power supply key outputs a power-on signal;

2. The power on/off control circuit of claim 1, wherein the power on/off control circuit controls the first processor and the second processor to be powered on and powered off respectively in response to different triggering events of the power key being pressed comprises:

responding to a first trigger event that the power key is pressed for a first preset time, controlling the second processor which is powered on to be powered off by the on-off control circuit, and switching a response main body of a power-on signal output by the power key to the first processor;

and responding to a second trigger event that the power key is pressed for a second preset time, and controlling the first processor to be started by the on-off control circuit, so that the second processor is reset after the first processor is started and the starting is realized.

3. The power on/off control circuit of claim 1, wherein the power on/off control circuit controls the first processor and the second processor to be powered on and powered off respectively in response to different triggering events of the power key being pressed comprises:

responding to a third trigger event that the power key is pressed for a third preset time, the on-off control circuit controls the first processor which is started to reset so that the first processor is shut down, and a response main body of a power-on signal output by the power key is switched to the second processor;

the power on/off control circuit is further configured to respond to a fourth trigger event that the power key is pressed for a fourth preset time in a state where the first processor is powered off and the second processor is powered on, control the second processor to be powered off and control the first processor to remain in a power off state.

4. The switching control circuit according to any one of claims 1 to 3, wherein the switching control circuit comprises a first switch and a second switch, the first switch and the second switch being connected;

the first switch is connected with the input/output end of the first processor and a starting signal line;

the second switch is connected with the input/output end of the second processor and a starting signal line,

5. The on/off control circuit of claim 4,

a control level input end of the first switch is connected with a general input/output port of the first processor;

the public end of the first switch is connected with the power supply key;

the normally open end of the first switch is connected with a starting signal line of the first processor;

the normally closed end of the first switch is connected with the common end of the second switch;

a control level input end of the second switch is connected with a general input/output port of the second processor;

the normally open end of the second switch is connected with a starting signal line of the first processor;

and the normally closed end of the second switch is connected with the starting signal line of the second processor.

6. The on/off control circuit of claim 5, wherein the normally closed end of the second switch is connected to an anti-jitter circuit, the anti-jitter circuit comprises a first resistor and a first capacitor,

one end of the first resistor is connected with the normally closed end of the second switch,

the other end of the first resistor is connected with one end of the first capacitor and a starting signal line of the second processor,

the other end of the first capacitor is grounded.

7. The on-off control circuit according to claim 5, wherein the normally closed end of the first switch is connected to one end of a voltage regulator resistor, and the other end of the voltage regulator resistor is connected to the second switch on-off control signal line.

8. The on-off control circuit of claim 4, wherein the first switch and the second switch are both digital single-pole double-throw switches;

the first processor is a Central Processing Unit (CPU), and the second processor is a Micro Control Unit (MCU).

9. The on/off control circuit of claim 4, wherein the first switch and the second switch comprise a common terminal, a normally open terminal, and a normally closed terminal, respectively;

when the control level of the upper electric signal is high, the common end of the first switch and the common end of the second switch are both connected with a normally open end, and when the control level of the upper electric signal is low, the common end of the first switch and the common end of the second switch are both connected with a normally closed end.

10. An electronic device, characterized in that the electronic device comprises the on-off control circuit of any of claims 1-8.