CN216056818U - Synchronous rectification control circuit - Google Patents
Synchronous rectification control circuit Download PDFInfo
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- CN216056818U CN216056818U CN202121914208.6U CN202121914208U CN216056818U CN 216056818 U CN216056818 U CN 216056818U CN 202121914208 U CN202121914208 U CN 202121914208U CN 216056818 U CN216056818 U CN 216056818U
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Abstract
The utility model relates to a synchronous rectification control circuit, which at least comprises a synchronous rectification control chip U1; the method is characterized in that: the synchronous rectification control circuit further comprises a switching tube Q3 and an isolation transformer T2, and the synchronous rectification control chip U1 comprises an enable signal pin SYN; the control end of the switching tube Q3 is used for inputting a control signal synchronous with a driving signal of a clamping tube in an active clamping flyback converter, one end of the switching tube Q3 is connected with an original side ground GND, the other end of the switching tube Q3 is connected with a primary side synonym end of an isolation transformer T2, a primary side synonym end of the isolation transformer T2 is used for inputting a working voltage VDD, a secondary side synonym end of the isolation transformer T2 is used for connecting a secondary side ground signal Vo-, and a secondary side synonym end of the isolation transformer T2 is connected with an enable signal pin SYN. The circuit is simple, the cost is low, and the synchronous rectification drive can be turned off in advance before the primary main pipe is turned on in a CCM mode of the active clamping flyback converter adopting the back edge non-complementary control time sequence.
Description
Technical Field
The utility model relates to the field of switch converters, in particular to synchronous rectification control of an active clamp flyback switch converter.
Background
An Active Clamping Flyback (ACF) converter is used as one of flyback converters, has the advantages that a main switching tube can achieve Zero Voltage Switching (ZVS), leakage inductance can be absorbed in a lossless mode, voltage spikes of the main switching tube are small, efficiency is high, and the like, and is increasingly widely applied. A circuit schematic diagram of an existing conventional active clamp flyback converter is shown in fig. 1, Q1 is a main switching tube (hereinafter, referred to as a main tube), Q2 is a clamp switching tube (hereinafter, referred to as a clamp tube), and Cc is a clamp capacitor; ds1 is the body diode of the main switch Q1, Ds2 is the body diode of the clamp switch Q2. The operation principle of the back porch non-complementary control sequence shown in fig. 2 and the schematic diagram shown in fig. 1 is as follows.
The trailing edge non-complementary control sequence means that the clamp tube is turned on a short time before the main tube is turned on (dead time), and the conduction time of the clamp tube is not complementary to the conduction time of the main tube. Specifically, the clamp tube is opened for a short time ton_c(here a short time ton_cLess than the main pipe shut-off time), a dead time t passes after the clamp pipe is shut offdOpening the main pipe; after the main pipe is cut off, a longer time t passesdelayAnd then, opening the clamping tube, and repeating the steps. If the switching period is Ts and the duty ratio of the main tube is D, then there is (1-D.T)s)＝tdelay+ton_c+td. When the active-clamp flyback converter circuit in fig. 1 operates in a continuous mode (CCM), timing control and main waveforms of a back-porch non-complementary control mode are as shown in fig. 2, where GTL is a driving voltage of a main pipe Q1, GTH is a driving voltage of a clamp pipe Q2, Vds1 is a drain-source voltage of a main pipe Q1, and Vds2 is a drain-source voltage of a clamp pipe Q2; vc is the voltage at two ends of the clamping capacitor Cc, and the direction of Vc is from top to bottom of the schematic diagram shown in FIG. 1; im is the current (or called as magnetizing current) flowing through the magnetizing inductor Lm of the transformer, and Ids1 is the current flowing through the drain of the main pipe Q1; ids2 is the current flowing through the drain of the clamp Q2, and Ids2 is also equal to the current flowing through the clamp capacitance Cc; ip is the current flowing through the primary winding of the transformer and also the current flowing through the leakage inductance Lk; id is the current flowing through the secondary rectifier diode, and Vd is the reverse voltage of the secondary rectifier diode.
In a switching converter, a synchronous rectification technique is often used in order to reduce the loss of a rectifier tube and improve the efficiency of the converter. Fig. 3 shows a schematic diagram of an active clamp flyback converter using synchronous rectification on the secondary side, in fig. 3, SR1 is a secondary side synchronous rectification N-MOS transistor, and a body diode inside SR1 is omitted; vgs _ SR is the driving voltage of synchronous rectification N-MOS transistor SR 1. The synchronous rectification control circuit of fig. 3 includes: the synchronous rectification control chip U1, a capacitor C10, a resistor Rd and a resistor Rg; the synchronous rectification control chip U1 comprises a power supply pin VCC, a detection pin VD, a driving signal pin GATE and a bootstrap pin VS, wherein the power supply pin VCC is used for supplying power to the synchronous rectification IC, the detection pin VD is used for detecting drain-source voltage change of the synchronous rectification N-MOS tube SR1, the driving signal pin GATE is used for outputting a driving signal, and the bootstrap pin VS is used for realizing voltage bootstrap between the driving signal pin GATE and the bootstrap pin VS; the capacitor C10 is a decoupling capacitor of the synchronous rectification control chip U1, and the resistor Rg is a driving resistor of a synchronous rectification N-MOS tube SR 1; the connection relationship of the synchronous rectification control circuit is as follows: the power supply pin VCC is used for inputting power supply voltage VCC, the power supply pin VCC is also connected with one end of a capacitor C10, the other end of the capacitor C10 is connected with a secondary ground signal Vo-, a detection pin VD is connected with one end of a resistor Rd, the other end of the resistor Rd is connected with the drain electrode of a synchronous rectification N-MOS tube SR1, a driving signal pin GATE is connected with one end of a resistor Rg, the other end of the resistor Rg is connected with the grid electrode of the synchronous rectification N-MOS tube SR1, and a bootstrap pin VS is connected with the source electrode of the synchronous rectification N-MOS tube SR 1.
Generally, the control mode of the synchronous rectification control chip U1 is that the drain-source voltage Vds _ SR of the synchronous rectification N-MOS tube SR1 is detected, when the Vds _ SR is smaller than a turn-on threshold value Vds _ on, the synchronous rectification driving voltage Vgs _ SR is set to be a high level, and the SR1 is turned on; when Vds _ SR is larger than the turn-off threshold Vds _ off, the synchronous rectification drive voltage Vgs _ SR is set to a low level, and SR1 is turned off. However, when the circuit works in a CCM mode, if the primary main pipe Q1 is turned on, the current Ids _ SR of the secondary rectifier tube is not reduced below the turn-off threshold of the control IC, and the primary and secondary N-MOS transistors share the same current; or when the primary main pipe Q1 is conducted, the voltage Vds1 at the two ends of the primary main pipe Q1 is reduced, the voltage at the two ends of the primary winding of the transformer and the voltage at the two ends of the secondary winding of the transformer are increased, so that the Vds _ SR of the secondary side and the rectifying N-MOS transistor SR1 is forced to rise, and when the Vds _ SR is greater than a turn-off threshold value Vds _ off, the synchronous rectifying driving voltage Vgs _ SR is set to be low level, and the SR1 is turned off; it can be seen that the generation of the turn-off signal of the synchronous rectification N-MOS transistor is realized by the voltage rise at the two ends of the transformer winding, however, because the transmission delay of the transformer and the signal transmission delay of other circuits such as the synchronous rectification control chip U1 exist, the turn-off of the synchronous rectification N-MOS transistor SR1 is delayed by the delay, and the simultaneous conduction (i.e., common conduction) of the primary and secondary N-MOS transistors occurs, as shown in fig. 4; and once the primary and secondary side N-MOS tubes are in common, the current or voltage of the primary and secondary side N-MOS tubes is increased sharply to fail.
It is noted that the information disclosed in this background section is only for enhancement of understanding of the general background of the utility model and should not be taken as an acknowledgement or any form of suggestion that this information constitutes prior art already known to a person skilled in the art.
SUMMERY OF THE UTILITY MODEL
Therefore, the present invention is to provide a synchronous rectification control circuit, which can turn off the synchronous rectification driving in advance before the primary main pipe is turned on.
In order to solve the problems, the technical scheme of the utility model is as follows:
a synchronous rectification control circuit is applied to an active clamp flyback converter and at least comprises a synchronous rectification control chip U1; the method is characterized in that:
the synchronous rectification control circuit further comprises a switching tube Q3 and an isolation transformer T2, and the synchronous rectification control chip U1 comprises an enable signal pin SYN; the control end of the switching tube Q3 is used for inputting a control signal synchronous with a driving signal of a clamping tube in an active clamping flyback converter, one end of the switching tube Q3 is connected with an original side ground GND, the other end of the switching tube Q3 is connected with a primary side different name end of the isolation transformer T2, a primary side same name end of the isolation transformer T2 is used for inputting a working voltage VDD, a secondary side same name end of the isolation transformer T2 is used for being connected with a secondary side ground signal Vo-, and a secondary side different name end of the isolation transformer T2 is connected with the enabling signal pin SYN.
Preferably, the applied active-clamp flyback converter adopts the trailing-edge non-complementary control timing and operates in the CCM mode.
Preferably, the switching transistor Q3 is an N-MOS transistor, the gate of the N-MOS transistor is the control end of the switching transistor Q3, the source of the N-MOS transistor is one end of the switching transistor Q3, and the drain of the N-MOS transistor is the other end of the switching transistor Q3.
Preferably, the switching transistor Q3 is a triode, the base of the triode is the control terminal of the switching transistor Q3, the emitter of the triode is one terminal of the switching transistor Q3, and the collector of the triode is the other terminal of the switching transistor Q3.
Further, the synchronous rectification control circuit further comprises a capacitor C1, and the capacitor C1 is connected across the secondary winding of the isolation transformer T2.
Further, the synchronous rectification control circuit further comprises a resistor R1, and the resistor R1 is connected across the secondary winding of the isolation transformer T2.
Further, the synchronous rectification control circuit further comprises a diode D1 and a diode D2, wherein the diode D1 and the diode D2 are connected in parallel in an inverse manner and then are connected across the two ends of the secondary winding of the isolation transformer T2 in a bridge connection mode.
The utility model relates to a synchronous rectification N-MOS tube SR1 capable of turning off a secondary side by utilizing a driving trigger signal of a primary clamping tube Q2, in particular to a synchronous rectification control circuit which mainly comprises: a synchronous signal trigger circuit, an isolation transformer T2 and a synchronous rectification control chip U1 with an enable control function; the synchronous signal trigger circuit converts a driving rising edge signal of the clamping tube Q2 into a positive pulse excitation signal of which the primary dotted end of the isolation transformer T2 is higher than the primary synonym end, the positive pulse excitation signal is coupled to the secondary side through the isolation transformer, the coupled signal is also that the dotted end is higher than the synonym end, because the dotted end of the secondary side of the isolation transformer T2 is grounded, the negative pulse excitation signal SYN received by the synonym end of the secondary side of the isolation transformer T2 enables the synchronous rectification control chip U1 to be turned off, and the synchronous rectification driving N-MOS tube SR1 is turned off, so that the condition that the primary side and the secondary side are simultaneously conducted (namely are commonly conducted) is avoided.
The utility model utilizes the switching tube and the isolation transformer to form a pulse signal control circuit, ensures that the synchronous rectification drive is turned off in advance before the primary main tube of the active clamping flyback converter is turned on, and compared with the prior art, the utility model has the following beneficial effects:
(1) the common turn-off of the primary and secondary N-MOS of the active clamp flyback converter can not be caused, and the active clamp flyback converter using the synchronous rectification control circuit has stable work and high reliability;
(2) the circuit is simple and the cost is low.
Drawings
FIG. 1 is a schematic diagram of an active clamp flyback converter with an N-MOS clamp switch tube;
fig. 2 is a timing diagram of an active clamp flyback converter in a trailing edge non-complementary control mode;
fig. 3 is a schematic diagram of an active clamp flyback converter with synchronous rectification on the secondary side;
fig. 4 is a common timing diagram of the primary side and the secondary side of the active clamp flyback converter in a CCM mode;
FIG. 5 is a schematic diagram of a first embodiment of the present invention;
FIG. 6 is a control timing chart of the first embodiment of the present invention;
FIG. 7 is a schematic diagram of a second embodiment of the present invention;
fig. 8 is a schematic diagram of a third embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the utility model and are not intended to limit the utility model.
First embodiment
As shown in fig. 5, a schematic circuit diagram according to a first embodiment of the present invention is different from fig. 3 in that the present invention further includes: the synchronous rectification control circuit comprises an N-MOS transistor Q3 and an isolation transformer T2, and in addition, a synchronous rectification control chip U1 further comprises an enable signal pin SYN; the driving signal input by the grid electrode of the N-MOS tube Q3 and the driving signal input by the grid electrode of the clamping tube Q2 are GTH, the source electrode of the N-MOS tube Q3 is connected with a primary side ground GND, the drain electrode of the N-MOS tube is connected with a primary side different name end of the isolation transformer T2, the primary side same name end of the isolation transformer T2 is input with working voltage VDD, the secondary side same name end of the isolation transformer T2 is connected with a secondary side ground signal Vo-, and the secondary side different name end of the isolation transformer T2 is connected with an enabling signal pin SYN of the synchronous rectification chip U1.
Fig. 6 shows a timing diagram of the primary and secondary sides of the first embodiment, when the GTH driving signal of the clamping tube Q2 is at a high level, the N-MOS tube Q3 is turned on, the isolation transformer T2 senses a positive pulse excitation signal whose primary dotted terminal is higher than the primary dotted terminal, the positive pulse excitation signal is coupled to the secondary side through the isolation transformer, the coupled signal also has a dotted terminal higher than the dotted terminal, since the dotted terminal of the secondary side of the isolation transformer is grounded, the negative pulse excitation signal SYN received by the dotted terminal of the secondary side of the isolation transformer enables the synchronous rectification control chip U1, and turns off the synchronous rectification driving N-MOS tube SR1, thereby avoiding the situation that the primary and secondary sides are simultaneously turned on (i.e., are turned on), the circuit of the enable control circuit is simple and low in cost, the common turn-off of the N-MOS of the primary and secondary sides is not caused, and the operation is stable and the reliability is high.
Second embodiment
As shown in fig. 7, which is a schematic circuit diagram of a second embodiment of the present invention, compared with the first embodiment of the present invention, the second embodiment is characterized by further comprising a capacitor C1 and a resistor R1, wherein the capacitors C1 and R1 are connected in parallel and then connected across the secondary winding of the isolation transformer T2.
After the capacitor C1 and the resistor R1 are added, the high-frequency interference signal of the secondary side excitation voltage signal SYN can be bypassed by the capacitor C1, so that the anti-interference capability of the circuit is improved, the amplitude of the secondary side excitation voltage signal SYN can be adjusted through the resistor R1, and the size of the enabling signal SYN can be flexibly controlled.
Compared with the first embodiment of the present invention, the basic working principle of the second embodiment is not substantially different, and is not described herein again.
Third embodiment
As shown in fig. 8, which is a schematic circuit diagram of a third embodiment of the present invention, compared with the second embodiment of the present invention, the second embodiment is different in that a diode D1 and a diode D2 are further included, and a diode D1 and a diode D2 are connected in anti-parallel and then connected across the secondary winding of the isolation transformer T2.
By adding the diode D1 and the diode D2, the voltage across the secondary winding of the isolation driving transformer T2 is clamped by the diodes, so that the amplitude of the secondary excitation voltage signal SYN is not too large or too small to damage the synchronous rectification control chip U1, and the reliability of the circuit is improved.
Compared with the second embodiment of the present invention, the basic working principle of the third embodiment is not substantially different, and is not described herein again.
The above is only a preferred embodiment of the present invention, and it should be noted that the above preferred embodiment should not be considered as limiting the present invention, and it will be apparent to those skilled in the art that several modifications and decorations can be made without departing from the spirit and scope of the present invention, for example, the N-MOS transistor in the above embodiment is changed to an NPN transistor, and these modifications and decorations should also be considered as the protection scope of the present invention, which is not described in detail with reference to the embodiment herein, and the protection scope of the present invention should be subject to the scope defined by the claims.
Claims (7)
1. A synchronous rectification control circuit is applied to an active clamp flyback converter and at least comprises a synchronous rectification control chip U1; the method is characterized in that:
the synchronous rectification control circuit further comprises a switching tube Q3 and an isolation transformer T2, and the synchronous rectification control chip U1 comprises an enable signal pin SYN; the control end of the switching tube Q3 is used for inputting a control signal synchronous with a driving signal of a clamping tube in an active clamping flyback converter, one end of the switching tube Q3 is connected with an original side ground GND, the other end of the switching tube Q3 is connected with a primary side different name end of the isolation transformer T2, a primary side same name end of the isolation transformer T2 is used for inputting a working voltage VDD, a secondary side same name end of the isolation transformer T2 is used for being connected with a secondary side ground signal Vo-, and a secondary side different name end of the isolation transformer T2 is connected with the enabling signal pin SYN.
2. The synchronous rectification control circuit of claim 1, wherein: the applied active clamp flyback converter adopts a back-porch non-complementary control time sequence and works in a CCM mode.
3. The synchronous rectification control circuit of claim 1 or 2, wherein: the switch tube Q3 is an N-MOS tube, the gate of the N-MOS tube is the control end of the switch tube Q3, the source of the N-MOS tube is one end of the switch tube Q3, and the drain of the N-MOS tube is the other end of the switch tube Q3.
4. The synchronous rectification control circuit of claim 1 or 2, wherein: the switch tube Q3 is a triode, the base of the triode is the control end of the switch tube Q3, the emitter of the triode is one end of the switch tube Q3, and the collector of the triode is the other end of the switch tube Q3.
5. The synchronous rectification control circuit of any one of claims 1 or 2, wherein: the synchronous rectification control circuit further comprises a capacitor C1, and the capacitor C1 is connected across the secondary winding of the isolation transformer T2 in a bridging mode.
6. The synchronous rectification control circuit of any one of claims 1 or 2, wherein: the synchronous rectification control circuit further comprises a resistor R1, and the resistor R1 is connected across the secondary winding of the isolation transformer T2 in a bridging mode.
7. The synchronous rectification control circuit of any one of claims 1 or 2, wherein: the synchronous rectification control circuit further comprises a diode D1 and a diode D2, wherein the diode D1 and the diode D2 are connected in parallel in an inverted mode and then are connected across the two ends of the secondary winding of the isolation transformer T2 in a bridge mode.
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| CN202121914208.6U CN216056818U (en) | 2021-08-16 | 2021-08-16 | Synchronous rectification control circuit |
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| CN202121914208.6U CN216056818U (en) | 2021-08-16 | 2021-08-16 | Synchronous rectification control circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113809926A (en) * | 2021-08-16 | 2021-12-17 | 广州金升阳科技有限公司 | Synchronous rectification control circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113809926A (en) * | 2021-08-16 | 2021-12-17 | 广州金升阳科技有限公司 | Synchronous rectification control circuit |
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