CN216002277U - BMS system - Google Patents

Abstract

The utility model discloses a BMS system, which uses an analog front end to supply power to a processor. When a 485 communication device is connected with a 485 communication chip, the differential signal output end outputs a differential signal, at the moment, the first output end of the wake-up circuit, namely a level signal of a preset pin of the processor, is changed, and the control switch is switched on, so that the DC/DC is electrified, and the corresponding 485 communication chip is electrified; the first preset level signal of the second output that awakens circuit can be received to the pin of awakening up of simulation front end, thereby the simulation front end is awaken up, not only can control switch on, can also realize awakening up the simulation front end, at this moment, no matter the BMS system is in shallow sleep mode or deep sleep mode, all can realize awakening up the BMS system, and when the state information of group battery is read to needs, only need connect 485 communication device can, need not use and connect the charger, the convenience has been improved.

Description

BMS system

Technical Field

The present invention relates to the field of battery control, and more particularly, to a BMS system.

Background

With the continuous development of the electric vehicle industry technology, in order to suppress common mode interference in the signal transmission process, a 485 communication function is added in a Battery Management System (BMS) communication System, and the inside of the BMS communication System is communicated with an external 485 communication device through a 485 communication chip. Referring to fig. 1, fig. 1 is a block diagram illustrating a BMS system according to the related art. When the switch is turned on, the DC/DC converter converts the output voltage of the battery pack to supply power to the 485 communication chip and the processor, the analog front end collects the state information of the battery pack and transmits the collected state information to the processor, and the processor processes the state information through the 485 communication chip and then transmits the processed state information to the external 485 communication device.

However, the 485 communication chip has a large power consumption, and if the 485 communication chip is operated all the time, the standby time of the electric vehicle can be reduced, so that in the prior art, when no external 485 communication device is accessed, the BMS system generally enters a shallow sleep mode, and when the state of the battery pack needs to be acquired, the BMS system is waken up again to increase the standby time of the electric vehicle.

When the BMS system in the prior art enters the shallow sleep mode, the switch between the battery pack and the DC/DC is switched off, the DC/DC is powered off, and then the 485 communication chip and the processor are in a power-off state. The way of waking up the BMS system in the prior art is: through inserting a charger, this charger can export a control signal to make the switch on, and then DC/DC gets electric, and then treater and 485 communication chip all get electric, then pulls out the charger after making treater control switch be in the conducting state, in order to realize awakening up the BMS system. By using the mode, when the state information of the battery pack is acquired, not only the 485 communication device but also the charger needs to be connected, and the steps are complicated.

In order to further increase the standby time of the electric vehicle, the BMS system may be controlled to enter a deep sleep mode, and particularly, the analog front end enters a sleep state, and a switch between the battery pack and the DC/DC is turned off to reduce power consumption of the BMS system, thereby increasing the standby time of the electric vehicle. Therefore, it is necessary to provide a wake-up circuit having a simple procedure to wake up not only the BMS system in the shallow sleep mode but also the BMS system in the deep sleep mode.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a BMS system, which can be awakened no matter the BMS system is in a shallow sleep mode or a deep sleep mode, only a 485 communication device needs to be connected when the state information of a battery pack needs to be read, a charger does not need to be used and connected, and convenience is improved.

In order to solve the technical problem, the utility model provides a BMS system which comprises an analog front end, a switch, a direct current/direct current converter DC/DC, a processor, a 485 communication chip and a wake-up circuit, wherein the analog front end is connected with the switch;

the voltage output end of the analog front end is connected with the power supply end of the processor, the control end of the processor is connected with the control end of the switch, the input end of the wake-up circuit is respectively connected with the differential signal end of the 485 communication chip, the first output end of the wake-up circuit is connected with the preset pin of the processor, the second output end of the wake-up circuit is connected with the wake-up pin of the analog front end, and when the differential signal end of the 485 communication chip is connected with an external 485 communication device, the differential signal end has differential signal output;

the analog front end is used for converting the output voltage of the battery pack to supply power for the processor;

the processor is used for controlling the switch to be conducted when the power supply end of the processor has input voltage and the level signal of the preset pin of the processor changes;

the wake-up circuit is used for controlling the level signal of the first output end of the wake-up circuit to change when a differential signal is input into the input end of the wake-up circuit, and controlling the second output end of the wake-up circuit to output a first preset level signal, so that the analog front end is woken up.

Preferably, the circuit comprises a first switch circuit, a second switch circuit and a third switch circuit;

the first end of the first switch circuit is connected with the differential signal end, the second end of the first switch circuit is respectively connected with the first end of the second switch circuit and the first end of the third switch circuit, the second end of the second switch circuit is a first output end of the wake-up circuit, and the second end of the third switch circuit is a second output end of the wake-up circuit;

the first switch circuit is used for being conducted when the differential signal is input at the first end of the first switch circuit, so that the second end of the first switch circuit outputs a second preset level signal;

the second switch circuit is used for being conducted when the first end of the second switch circuit receives the second preset level signal, so that the level signal of the second end of the second switch circuit is changed;

the third switch circuit is used for being conducted when the first end of the third switch circuit receives the second preset level signal, so that the second end of the third switch circuit outputs the first preset level signal, and the analog front end is awakened.

Preferably, the first switch circuit includes an optocoupler and a capacitor, and the differential signal terminal includes a first signal terminal and a second signal terminal;

the first end of the optical coupler is connected with the first signal end, the second end of the optical coupler is connected with the second signal end, the third end of the optical coupler is connected with the output end of the power module, the fourth end of the optical coupler is connected with the first end of the capacitor and serves as the second end of the first switch circuit, and the second end of the capacitor is grounded.

Preferably, the first switch circuit further comprises a first diode and a first resistor;

the first end of the first resistor is connected with the first signal end, the second end of the first resistor is connected with the cathode of the first diode and the first end of the optocoupler, and the anode of the first diode is connected with the second signal end and the second end of the optocoupler respectively.

Preferably, the second switch circuit includes a controllable switch, a control end of the controllable switch is connected to the second end of the first switch circuit, a first end of the controllable switch is connected to the output end of the power module and the preset pin of the processor, respectively, and a second end of the controllable switch is grounded.

Preferably, the third switch circuit comprises a second diode having an anode connected to the second terminal of the first switch circuit and a cathode connected to the wake-up terminal of the analog front end.

Preferably, the second switch circuit further comprises a second resistor, a third resistor and a fourth resistor;

one end of the second resistor is connected with the output end of the power supply module, the other end of the second resistor is connected with the first end of the controllable switch and the preset pin respectively, one end of the third resistor is connected with the output end of the first switch circuit, the other end of the third resistor is connected with one end of the fourth resistor and the control end of the controllable switch respectively, and the other end of the fourth resistor is connected with the second end of the controllable switch.

Preferably, the method further comprises the following steps:

the isolation power supply is arranged between the output end of the DC/DC and the power supply end of the 485 communication chip;

and the communication isolation chip is arranged between the output end of the processor and the communication end of the 485 communication chip.

Preferably, the method further comprises the following steps:

and the linear voltage stabilizer is arranged between the output end of the DC/DC and the power supply end of the processor and is used for adjusting the output voltage of the DC/DC to a preset voltage so as to supply power to the processor.

The application provides a BMS system that uses an analog front end to power a processor. When a 485 communication device is connected with a 485 communication chip, the differential signal output end outputs a differential signal, at the moment, the first output end of the wake-up circuit, namely a level signal of a preset pin of the processor, is changed, and the control switch is switched on, so that the DC/DC is electrified, and the corresponding 485 communication chip is electrified; the first preset level signal of the second output that awakens circuit can be received to the pin of awakening up of simulation front end, thereby the simulation front end is awaken up, not only can control switch on, can also realize awakening up the simulation front end, at this moment, no matter the BMS system is in shallow sleep mode or deep sleep mode, all can realize awakening up the BMS system, and when the state information of group battery is read to needs, only need connect 485 communication device can, need not use and connect the charger, the convenience has been improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a block diagram of a structure in a BMS system in the related art;

fig. 2 is a block diagram illustrating a BMS system according to the present invention;

FIG. 3 is a block diagram of a wake-up circuit according to the present invention;

FIG. 4 is a schematic diagram of a wake-up circuit according to an embodiment of the present invention;

fig. 5 is a block diagram illustrating the structure of another BMS system according to the present invention.

Detailed Description

The core of the utility model is to provide a BMS system, a wake-up circuit can wake up the BMS system no matter the BMS system is in a shallow sleep mode or a deep sleep mode, and when the state information of a battery pack needs to be read, only a 485 communication device needs to be connected, a charger does not need to be used and connected, and the convenience is improved.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 2, fig. 2 is a block diagram of a BMS system according to the present invention, the BMS system including an analog front end 2, a switch 4, a DC/DC5, a processor 3, a 485 communication chip, and a wake-up circuit 1;

the voltage output end of the analog front end 2 is connected with the power supply end of the processor 3, the control end of the processor 3 is connected with the control end of the switch 4, the input end of the wake-up circuit 1 is respectively connected with the differential signal end of the 485 communication chip, the first output end of the wake-up circuit 1 is connected with the preset pin of the processor 3, the second output end of the wake-up circuit 1 is connected with the wake-up pin of the analog front end 2, and when the differential signal end of the 485 communication chip is connected with an external 485 communication device, the differential signal end has differential signal output;

the analog front end 2 is used for converting the output voltage of the battery pack to supply power for the processor 3;

the processor 3 is used for controlling the switch 4 to be switched on when the power supply end of the processor has input voltage and the level signal of the preset pin of the processor changes;

the wake-up circuit 1 is configured to control a level signal of a first output terminal of the wake-up circuit to change when a differential signal is input to an input terminal of the wake-up circuit, and control a second output terminal of the wake-up circuit to output a first preset level signal, so that the analog front end 2 is woken up.

Considering that when the BMS system that controls only the battery in the related art enters the shallow sleep mode, although the standby time of the electric vehicle can be increased to some extent, the analog front end 2 can also reduce the standby time of the electric vehicle to some extent, and thus, the BMS system can be controlled to enter the deep sleep mode in the related art, at this time, the switch 4 in the BMS system is turned off and the analog front end 2 enters the sleep mode to reduce the power consumption of the BMS, thereby increasing the power consumption of the electric vehicle.

In view of the above, the present invention is directed to provide a wake-up circuit 1, which can wake up not only a BMS system in a shallow sleep mode but also a BMS system in a deep sleep mode to enable the BMS system to exit from the sleep mode.

Therefore, this application provides a wake-up circuit 1, wherein, still use analog front end 2 to supply power for treater 3 in the BMS system in this application, thereby when shallow sleep mode, the 485 communication chip falls the power supply, treater 3 is in electrified state always, at this moment, when having 485 communication device output differential signal, the level signal of the first output of wake-up circuit 1 changes, when treater 3 detects that the level signal of predetermineeing the pin changes, control switch 4 switches on, so that DC/DC5 gets the electricity, the 485 communication chip falls the power supply, accomplish the wake-up to the shallow sleep mode of BMS system. When the degree of depth sleep mode, processor 3 falls the power supply, 485 communication chip also falls the power supply, and 2 dormancy of simulation front end, 485 communication device output difference signal are in order to make the first level signal of predetermineeing of the second output of awaking circuit 1 to make simulation front end 2 awaken up, simulation front end 2 can be for processor 3 power supply this moment, and when predetermineeing the pin and receive the level signal of change, control switch 4 switches on, thereby realize awaking up to the degree of depth sleep mode of BMS system.

It should be noted that, the processor 3 in this application may be but is not limited to an MCU, the power supply voltage of the power supply terminal of the MCU is 3.3V, the power supply voltage of the 485 communication chip may be but is not limited to 5V, and other implementation modes may also be used, and this application is not limited in particular herein.

In conclusion, no matter the BMS system is in shallow sleep mode or deep sleep mode, the wake-up circuit 1 in the application can realize the wake-up of the BMS system, and when the state information of the battery pack needs to be read, only the 485 communication device needs to be connected, the charger does not need to be used and connected, and the convenience is improved.

On the basis of the above-described embodiment:

referring to fig. 3, fig. 3 is a block diagram of a wake-up circuit according to the present invention.

As a preferred embodiment, it includes a first switch circuit 31, a second switch circuit 32, and a third switch circuit 33;

a first end of the first switch circuit 31 is connected with the differential signal end, a second end of the first switch circuit is respectively connected with a first end of the second switch circuit 32 and a first end of the third switch circuit 33, a second end of the second switch circuit 32 is a first output end of the wake-up circuit 1, and a second end of the third switch circuit 33 is a second output end of the wake-up circuit 1;

the first switch circuit 31 is used for being conducted when a differential signal is input at a first end of the first switch circuit, so that a second end of the first switch circuit outputs a second preset level signal;

the second switch circuit 32 is configured to be turned on when the first end of the second switch circuit receives a second preset level signal, so that the level signal of the second end of the second switch circuit changes;

the third switch circuit 33 is turned on when the first terminal of the third switch circuit receives the second preset level signal, so that the second terminal of the third switch circuit outputs the first preset level signal, and the analog front end 2 is awakened.

The present embodiment is intended to provide a specific implementation manner of the wake-up circuit 1, specifically, the wake-up circuit 1 in the present embodiment may include, but is not limited to, three switch circuits, wherein after the first terminal of the first switch circuit 31 receives the differential signal, the first switch circuit 31 is turned on, and then the second switch circuit 32 is turned on based on the second preset level signal to change the level signal of the second stage thereof, so as to change the level signal of the preset pin of the processor 3, and the third switch circuit 33 is turned on based on the second preset level signal to output the first preset level signal, so as to wake-up the analog front end 2.

The first preset level signal and the second preset level signal in the present application relate to specific implementations of three switch circuits, and the present application is not limited herein.

In summary, the three switch circuits in the present application can wake up the shallow sleep mode and the deep sleep mode of the BMS system, and the implementation manner is simple and reliable.

Referring to fig. 4, fig. 4 is a specific circuit diagram of a wake-up circuit according to the present invention.

As a preferred embodiment, the first switch circuit 31 includes an optical coupler and a capacitor, and the differential signal terminal includes a first signal terminal and a second signal terminal;

the first end and the first signal end of opto-coupler are connected, and the second end and the second signal end of opto-coupler are connected, and the third end and the output of power module of opto-coupler are connected, and the fourth end and the first end of electric capacity of opto-coupler are connected to as first switch circuit 31's second end, electric capacity's second end ground connection.

Specifically, first switch circuit 31 in this application when including opto-coupler and electric capacity, when differential signal was received to the first end of opto-coupler and second end, differential signal's voltage is different, switch on between the first end of the opto-coupler that corresponds this moment and the second end, switch on between the third end of the opto-coupler that corresponds and the fourth end, the second end output high level signal of the fourth end of the opto-coupler that corresponds, electric capacity is used for filtering this high level signal to guarantee that first switch circuit 31's second end output is stable high level signal. On the basis of the present embodiment, the second predetermined level signal is a high level signal.

It should be noted that, in the present application, but not limited to: the positive pole of emitting diode in the opto-coupler is as the first end of opto-coupler, and the negative pole of emitting diode in the opto-coupler is as the second end of opto-coupler, and the third end of opto-coupler is regarded as to the collector of photosensitive semiconductor transistor in the opto-coupler, and the fourth end of opto-coupler is regarded as to the projecting pole of photosensitive semiconductor transistor. At this time, correspondingly, the voltage (485B) output by the first signal terminal is greater than the output voltage (485A) of the second signal terminal.

As a preferred embodiment, the first switch circuit 31 further includes a fifth resistor, and the fifth resistor is disposed between the power module and the third terminal of the optocoupler.

Wherein, first switch circuit 31 in this application has still utilized the characteristic that the opto-coupler can be kept apart, avoids simulating front end 2 and treater 3 to receive external interference, and the protection is simulated front end 2 and is not influenced by the high pressure that outside (difference signal) probably brought to and the protection treater 3 is not influenced by the high pressure that outside probably brought, avoids the components and parts in the BMS system to be damaged.

In summary, the function of the first switch circuit 31 can be realized through the optocoupler and the capacitor in this embodiment, and each device in the BMS system can be prevented from being interfered by the outside, so as to ensure the reliability of the operation of the BMS system.

As a preferred embodiment, the first switch circuit 31 further includes a first diode and a first resistor;

the first end of the first resistor is connected with the first signal end, the second end of the first resistor is connected with the cathode of the first diode and the first end of the optocoupler, and the anode of the first diode is connected with the second signal end and the second end of the optocoupler respectively.

When the voltage output by the first signal terminal is greater than the output voltage of the second signal terminal, the output current of the first signal terminal may flow back to the second signal output terminal, which may damage the 485 communication chip and/or the 485 communication device connected thereto.

In order to solve the above technical problem, the first diode is disposed between the first signal terminal and the second signal terminal in this embodiment, so as to prevent the output current of the first signal terminal with higher output voltage from flowing backward to the second signal terminal with lower output voltage, prevent the 485 communication chip and/or the 485 communication device in the BMS system from being damaged, and ensure the reliability of the BMS system.

It should be noted that the arrangement between the first signal terminal and the second signal terminal in the present application is not limited to the first diode, and may be other anti-backflow devices, and the present application is not limited thereto.

As a preferred embodiment, the second switch circuit 32 includes a controllable switch, a control terminal of the controllable switch is connected to the second terminal of the first switch circuit 31, a first terminal of the controllable switch is respectively connected to the output terminal of the power module and the predetermined pin of the processor 3, and a second terminal of the controllable switch is grounded.

The embodiment aims to provide a specific implementation manner of the second switch circuit 32, specifically, when the first switch circuit 31 is an optocoupler, and the output second preset level signal is a high level signal, the controllable switch is turned on after the control end of the controllable switch receives the high level signal, the output end of the second switch circuit 32 is changed from the high level to the low level, at this time, the corresponding processor 3 controls the switch to be turned on, so that the DC/DC5 is powered on, and the 485 communication chip is powered on.

The controllable switch in this application may be an NPN (Negative-positive-Negative) type triode, or may be another controllable switch that is conducted between the first end and the second end when the control end is a high level signal, and this application is not limited herein.

In addition, the power module in this application can be the power module that can always output power that sets up alone in the BMS system to guarantee that controllable switch can stable switch on or turn off, also can be the group battery, then through carrying out transform and adjustment to the output voltage of group battery, so that its stable switch on or turn off of control controllable switch, the specific implementation of power module and power module's output voltage is what, this application does not do particular restriction here, as long as can realize the reliable control to controllable switch.

As a preferred embodiment, the third switching circuit 33 comprises a second diode having an anode connected to the second terminal of the first switching circuit 31 and a cathode connected to the wake-up terminal of the analog front end 2.

The embodiment aims to provide a specific implementation manner of the third switching circuit 33, specifically, when the third switching circuit 33 includes a second diode, and when the first switching circuit 31 includes an optocoupler, and the second terminal of the first switching circuit 31 outputs a high level signal, the second diode is turned on, outputs a high level signal to the wake-up pin of the analog front end 2, and the analog front end 2 is woken up.

In addition, when the BMS system does not enter the deep sleep mode, the wake-up pin of the analog front end 2 may be controlled to be at a high level and the control switch may be turned on by the wake-up circuit 1, or the wake-up pin of the analog front end 2 may be controlled to be at a high level and the control switch may be turned on after the processor 3 is powered on. The present invention is not particularly limited herein, depending on the actual situation.

In summary, the second diode in this embodiment can realize the function of the third switch circuit 33, and the implementation manner is simple and reliable.

As a preferred embodiment, the second switch circuit 32 further includes a second resistor, a third resistor, and a fourth resistor;

one end of the second resistor is connected with the output end of the power module, the other end of the second resistor is connected with the first end of the controllable switch and the preset pin respectively, one end of the third resistor is connected with the output end of the first switch circuit 31, the other end of the third resistor is connected with one end of the fourth resistor and the control end of the controllable switch respectively, and the other end of the fourth resistor is connected with the second end of the controllable switch.

In order to improve the reliability of the second switch circuit 32, the three resistors are further provided in this embodiment, which can ensure the stability of the voltage at the control end of the controllable switch, so that the control end of the controllable switch can receive a stable high-level signal, thereby ensuring the reliability of the third controllable switch.

Specifically, when the power module is a battery pack, the resistance values of the three resistors may be adjusted to enable the voltage input to the control terminal of the controllable switch to be a voltage capable of controlling the controllable switch to be stably switched on and off, and the corresponding output voltage of the battery pack and the resistance values of the three resistors are not particularly limited herein and are specifically implemented according to actual conditions.

In summary, the controllable switch and the related resistor in the embodiment can realize the function of the second switch circuit 32, and the realization method is simple and reliable.

Referring to fig. 5, fig. 5 is a block diagram illustrating another BMS system according to the present invention.

As a preferred embodiment, the method further comprises the following steps:

the isolation power supply 51 is arranged between the output end of the DC/DC5 and the power supply end of the 485 communication chip;

and the communication isolation chip 52 is arranged between the output end of the processor 3 and the communication end of the 485 communication chip.

In order to ensure the reliability of power supply with the 485 communication chip and prevent the power supply end from being interfered by the outside, the front end of the 485 communication chip in the application is also provided with an isolation power supply 51.

In addition, in order to ensure the reliability of the communication between the processor 3 and the 485 communication chip and prevent the communication from receiving external interference signals, the communication isolation chip 52 is further provided in the embodiment, so as to improve the reliability of the BMS system.

As a preferred embodiment, the method further comprises the following steps:

and a linear regulator 53 disposed between the output terminal of DC/DC5 and a power supply terminal of processor 3 for regulating the output voltage of DC/DC5 to a preset voltage to power processor 3.

In another way of supplying power to processor 3, the present embodiment provides linear regulator 53 for adjusting the output voltage of DC/DC5, which corresponds to the LDO shown in fig. 5, so that DC/DC5 can supply power to processor 3 through linear regulator 53. At the output of DC/DC5, 5V is used to power the 485 communication chip, and processor 3 requires a 3.3V supply voltage, and linear regulator 53 converts the 5V supply voltage to 3.3V to power processor 3.

It can be seen that the present embodiment provides another way of supplying power to the processor 3, which increases the flexibility and variety of the processor 3 being powered.

It is to be noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the utility model. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (9)

1. A BMS system is characterized by comprising an analog front end, a switch, a DC/DC converter DC/DC, a processor, a 485 communication chip and a wake-up circuit;

the voltage output end of the analog front end is connected with the power supply end of the processor, the control end of the processor is connected with the control end of the switch, the input end of the wake-up circuit is respectively connected with the differential signal end of the 485 communication chip, the first output end of the wake-up circuit is connected with the preset pin of the processor, the second output end of the wake-up circuit is connected with the wake-up pin of the analog front end, and when the differential signal end of the 485 communication chip is connected with an external 485 communication device, the differential signal end outputs differential signals;

the analog front end is used for converting the output voltage of the battery pack to supply power for the processor;

the processor is used for controlling the switch to be conducted when the power supply end of the processor has input voltage and the level signal of the preset pin of the processor changes;

the wake-up circuit is used for controlling the level signal of the first output end of the wake-up circuit to change when a differential signal is input into the input end of the wake-up circuit, and controlling the second output end of the wake-up circuit to output a first preset level signal, so that the analog front end is woken up.

2. The BMS system of claim 1, comprising a first switching circuit, a second switching circuit, and a third switching circuit;

the first end of the first switch circuit is connected with the differential signal end, the second end of the first switch circuit is respectively connected with the first end of the second switch circuit and the first end of the third switch circuit, the second end of the second switch circuit is a first output end of the wake-up circuit, and the second end of the third switch circuit is a second output end of the wake-up circuit;

the first switch circuit is used for being conducted when the differential signal is input at the first end of the first switch circuit, so that the second end of the first switch circuit outputs a second preset level signal;

the second switch circuit is used for being conducted when the first end of the second switch circuit receives the second preset level signal, so that the level signal of the second end of the second switch circuit is changed;

the third switch circuit is used for being conducted when the first end of the third switch circuit receives the second preset level signal, so that the second end of the third switch circuit outputs the first preset level signal, and the analog front end is awakened.

3. The BMS system of claim 2, wherein the first switching circuit comprises an optocoupler and a capacitor, the differential signal terminals comprise a first signal terminal and a second signal terminal;

the first end of the optical coupler is connected with the first signal end, the second end of the optical coupler is connected with the second signal end, the third end of the optical coupler is connected with the output end of the power module, the fourth end of the optical coupler is connected with the first end of the capacitor and serves as the second end of the first switch circuit, and the second end of the capacitor is grounded.

4. The BMS system of claim 3, wherein the first switching circuit further comprises a first diode and a first resistor;

the first end of the first resistor is connected with the first signal end, the second end of the first resistor is connected with the cathode of the first diode and the first end of the optocoupler, and the anode of the first diode is connected with the second signal end and the second end of the optocoupler respectively.

5. The BMS system of claim 3, wherein the second switching circuit comprises a controllable switch having a control terminal connected to the second terminal of the first switching circuit, a first terminal of the controllable switch being connected to the output terminal of the power module and a predetermined pin of the processor, respectively, and a second terminal of the controllable switch being connected to ground.

6. The BMS system of claim 5, wherein the third switching circuit includes a second diode having an anode connected to the second terminal of the first switching circuit and a cathode connected to the wake-up terminal of the analog front end.

7. The BMS system of claim 6, wherein the second switching circuit further comprises a second resistor, a third resistor, and a fourth resistor;

one end of the second resistor is connected with the output end of the power supply module, the other end of the second resistor is connected with the first end of the controllable switch and the preset pin respectively, one end of the third resistor is connected with the output end of the first switch circuit, the other end of the third resistor is connected with one end of the fourth resistor and the control end of the controllable switch respectively, and the other end of the fourth resistor is connected with the second end of the controllable switch.

8. The BMS system of any of claims 1-7, further comprising:

the isolation power supply is arranged between the output end of the DC/DC and the power supply end of the 485 communication chip;

and the communication isolation chip is arranged between the output end of the processor and the communication end of the 485 communication chip.

9. The BMS system of claim 8, further comprising:

and the linear voltage stabilizer is arranged between the output end of the DC/DC and the power supply end of the processor and is used for adjusting the output voltage of the DC/DC to a preset voltage so as to supply power to the processor.

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