CN215989633U

CN215989633U - Drive level circuit for reducing power consumption of transmitting end of optical communication chip

Info

Publication number: CN215989633U
Application number: CN202122398613.3U
Authority: CN
Inventors: 张�浩; 施家鹏; 吴思聪; 邓青
Original assignee: Nanjing Magnichip Microelectronics Co ltd
Current assignee: Nanjing Magnichip Microelectronics Co ltd
Priority date: 2021-09-30
Filing date: 2021-09-30
Publication date: 2022-03-08
Anticipated expiration: 2031-09-30

Abstract

The utility model discloses a driving stage circuit for reducing power consumption of an emitting end of an optical communication chip, which relates to the technical field of microelectronics, and is used for receiving an optical signal emitted by an optical module and outputting current to an external laser through the driving stage circuit. According to the technical scheme, the power consumption index of the system is met under the condition that the voltage domain is not changed, the power consumption of the emitter of the optical module chip is effectively reduced, and low-power-consumption voltage input and current output are realized.

Description

Drive level circuit for reducing power consumption of transmitting end of optical communication chip

Technical Field

The utility model relates to the technical field of microelectronics, in particular to a driving stage circuit for reducing power consumption of an emitting end of an optical communication chip.

Background

With the arrival of new application scenarios such as cloud computing, 5G, IoT, AI, etc., optical communication needs to solve communication between machines more, thereby bringing about huge market demand changes. From the 5G network architecture of an operator, the speed requirement of a 5G base station (considered according to large concentration, small concentration and non-concentration) is gradually upgraded to 25G or even 100G, and the whole 5G network is expected to bring the requirement of 25Gbps high-speed optical modules of tens of millions of orders, and the market space of billions of yuan is expected to be increased. From the perspective of operators to market price expectation of 5G optical modules, the future home-made replacement of 25G optoelectronic chips will be the main approach and deterministic target for realizing low-cost 5G optical modules.

In the application scenario of the 5G optical module, power consumption is a very central index, and even the commercial application of the whole module is affected. In the system-level design, under the condition of keeping the signal swing constant, the most direct method for reducing the power consumption is to adopt a plurality of voltage domains, and the cost of the scheme is that two direct current voltage regulators are required to be additionally added in the optical module, so that the cost of the whole module is increased. The power consumption is subdivided into the optical transceiver chip, and the power consumption of the transmitting end is far greater than that of the receiving end during working due to the fact that the transmitting end needs to drive the laser, so that if the power consumption of a transmitting link during working can be reduced, the power consumption index of the chip can be met under the condition that the voltage domain is not reduced.

When the current 5G fronthaul network optical transceiver chip works normally, a sending end adopts a DML (direct coupled modulation laser) mode, the range of output driving level bias current is 1.5 mA-50 mA, the range of modulation current is 10 mA-80 mA, and the power consumption requirement of the whole transceiver chip is that the whole power consumption is controlled within 500mW under a typical working state.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a driving stage circuit for reducing power consumption of an emitting end of an optical communication chip so as to solve the problems in the prior art.

In order to achieve the purpose, the utility model provides the following technical scheme:

a drive level circuit for reducing power consumption of an emitting end of an optical communication chip is used for receiving optical signals emitted by an optical module and multiplexing current to output current to an external laser through the drive level circuit, and the drive level circuit comprises a modulation current circuit and a bias current circuit;

the input end of the modulation current circuit forms the input end of the driving stage circuit and is used for receiving an optical signal emitted by the emitting end of the optical module, the modulation current circuit converts the received input voltage into alternating current and outputs the alternating current to the cathode of an external laser through the output end Toutc of the modulation current circuit, and the anode of the external laser is connected with the output end Touta of the modulation current circuit;

the input end of the bias current circuit is connected with the output end Toutc of the modulation current circuit, the output end of the bias current circuit is connected with the negative electrode of the external laser, and the bias current circuit is used for carrying out bias and impedance matching on the received alternating current to obtain the static current for providing the external laser.

Further, the aforementioned modulation current circuit includes an inductor L1, a resistor R1, a transistor Q1, a transistor Q2, a transistor Q3, and a current source I_MODThe bases of the transistor Q1 and the transistor Q2 are respectively connected with the emitter of the optical module and used as the input end of the modulation current circuit, and the emitters of the transistor Q1 and the transistor Q2 are respectively connected with the current source I_MODThe collector of the transistor Q1 is connected to the emitter of the transistor Q3, the collector of the transistor Q3 is connected to one end of the inductor L1, one end of the resistor R1 and the anode of the external laser respectively as the output terminal Touta of the modulation current circuit, the collector of the transistor Q2 forms the output terminal Toutc of the modulation current circuit, the other ends of the inductor L1 and the resistor R1 are connected to the power supply VDD, and the current source I_MODThe negative electrode of (2) is grounded.

Further, the bias current circuit includes a resistor R2, an inductor L2, and a current source I_BIASOne end of the resistor R2 and one end of the inductor L2 form an input end of a bias current circuit, and the other end of the resistor R2 and the other end of the inductor L2 are respectively connected with the capacitor CoutOne terminal of Cout and current source I_BIASThe other end of the resistor R2 and the other end of the inductor L2 form the output end of a bias current circuit, and a current source I_BIASThe other end of the capacitor Cout and the cathode of the capacitor are grounded, respectively.

Further, the aforementioned current source I_BIASComprises I_{BIAS_SINK}Loop, I_{BIAS_SOURCE1}Loop circuit, and I_{BIAS_SOURCE2}Loop circuit, I_{BIAS_SOURCE1}The input end of the loop forms a current source I_BIASInput terminal of (1)_{BIAS_SINK}Output terminal of loop, I_{BIAS_SOURCE1}Output of the loop, and I_{BIAS_SOURCE2}The output end of the loop forms the output end of the bias current circuit;

said I_{BIAS_SOURCE1}The loop comprises a transistor Q7, a transistor Q8, a transistor Q9, a transistor Q10, a transistor Q11, a transistor Q12, an operational amplifier OP2, a variable resistor array R4, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10 and a current source I2, wherein the base of the transistor Q11 is connected with the base of the transistor Q12, and the base of the transistor Q11 forms I_{BIAS_SOURCE1}An input end of the loop circuit, which is used for receiving the bias voltage and performing impedance matching on the bias voltage, the collectors of the transistors Q11 are respectively connected with the collector of the transistor Q12 and then connected with the inverting input end of the operational amplifier OP2, the collector of the transistor Q11 is connected with one end of the variable resistor array R4, the other end of the variable resistor array R4 is respectively connected with one end of the resistor R6 and the power supply VDD, the other end of the resistor R6 is connected with the non-inverting input end of the operational amplifier OP2, the output end of the operational amplifier OP2 is connected with the base of the transistor Q7, the emitter of the transistor Q7 is respectively connected with the collector of the transistor Q8, the base of the transistor Q9 and the base of the transistor Q10, the emitter of the transistor Q8 is connected with one end of the resistor R7, the collector of the transistor Q9 is connected with one end of the resistor R10, the emitter of the transistor Q9 is connected with one end of the resistor R8, the collector of the transistor Q10 is connected with the emitter of the transistor Q11, an emitter of the transistor Q10 is connected to one end of a resistor R9, an emitter of the transistor Q12 is connected to a current source I2, the other end of the resistor R7, the other end of the resistor R8, the other end of the resistor R9, andthe cathodes of the current sources I2 are all grounded, and the collector of the transistor Q7 and the other end of the resistor R10 form I_{BIAS_SOURCE1}An output of the loop.

Further, the foregoing I_{BIAS_SINK}The loop comprises a transistor Q4, a transistor Q5, a transistor Q6, an operational amplifier OP1, a variable resistor array R3, a resistor R5 and a current source I1, wherein the collector of the transistor Q6 is connected with a power supply VDD, the base of the transistor Q5 is connected with the base of a transistor Q6, the collector of the transistor Q5 is respectively connected with the inverting input end of the operational amplifier and one end of the variable resistor array R3, the other end of the variable resistor array R3 is connected with one end of a resistor R5 and connected with the power supply VDD, the other end of the resistor R5, the collector of the transistor Q4 and the base of the transistor Q4 are connected with the non-inverting input end of the operational amplifier 1, and the non-inverting input end and the inverting input end of the operational amplifier OP1 form I_{BIAS_SINK}The input end of the loop, the emitter of the transistor Q4 is connected with the anode of the current source I1, the output end of the operational amplifier OR1 is connected with the base of the transistor Q5 and the base of the transistor Q6, and the emitter of the transistor Q5 and the emitter of the transistor Q6 form I_{BIAS_SINK}The output end of the loop, the negative pole of the current source I1 is grounded, and the collector of the transistor Q6 is connected with the power supply VDD.

Further, the foregoing I_{BIAS_SOURCE2}The loop comprises a transistor Q13, a transistor Q14, a transistor Q15, a transistor Q16, a resistor R11, a resistor R12, a current source I3, a current source I4 and a current source I5, wherein the base of the transistor Q13 and the base of the transistor Q14 form I_{BIAS_SOURCE2}At the input end of the loop, the collector of the transistor Q13 is connected with one end of the resistor R11, one end of the resistor R12 and the base of the transistor Q15, the emitter of the transistor Q13 is connected with the emitter of the transistor Q14 and then connected with the anode of the current source I3, the emitter of the transistor Q15 is connected with the anode of the current source I4, the emitter of the transistor Q16 is connected with the collector of the transistor Q14, the base of the transistor Q16 and the anode of the current source I5, the collector of the transistor Q16 and the collector of the transistor Q15 form I_{BIAS_SOURCE2}The output end of the loop, the other end of the resistor R11 and the other end of the resistor R12 are respectively connected with the power supply VDD and the cathode of the current source I3The negative electrode of the current source I4 and the negative electrode of the current source I5 are all grounded.

Compared with the prior art, the driving stage circuit for reducing the power consumption of the transmitting end of the optical communication chip has the following technical effects by adopting the technical scheme:

the utility model provides a circuit architecture for reducing chip power consumption by adopting a multiplexing current mode in a laser driving circuit, and I can be multiplexed by the technical scheme of the utility model_{BIAS_SOURCE2}The current of the loop effectively reduces the power consumption of the emitter of the optical module chip, meets the power consumption index of the system under the condition of not changing a voltage domain, and realizes the voltage input and current output with low power consumption.

Drawings

FIG. 1 is a schematic diagram of a driver stage circuit according to an exemplary embodiment of the present invention;

FIG. 2 is a drawing I of an exemplary embodiment of the present invention_{BIAS_SINK}Loop and I_{BIAS_SOURCE1}A schematic diagram of a loop;

FIG. 3 is a drawing I of an exemplary embodiment of the present invention_{BIAS_SOURCE2}Schematic diagram of the loop.

Detailed Description

In order to better understand the technical content of the present invention, specific embodiments are described below with reference to the accompanying drawings.

Aspects of the utility model are described herein with reference to the accompanying drawings, in which a number of illustrative embodiments are shown. Embodiments of the utility model are not limited to those shown in the drawings. It is to be understood that the utility model is capable of implementation in any of the numerous concepts and embodiments described hereinabove or described in the following detailed description, since the disclosed concepts and embodiments are not limited to any embodiment. In addition, some aspects of the present disclosure may be used alone, or in any suitable combination with other aspects of the present disclosure.

With reference to the schematic diagram of the exemplary driver stage circuit shown in fig. 1, the power consumed when the receiving end of the conventional optical communication chip drives the external laser is reduced, the power consumption of the receiving end and the transmitting end of the chip is balanced without reducing the voltage domain, and the power consumption index of the chip is satisfied, and a detailed working process of the driver stage circuit is described in more detail with reference to fig. 1 to 3.

As shown in fig. 1, a schematic diagram of an exemplary driver stage circuit for reducing power consumption of a transmitting end of an optical communication chip is used for receiving an optical signal transmitted by an optical module and multiplexing a current through the driver stage circuit to output the current to an external laser, where the driver stage circuit includes a modulation current circuit and a bias current circuit;

The modulation current circuit comprises an inductor L1, a resistor R1, a transistor Q1, a transistor Q2, a transistor Q3 and a current source I_MODThe bases of the transistor Q1 and the transistor Q2 are respectively connected with the emitter of the optical module and used as the input end of the modulation current circuit, and the emitters of the transistor Q1 and the transistor Q2 are respectively connected with the current source I_MODThe collector of the transistor Q1 is connected to the emitter of the transistor Q3, the collector of the transistor Q3 is connected to one end of the inductor L1, one end of the resistor R1 and the anode of the external laser respectively as the output terminal Touta of the modulation current circuit, the collector of the transistor Q2 forms the output terminal Toutc of the modulation current circuit, the other ends of the inductor L1 and the resistor R1 are connected to the power supply VDD, and the current source I_MODThe negative pole of the transistor Q1 and the transistor Q2 form a differential amplifier to control the current outputAn alternating current signal is generated.

The bias current circuit comprises a resistor R2, an inductor L2 and a current source I_BIASOne end of the resistor R2 and one end of the inductor L2 form an input end of a bias current circuit, the other end of the resistor R2 and the other end of the inductor L2 are respectively connected with one end of the capacitor Cout and a current source I_BIASThe other end of the resistor R2 and the other end of the inductor L2 form the output end of a bias current circuit, and a current source I_BIASThe other end of the negative electrode and the capacitor Cout are respectively grounded, and the bias current is directly output to the laser after being subjected to impedance matching by an inductor L2 and a resistor R2 and is a direct current signal I_MODHas a maximum current capacity of more than 100mA, I_BIASThe maximum current capability of the capacitor Cout is larger than 50mA, and the function of the capacitor Cout is to keep the voltage of Vout stable.

With particular reference to FIG. 2, a current source I_BIASComprises I_{BIAS_SINK}Loop, I_{BIAS_SOURCE1}Loop circuit, and I_{BIAS_SOURCE2}Loop circuit, I_{BIAS_SOURCE1}The input end of the loop forms a current source I_BIASInput terminal of (1)_{BIAS_SINK}Output terminal of loop, I_{BIAS_SOURCE1}Output of the loop, and I_{BIAS_SOURCE2}The output end of the loop forms the output end of the bias current circuit;

said I_{BIAS_SOURCE1}The loop comprises a transistor Q7, a transistor Q8, a transistor Q9, a transistor Q10, a transistor Q11, a transistor Q12, an operational amplifier OP2, a 10-bit variable resistor array R4, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10 and a current source I2, wherein the base of the transistor Q11 is connected with the base of the transistor Q12, and the base of the transistor Q11 forms I_{BIAS_SOURCE1}An input end of the loop, configured to receive a bias voltage and perform impedance matching on the bias voltage, a collector of the transistor Q11 is connected to a collector of the transistor Q12 and then connected to an inverting input end of the operational amplifier OP2, a collector of the transistor Q11 is connected to one end of the variable resistor array R4, the other end of the variable resistor array R4 is connected to one end of the resistor R6 and the power supply VDD, the other end of the resistor R6 is connected to a non-inverting input end of the operational amplifier OP2, and an output of the operational amplifier OP2 is connected to the non-inverting input end of the operational amplifier OP2The terminal of the transistor Q7 is connected with the base of the transistor Q7, the emitter of the transistor Q7 is connected with the collector of the transistor Q8, the base of the transistor Q9 and the base of the transistor Q10 respectively, the emitter of the transistor Q8 is connected with one terminal of the resistor R7, the collector of the transistor Q9 is connected with one terminal of the resistor R10, the emitter of the transistor Q9 is connected with one terminal of the resistor R8, the collector of the transistor Q10 is connected with the emitter of the transistor Q11, the emitter of the transistor Q10 is connected with one terminal of the resistor R9, the emitter of the transistor Q12 is connected with the current source I2, the other terminal of the resistor R7, the other terminal of the resistor R8, the other terminal of the resistor R9 and the cathode of the current source I2 are all grounded respectively, the collector of the transistor Q7 and the other terminal of the resistor R10 form I3526_{BIAS_SOURCE1}An output of the loop.

I_{BIAS_SINK}The loop comprises a transistor Q4, a transistor Q5, a transistor Q6, an operational amplifier OP1, a variable resistor array R3, a resistor R5 and a current source I1, wherein the collector of the transistor Q6 is connected with a power supply VDD, the base of the transistor Q5 is connected with the base of a transistor Q6, the collector of the transistor Q5 is respectively connected with the inverting input end of the operational amplifier and one end of the variable resistor array R3, the other end of the 10-bit variable resistor array R3 is connected with one end of a resistor R5 and is connected with the power supply VDD, the other end of the resistor R5, the collector of the transistor Q4 and the base of the transistor Q4 are connected with the non-inverting input end of the operational amplifier OP1, and the non-inverting input end and the inverting input end of the operational amplifier OP1 form I_{BIAS_SINK}The input end of the loop, the emitter of the transistor Q4 is connected with the anode of the current source I1, the output end of the operational amplifier OR1 is connected with the base of the transistor Q5 and the base of the transistor Q6, and the emitter of the transistor Q5 and the emitter of the transistor Q6 form I_{BIAS_SINK}The output end of the loop, the negative pole of the current source I1 is grounded, and the collector of the transistor Q6 is connected with the power supply VDD.

As shown in FIG. 3, I_{BIAS_SOURCE2}The loop comprises a transistor Q13, a transistor Q14, a transistor Q15, a transistor Q16, a resistor R11, a resistor R12, a current source I3, a current source I4 and a current source I5, wherein the base of the transistor Q13 and the base of the transistor Q14 form I_{BIAS_SOURCE2}The input terminal of the loop, the collector of the transistor Q13 and one terminal of the resistor R11, respectivelyOne end of the resistor R12 and the base of the transistor Q15 are connected, the emitter of the transistor Q13 is connected with the emitter of the transistor Q14 and then connected with the anode of the current source I3, the emitter of the transistor Q15 is connected with the anode of the current source I4, the emitter of the transistor Q16 is respectively connected with the collector of the transistor Q14, the base of the transistor Q16 and the anode of the current source I5, and the collector of the transistor Q16 and the collector of the transistor Q15 form I_{BIAS_SOURCE2}The output end of the loop, the other end of the resistor R11 and the other end of the resistor R12 are respectively connected with the power supply VDD, and the cathode of the current source I3, the cathode of the current source I4 and the cathode of the current source I5 are respectively connected with the ground.

The working principle of the utility model is as follows:

adjustable I_{BIAS_SINK}Loop and I_{BIAS_SOURCE1}Under a typical working state, the open-loop gain of the amplifier OP1 is larger than 60dB, the negative feedback formed by the amplifier OP1, the transistor Q5 and the resistor R3 enables the voltage of the non-inverting input end of the amplifier OP1 to be approximately equal to that of the inverting input end, the transistors Q5 and Q6 keep the sizes of single tubes consistent, and the ratio of the number of parallel transistors is 1: m, the open loop gain of the amplifier OP2 is greater than 60dB, the feedback of OP2 is such that the voltage at its non-inverting input is approximately equal to the voltage at its inverting input, the ratio of the resistances of resistors R9 and R10 is 1: n, the overall size ratio of transistors Q9 and Q10 is N:1, where R₁、R₂、R₃、R₄Keeping the resistance types consistent and layout matched, I₁And I₂Keeping the current consistent and the layout matching to realize the consistency of unit precision of the pull-up and pull-down current;

for the output stage with current driving capability up to 100mA, the output tube has large size, and in order to meet the transmission speed of 25Gbps data, the pre-driving capability of the front stage needs to be correspondingly large, so the bias currents I4 and I5 of the pre-driving buffers Q15 and Q16 in FIG. 3 are large, and I is large_{BIAS_SOURCE2}The total pull-down current of the loop output can reach 15mA, so that the bias current output by the bias current circuit can be represented as I_{BIAS_SOURCE1}+I_{BIAS_SOURCE2}-I_{BIAS_SINK}Controlling the proportion of the three components to obtain I in the range of 0-50 mA_BIASElectric current. In a typical operating state, I_BIASIs about 20mA, I can be multiplexed by the circuit of the utility model_{BIAS_SOURCE2}The purpose of reducing the power consumption of the chip is achieved;

when the driving stage circuit provided by the utility model works normally, firstly, I is judged_BIASValue and I_{BIAS_SINK}Magnitude of value, if I_BIASSmall value, no additional I is required_{BIAS_SOURCE1}Current sum I_{BIAS_SOURCE2}Current, only needing I_{BIAS_SINK}Is reduced to I_{BIAS_SINK}-I_BIASA value; if I_BIASIf the value is large, first, I is_{BIAS_SINK}The current is reduced to 0 and then I is increased_{BIAS_SOURCE1}Current sum I_{BIAS_SOURCE2}Current to I_BIAS-I_{BIAS_SINK}The value is obtained.

Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the utility model. Therefore, the protection scope of the present invention should be determined by the appended claims.

Claims

1. A drive level circuit for reducing power consumption of an emitting end of an optical communication chip is used for receiving an optical signal emitted by an optical module and outputting current to an external laser through the drive level circuit, and is characterized in that the drive level circuit comprises a modulation current circuit and a bias current circuit;

2. The driving stage circuit for reducing power consumption of emitter of optical communication chip as claimed in claim 1, wherein the modulation current circuit comprises an inductor L1, a resistor R1, a transistor Q1, a transistor Q2, a transistor Q3, and a current source I_MODThe bases of the transistor Q1 and the transistor Q2 are respectively connected with the emitter of the optical module and used as the input end of the modulation current circuit, and the emitters of the transistor Q1 and the transistor Q2 are respectively connected with the current source I_MODThe collector of the transistor Q1 is connected to the emitter of the transistor Q3, the collector of the transistor Q3 is connected to one end of the inductor L1, one end of the resistor R1 and the anode of the external laser respectively as the output terminal Touta of the modulation current circuit, the collector of the transistor Q2 forms the output terminal Toutc of the modulation current circuit, the other ends of the inductor L1 and the resistor R1 are connected to the power supply VDD, and the current source I_MODThe negative electrode of (2) is grounded.

3. The driving stage circuit for reducing power consumption of the emitting end of the optical communication chip as claimed in claim 1, wherein the bias current circuit comprises a resistor R2, an inductor L2, a current source I_BIASOne end of the resistor R2 and one end of the inductor L2 form an input end of a bias current circuit, the other end of the resistor R2 and the other end of the inductor L2 are respectively connected with one end of the capacitor Cout and a current source I_BIASThe other end of the resistor R2 and the other end of the inductor L2 form the output end of a bias current circuit, and a current source I_BIASThe other end of the capacitor Cout and the cathode of the capacitor are grounded, respectively.

4. The driving stage circuit for reducing power consumption of the emitting end of the optical communication chip as claimed in claim 3, wherein the current source I is configured to provide a current_BIASComprises I_{BIAS_SINK}Loop, I_{BIAS_SOURCE1}Loop circuit, and I_{BIAS_SOURCE2}Loop circuit, I_{BIAS_SOURCE1}The input end of the loop forms a current source I_BIASInput terminal of (1)_{BIAS_SINK}Output terminal of loop, I_{BIAS_SOURCE1}Output of the loop, and I_{BIAS_SOURCE2}The output end of the loop forms the output end of the bias current circuit;

said I_{BIAS_SOURCE1}The loop comprises a transistor Q7, a transistor Q8, a transistor Q9, a transistor Q10, a transistor Q11, a transistor Q12, an operational amplifier OP2, a variable resistor array R4, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10 and a current source I2, wherein the base of the transistor Q11 is connected with the base of the transistor Q12, and the base of the transistor Q11 forms I_{BIAS_SOURCE1}An input end of the loop circuit, which is used for receiving the bias voltage and performing impedance matching on the bias voltage, the collectors of the transistors Q11 are respectively connected with the collector of the transistor Q12 and then connected with the inverting input end of the operational amplifier OP2, the collector of the transistor Q11 is connected with one end of the variable resistor array R4, the other end of the variable resistor array R4 is respectively connected with one end of the resistor R6 and the power supply VDD, the other end of the resistor R6 is connected with the non-inverting input end of the operational amplifier OP2, the output end of the operational amplifier OP2 is connected with the base of the transistor Q7, the emitter of the transistor Q7 is respectively connected with the collector of the transistor Q8, the base of the transistor Q9 and the base of the transistor Q10, the emitter of the transistor Q8 is connected with one end of the resistor R7, the collector of the transistor Q9 is connected with one end of the resistor R10, the emitter of the transistor Q9 is connected with one end of the resistor R8, the collector of the transistor Q10 is connected with the emitter of the transistor Q11, an emitter of the transistor Q10 is connected with one end of the resistor R9, an emitter of the transistor Q12 is connected with the current source I2, the other end of the resistor R7, the other end of the resistor R8, the other end of the resistor R9 and a cathode of the current source I2 are all grounded respectively, and a collector of the transistor Q7 and the other end of the resistor R10 form I_{BIAS_SOURCE1}An output of the loop.

5. The driving stage circuit for reducing power consumption of the emitting end of the optical communication chip as claimed in claim 3, wherein I is_{BIAS_SINK}The loop comprises a transistor Q4, a transistor Q5, a transistor Q6, an operational amplifier OP1, a variable resistor array R3, a resistor R5 and a current sourceI1, the collector of the transistor Q6 is connected with a power supply VDD, the base of the transistor Q5 is connected with the base of the transistor Q6, the collector of the transistor Q5 is respectively connected with the inverting input end of the operational amplifier and one end of the variable resistor array R3, the other end of the variable resistor array R3 is connected with one end of the resistor R5 and is connected with the power supply VDD, the other end of the resistor R5, the collector of the transistor Q4 and the base of the transistor Q4 are connected with the non-inverting input end of the operational amplifier OP1, and the non-inverting input end and the inverting input end of the operational amplifier OP1 form I1_{BIAS_SINK}The input end of the loop, the emitter of the transistor Q4 is connected with the anode of the current source I1, the output end of the operational amplifier OR1 is connected with the base of the transistor Q5 and the base of the transistor Q6, and the emitter of the transistor Q5 and the emitter of the transistor Q6 form I_{BIAS_SINK}The output end of the loop, the negative pole of the current source I1 is grounded, and the collector of the transistor Q6 is connected with the power supply VDD.

6. The driving stage circuit for reducing power consumption of the emitting end of the optical communication chip as claimed in claim 5, wherein I is a voltage level of the driving stage circuit_{BIAS_SOURCE2}The loop comprises a transistor Q13, a transistor Q14, a transistor Q15, a transistor Q16, a resistor R11, a resistor R12, a current source I3, a current source I4 and a current source I5, wherein the base of the transistor Q13 and the base of the transistor Q14 form I_{BIAS_SOURCE2}At the input end of the loop, the collector of the transistor Q13 is connected with one end of the resistor R11, one end of the resistor R12 and the base of the transistor Q15, the emitter of the transistor Q13 is connected with the emitter of the transistor Q14 and then connected with the anode of the current source I3, the emitter of the transistor Q15 is connected with the anode of the current source I4, the emitter of the transistor Q16 is connected with the collector of the transistor Q14, the base of the transistor Q16 and the anode of the current source I5, the collector of the transistor Q16 and the collector of the transistor Q15 form I_{BIAS_SOURCE2}The output end of the loop, the other end of the resistor R11 and the other end of the resistor R12 are respectively connected with the power supply VDD, and the cathode of the current source I3, the cathode of the current source I4 and the cathode of the current source I5 are respectively connected with the ground.