CN215911168U - Display panel, touch panel and display device - Google Patents

Abstract

The embodiment of the present disclosure provides a display panel and a display device, the display panel including: the display device comprises a display substrate, a first bonding area and a second bonding area, wherein the display substrate is provided with a display area and the first bonding area positioned on at least one side of the display area, the first bonding area is provided with a first test pin and a second test pin, the first test pin is connected with the second test pin, and the first test pin and the second test pin are grounded; the first flexible circuit board is bonded to the first bonding area, the first flexible circuit board is provided with a second bonding area, the second bonding area is provided with a third testing pin, a fourth testing pin, a first testing pad and a second testing pad, the third testing pin is connected with the first testing pin and the first testing pad, and the fourth testing pin is connected with the second testing pin and the second testing pad.

Description

Display panel, touch panel and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display panel, a touch panel and a display device.

Background

Along with the development and popularization of electronic devices, such as wearable electronic devices, the antistatic performance of the electronic devices is also more and more important. And electronic equipment develops towards the direction of narrow frame and high screen ratio gradually, and this has restricted the line space of display substrate to a great extent for electronic equipment's antistatic properties is relatively poor.

Therefore, how to improve the antistatic ability of electronic devices is a problem that needs to be solved.

SUMMERY OF THE UTILITY MODEL

An object of the present disclosure is to provide a display panel, a touch panel and a display device, so as to improve the antistatic performance of an electronic device. The specific technical scheme is as follows:

a first aspect of embodiments of the present disclosure provides a display panel, including:

the display device comprises a display substrate, a first bonding area and a second bonding area, wherein the display substrate is provided with a display area and the first bonding area is positioned on at least one side of the display area, the first bonding area is provided with a first test pin and a second test pin, the first test pin is electrically connected with the second test pin, and the first test pin and the second test pin are grounded;

the first flexible circuit board, first flexible circuit board nation decide in first nation decides the district, the second nation decides the district on the first flexible circuit board has, the second nation decides the district and is provided with third test pin and fourth test pin to and first test pad and second test pad, the third test pin with first test pin reaches first test pad is connected, the fourth test pin with the second test pin reaches the second test pad is connected.

In some embodiments, the first test pad and the second test pad are both grounded.

In some embodiments, the first test pin is connected to the second test pin through a connection portion, and the connection portion includes a first metal layer and a first transparent conductive layer which are stacked.

In some embodiments, the display panel further comprises:

the first test pin and the second test pin are grounded through the protection line;

the third test pin passes through the test line and is connected with the first test pad, and the fourth test pin passes through the test line and is connected with the second test pad.

In some embodiments, the protection line includes a second metal layer and a second transparent conductive layer, which are stacked, and a width of the second transparent conductive layer is the same as a distance between two sides of the first test pin and the second test pin that are far away from each other.

In some embodiments, the display panel further comprises:

a first alignment mark disposed in the first bonding area;

and the second alignment identifier is arranged in the second bonding area, and the position of the second alignment identifier is matched with that of the first alignment identifier.

In some embodiments, the first alignment indicator is coupled to ground, and/or the second alignment indicator is coupled to ground.

In some embodiments, the display panel further comprises:

the copper sheet is arranged in an area where the first bonding area does not have the wiring, and the first test pin and the second test pin are connected with the copper sheet.

In some embodiments, the test pin includes a substrate base plate, and a pin first metal layer, a pin first insulating layer, a pin first transparent conductive layer, a pin second transparent conductive layer, and a pin second insulating layer that are located on one side of the substrate base plate and sequentially distributed along a direction away from the substrate base plate, where the pin second transparent conductive layer is connected with the pin first transparent conductive layer through a first via hole, and the test pin includes at least one of the first test pin, the second test pin, the third test pin, and the fourth test pin.

In some embodiments, the display region of the display panel includes a substrate and a pixel circuit located on one side of the substrate, and the pixel circuit includes an active layer, a first gate insulating layer, a first metal layer of the display region, a second gate insulating layer, a second metal layer of the display region, an interlayer dielectric layer, and a third metal layer of the display region, which are sequentially distributed along a direction away from the substrate, wherein the first metal layer of the pin and the first metal layer of the display region are fabricated in the same layer, and the first transparent conductive layer of the pin and the third metal layer of the display region are fabricated in the same layer.

In some embodiments, the display area of the display panel includes at least one organic light emitting device, and the at least one organic light emitting device includes an anode layer, a pixel defining layer, an organic light emitting layer, and a cathode layer, which are sequentially distributed along a direction away from the pixel circuit, wherein the pin second transparent electrode layer and the anode layer are fabricated at the same layer.

A second aspect of the embodiments of the present disclosure provides a touch panel, including:

the touch substrate is provided with a touch display area and a third bonding area positioned on at least one side of the display area, the third bonding area is provided with a fifth test pin and a sixth test pin, the fifth test pin is electrically connected with the sixth test pin, and the fifth test pin and the sixth test pin are grounded;

the second flexible circuit board, the flexible circuit board bind in the third bonding district, the third bonding district has on the second flexible circuit board, the third bonding district is provided with seventh test pin and eighth test pin to and third test pad and fourth test pad, seventh test pin with the sixth test pin reaches the third test pad is connected, the eighth test pin with the fifth test pin reaches the fourth test pad is connected.

In some embodiments, the fourth test pad and the fifth test pad are grounded.

In some embodiments, the test pins include a substrate base plate, and a pin first metal layer, a pin first insulating layer, a pin first transparent conductive layer, a pin second transparent conductive layer, and a pin second insulating layer that are located on one side of the substrate base plate and sequentially distributed along a direction away from the substrate base plate, where the pin second transparent conductive layer is connected to the pin first transparent conductive layer through a first via hole, and the test pins include at least one of the eighth test pin, the fifth test pin, the sixth test pin, and the seventh test pin.

In some embodiments, the touch display area of the touch substrate includes a buffer layer, and a bridge layer, an insulating layer, a touch pattern layer, and a protective layer that are located on one side of the buffer layer and sequentially distributed along a direction away from the buffer layer, where the first transparent conductive layer of the pin and the bridge layer are fabricated on the same layer, and the second transparent conductive layer and the touch pattern layer are fabricated on the same layer.

A third aspect of the embodiments of the present disclosure provides a display device, where the display device includes any one of the display panels described above, or the display device includes any one of the touch panels described above.

The embodiment of the disclosure has the following beneficial effects:

the display panel and the display device provided by the embodiment of the disclosure comprise a display substrate, wherein the display substrate is provided with a display area and a first bonding area positioned on at least one side of the display area, and the first bonding area is provided with a first test pin and a second test pin which are used for bonding impedance test and are connected. The display panel further comprises a first flexible circuit board bonded in the first bonding area, the first flexible circuit board is provided with a second bonding area, and the second bonding area is provided with a third test pin and a fourth test pin which are used for testing bonding impedance. The second bonding area is also provided with a first testing pad and a second testing pad which are used for being connected with an external testing power supply, the first testing pad is connected with the first testing pin through a third testing pin, and the second testing pad is connected with the second testing pin through a fourth testing pin. In the display panel provided by the embodiment of the disclosure, the first test pin and the second test pin for bonding impedance test on the display substrate are grounded, a good ESD discharge channel is formed between the first test pin and the second test pin, and the ESD is conveniently discharged from the discharge channel, so that the antistatic performance of the display panel is improved, and further the antistatic performance of the display device is improved.

Of course, not all advantages described above need to be achieved at the same time to practice any one product or method of the present disclosure.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other embodiments can be obtained by those skilled in the art according to the drawings.

Fig. 1 is a schematic structural diagram of a display panel according to some embodiments of the present disclosure;

FIG. 2 is a schematic structural diagram of a first bonding area of a display substrate and a second bonding area of a flexible printed circuit according to some embodiments of the disclosure;

FIG. 3 is a cross-sectional view taken along the line A-A in FIG. 1;

FIG. 4 is a cross-sectional view taken along the line C-C in FIG. 1;

FIG. 5 is a schematic structural diagram of another display panel according to some embodiments of the present disclosure;

FIG. 6 is a cross-sectional view taken along line B-B of FIG. 1;

fig. 7 is another schematic structural diagram of a first bonding area of a display substrate and a second bonding area of a flexible circuit board according to some embodiments of the disclosure.

Reference numerals: 1-a display substrate; 10-a display area; 11-a first bonding area; 12-a first test pin; 121-pin first metal layer; 122-pin first transparent conductive layer; 123-pin first insulating layer; 124-pin second transparent conductive layer; 125-pin second insulating layer; 13-a second test pin; 14-a protection line; 141-a first protection line; 142-a second protection line; 15-first alignment identification; 2-a first flexible circuit board; 21-a second bonding area; 22-a third test pin; 23-a fourth test pin; 24-a first test pad; 25-a second test pad; 26-test line; 27-second alignment identification; 3-a connecting part; 31 — a first metal layer; 32-a first transparent conductive layer; 4-a first ground structure; 5-a second ground structure; 51-copper sheet; 100-substrate base plate; 101-a first substrate layer; 102-a first waterproof oxygen layer; 103-amorphous silicon layer; 104-a second substrate layer; 105-a second waterproof oxygen layer; 201-a buffer layer; 202-an active layer; 203-a first gate insulating layer; 204-display area first metal layer; 204 a-gate; 206 a-a second electrode plate; 204 b-a first electrode plate; 205 — a second gate insulating layer; 206-display area second metal layer; 207-interlayer dielectric layer; 208-display area third metal layer; 208 a-source; 208 b-drain; 209-a passivation layer; 300-an organic light emitting device; 301-an anode layer; 302-a pixel defining layer; 303 — an organic light emitting layer; 304-a cathode layer; 305-a spacer layer; 400-a planarization layer; 500-an encapsulation layer; 501-a first inorganic encapsulation layer; 502-organic encapsulation layer; 503-a second inorganic encapsulation layer; 600-a touch substrate; 601-a buffer layer; 602-a bridge layer; 603-an insulating layer; 604-touch pattern layer; 605-protective layer.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments that can be derived from the disclosure by one of ordinary skill in the art based on the embodiments in the disclosure are intended to be within the scope of the disclosure.

In the related art, the antistatic performance of the touch display module may be improved by increasing a TVS (Transient Voltage regulator) on the flexible circuit board and increasing a ground area of the copper leakage area, but the method cannot directly protect an ITO (Indium Tin oxide) bridge point of the touch panel, so that the ITO bridge point of the touch panel is easily damaged during an ESD (Electro-Static discharge) test, thereby causing a touch failure of the touch panel.

In order to solve the above problem, embodiments of the present disclosure provide a display panel and a display device, which will be described in detail below with reference to the accompanying drawings. The Display panel includes, but is not limited to, an LCD (Liquid Crystal Display) Display panel, an OLED (Organic Light-Emitting Diode) Display panel, a QLED (Quantum Dot Light-Emitting Diode) Display panel, a mini LED (small Light-Emitting Diode) Display panel, and a micro LED (micro Light-Emitting Diode) Display panel.

As shown in fig. 1 and 2, a display panel provided by an embodiment of the present disclosure includes:

the display device comprises a display substrate 1, wherein the display substrate 1 is provided with a display area 10 and a first bonding area 11 positioned on at least one side of the display area 10, the first bonding area 11 is provided with a first test pin 12 and a second test pin 13 which are used for bonding impedance test, the first test pin 12 is connected with the second test pin 13, and the first test pin 12 and the second test pin 13 are grounded;

the flexible circuit board comprises a first flexible circuit board 2, wherein the first flexible circuit board 2 is bonded to a first bonding area 11, a second bonding area 21 is arranged on the first flexible circuit board 2, the second bonding area 21 is provided with a third testing pin 22 and a fourth testing pin 23 which are used for bonding impedance testing, and a first testing pad 24 and a second testing pad 25 which are used for connecting an external testing power supply, the third testing pin 22 is connected with the first testing pin 12 and the first testing pad 24, and the fourth testing pin 23 is connected with the second testing pin 13 and the second testing pad 25.

The first test pin 12 and the second test pin 13 are used for bonding impedance testing, and when the first flexible circuit board 2 is bonded to the first bonding area 11, the third test pin 22 on the first flexible circuit board 2 is connected to the first test pin 12, so that the first test pin 12 is connected to the first test pad 24 through the third test pin 22. And the fourth test pin 23 on the first flexible circuit board 2 is connected to the second test pin 13 so that the second test pin 13 is connected to the second test pad 25 through the fourth test pin 23. Since the first test pad 24 and the second test pad 25 can be connected to an external test power source, such as a bonding impedance test device, a bonding impedance test between the display substrate 1 and the first flexible circuit board 2 can be implemented by the first test pad 24 and the second test pad 25. The first test pad 24 and the second test pad 25 may be circular windowing pads, and the first test pad 24 and the second test pad 25 may also have other structures.

For example, as shown in fig. 2, the first bonding area 11 is provided with two first test pins 12 and two second test pins 13, and the corresponding second bonding area 21 is provided with two third test pins 22 and two fourth test pins 23, as shown in fig. 2. First bonding area 11 and second bonding area 21 also have a transmit pin, a receive pin, and a Ground pin, among others. It should be noted that, taking a first test pin 12 and a second test pin 13 as an example of a pair of test pins, when two pairs of test pins are disposed in the first bonding area 11, the transmitting terminal pin, the receiving terminal pin and the ground pin may be located between the two pairs of test pins along the long side direction of the first bonding area 11, i.e., the direction S in fig. 2, so that the two pairs of test pins can protect the transmitting terminal pin, the receiving terminal pin and the ground pin. The third test pin 22 and the fourth test pin 23 in the second bonding area 21 are disposed corresponding to the first test pin 12 and the second test pin 13, and therefore the positions of the pins in the second bonding area 21 are not described again.

In some embodiments, the first test pin 12, the second test pin 13, the third test pin 22, and the fourth test pin 23 may have the same structure. For convenience of description, at least one of the first test pin 12, the second test pin 13, the third test pin 22, and the fourth test pin 23 is referred to as a test pin. As shown in fig. 3, the test pin includes a substrate 100, and a first pin metal layer 121, a first transparent pin conductive layer 122, a first pin insulating layer 123, a second transparent pin conductive layer 124, and a second pin insulating layer 125, which are disposed on one side of the substrate 100 and sequentially distributed along a direction away from the substrate 100.

As shown in fig. 3, the second transparent conductive layer 124 is connected to the first transparent conductive layer 122 through a first via. The first and second transparent conductive layers 122 and 124 may be ITO (Indium Tin Oxides) layers or IZO (Indium zinc Oxides) layers.

In some embodiments, the first test pin 12 is connected to the second test pin 13 through a connection portion 3, and the connection portion 3 includes a first metal layer 31 and a first transparent conductive layer 32, which are stacked, as shown in fig. 4.

In the embodiment of the present disclosure, the first metal layer 31 in the connection portion 3 may be fabricated in the same layer as the first metal layers 121 of the first test pin 12 and the second test pin 13, and the first transparent conductive layer 32 in the connection portion 3 may be fabricated in the same layer as the first transparent conductive layers 122 of the first test pin 12 and the second test pin 13. The first test pin 12 and the second test pin 13 may also be connected by other methods, such as by wire connection, which is not specifically limited in the embodiment of the present disclosure. The first transparent conductive layer 32 may be an ITO (Indium Tin oxide) layer, an IZO (Indium zinc oxide) layer, or the like.

In some embodiments, as shown in fig. 5, the display area 10 of the display panel includes a substrate base board 100 and a pixel circuit located on one side of the substrate base board 100, the pixel circuit includes a thin film transistor device and a capacitor device, and the pixel circuit includes a buffer layer 201, an active layer 202 of the thin film transistor device, a first gate insulating layer 203, a first metal layer 204 of the display area, a second gate insulating layer 205, a second metal layer 206 of the display area, an interlayer dielectric layer 207, a third metal layer 208 of the display area, and a passivation layer 209, which are sequentially distributed in a direction away from the substrate base board 100, wherein the first metal layer 204 of the display area includes at least a gate electrode 204a of the thin film transistor device and a first electrode plate 204b of the capacitor device, the second metal layer 206 of the display area includes at least a second electrode plate 206a of the capacitor device, the third metal layer 208 of the display area includes at least a source electrode 208a and a drain electrode 208b of the thin film transistor device, the source and drain electrodes 208a and 208b are connected to the active layer 202 through second vias. In some embodiments, the lead first metal layer 121 is fabricated on the same layer as the display region first metal layer 204, and the lead first transparent conductive layer 122 is fabricated on the same layer as the display region third metal layer 208.

In the embodiment of the present disclosure, the buffer layer 201 is used to protect a thin film transistor device in the pixel circuit, ensure that the thin film transistor device is separated from the substrate 100, prevent impurities on the substrate 100 from affecting the thin film transistor device, and ensure that the thin film transistor device can normally operate. The material of the buffer layer 201 may be silicon oxide, silicon nitride, or silicon oxynitride.

In some embodiments, as shown in fig. 5, the substrate 100 includes a first substrate layer 101, a first water-oxygen resistant layer 102, an amorphous silicon layer 103, a second substrate layer 104, and a second water-oxygen resistant layer 105, which are sequentially stacked.

Wherein the first substrate layer 101 and the second substrate layer 104 may be flexible substrate layers. The first substrate layer 101 and the second substrate layer 104 may be made of a flexible organic material, such as a resin-based organic material, such as polyimide, polycarbonate, polyacrylate, or polyetherimide. The first waterproof oxygen layer 102 and the second waterproof oxygen layer 105 serve to prevent moisture and oxygen from entering the display region 10 of the display panel, causing the display region 10 to fail. The material of the first waterproof oxide layer 102 and the second waterproof oxide layer 105 may be silicon nitride, silicon oxide, aluminum oxide, or the like. The amorphous silicon layer 103 is an insulating layer, which can ensure the insulation of the substrate 100 and prevent the substrate 100 from affecting the electrical connection of the pixel circuit.

In some embodiments, the display region 10 of the display panel includes at least one organic light emitting device 300, the organic light emitting device 300 is located on a side of the pixel circuit away from the substrate 100, and the planarization layer 400 is between the organic light emitting device 300 and the pixel circuit.

In the embodiment of the present disclosure, there may be one or more organic light emitting devices 300, and the pixel circuit is used to supply power to at least one organic light emitting device 300.

In some embodiments, the organic light emitting device 300 is located on a side of the planarization layer 400 away from the pixel circuit, and the organic light emitting device 300 includes an anode layer 301, a pixel defining layer 302, an organic light emitting layer 303, and a cathode layer 304 sequentially distributed along a direction away from the planarization layer 400, wherein the pin second transparent electrode layer 124 is fabricated on the same layer as the anode layer 301.

In the embodiment of the present disclosure, the planarization layer 400 may make the surface of the pixel circuit more flat, and the organic light emitting device 300 may be easily disposed. The material of the planarization layer 400 may be an insulating material such as resin to ensure the insulation of the planarization layer 400. In addition, the pixel defining layer 302 serves to separate the respective sub-pixel regions of the organic light emitting device 300, and in particular, the pixel defining layer 302 may form a plurality of sub-pixel regions by its own groove structure. The organic light emitting layer 303 may include at least a hole transport layer, a light emitting layer, and an electron transport layer, which are stacked.

In some embodiments, as shown in fig. 5, a spacer layer 305 is disposed between the pixel defining layer 302 and the organic light emitting layer 303, and the spacer layer 305 is used for supporting the mask plate when the organic light emitting layer 303 is evaporated.

In some embodiments, as shown in fig. 5, the display area 10 of the display panel further includes an encapsulation layer 500, where the encapsulation layer 500 is located on a side of the organic light emitting device 300 away from the substrate 100, and is used to encapsulate the organic light emitting device 300 and the pixel circuit, protect the display panel, and ensure the encapsulation performance of the display panel.

In some embodiments, as shown in fig. 5, the encapsulation layer 500 includes a first inorganic encapsulation layer 501, an organic encapsulation layer 502, and a second inorganic encapsulation layer 503 sequentially stacked on the cathode layer 304. Namely, a plurality of packaging layers are arranged on the display panel, so that the packaging effect is ensured.

In the embodiment of the present disclosure, as shown in fig. 2, the first test pin 12 and the second test pin 13 are grounded, that is, the first test pin 12 and the second test pin 13 are connected to the first grounding structure 4. Further, the first test pad 24 and the second test pad 25 are grounded, i.e. both the first test pad 24 and the second test pad 25 are connected to the second ground structure 5. Wherein the first grounding structure 4 is electrically connected with the second grounding structure 5.

In some embodiments, the display panel further includes a copper sheet 51, the copper sheet 51 is disposed in an area of the second bonding area 21 without traces, and the first test pad 24 and the second test pad 25 are connected to the copper sheet 51.

In the embodiment of the present disclosure, the second ground structure 5 may be a copper sheet 51 or the second ground structure 5 includes the copper sheet 51. The first test pad 24 and the second test pad 25 are connected to the copper sheet 51, that is, the first test pad 24 and the second test pad 25 are connected to the second ground structure 5, that is, the first test pad 24 and the second test pad 25 are grounded. The copper sheet 51 is placed in the area of the second bonding area 21 without traces, so that the copper sheet 51 is prevented from influencing the traces in the second bonding area 21. Based on this, the first test pin 12 can be connected to the copper sheet 51 through the first test pad 24, and the second test pin 13 can be connected to the copper sheet 51 through the second test pad 25, so as to realize the grounding of the first test pin 12 and the second test pin 13. In addition, the first ground structure 4 and the second ground structure 5 may also be other structures, such as a ground line, and the first test pin 12, the second test pin 13, the first test pad 24, and the second test pad 25 may also be directly grounded through the ground line.

In the display panel provided by the embodiment of the present disclosure, the first test pin 12 and the second test pin 13 used for bonding impedance test on the display substrate 1 are both grounded, and the first test pin 12 and the second test pin 13 are connected through the connection portion 3, so that a good ESD discharge channel is formed between the first test pin 12 and the second test pin 13, which is convenient for ESD discharge through the discharge channel. In addition, because the first test pad 24 and the second test pad 25 are grounded, each test pin can be grounded well, the ground impedance of each test pin, the first test pad 24 and the second test pad 25 is reduced, ESD can be discharged through the first test pad 24 and the second test pad 25 better, and therefore the antistatic performance of the display panel is improved, and the antistatic performance of the display device is further improved.

In some embodiments, as shown in fig. 2, the display panel further includes a protection line 14 disposed in the first bonding area 11, and the first test pin 12 and the second test pin 13 are grounded through the protection line 14; and a test line 26 disposed at the second bonding area 21, wherein the third test pin 22 is connected to the first test pad 24 through the test line 26, and the fourth test pin 23 is connected to the second test pad 25 through the test line 26.

In the embodiment of the disclosure, as shown in fig. 2, one end of the protection line 14 is connected to the first test pin 12 and the second test pin 13, and the other end of the protection line 14 is electrically connected to the first grounding structure 4, so that the first test pin 12 and the second test pin 13 are grounded through the protection line 14. In addition, the second bonding area 21 may be provided with a plurality of test lines 26, the third test pin 22 may be connected to the first test pad 24 through at least one test line 26, and the fourth test pin 23 may be connected to the second test pad 25 through at least another test line 26.

The protection line 14 connects the first test pin 12 and the second test pin 13 to the ground, so that the protection line 14 forms an ESD leakage channel between the first test pin 12, the second test pin 13 and the first ground structure 4, and static electricity on the display substrate 1 is discharged through the leakage channel, thereby improving the anti-static performance of the display substrate 1. The test line 26 connects the third test pin 22 with the first test pad 24, and the test line 26 also connects the fourth test pin 23 with the second test pad 25, so that the impedance test is performed on the display substrate 1 through the first test pad 24 and the second test pad 25.

In some embodiments, the first test pad 24 and the second test pad 25 are both grounded. As shown in fig. 2, the first test pad 24 and the second test pad 25 are further connected to the second grounding structure 5, so that each test pin can be grounded better, ESD can be discharged through an ESD discharge channel formed by the first test pin 12, the second test pin 13 and the protection line 14, and ESD can be discharged through the first test pad 24 and the second test pad 25, thereby further improving the anti-static performance of the display substrate 1 and the display panel.

In some embodiments, the protection line 14 is disposed around a circumference of the display region 11.

In the embodiments of the present disclosure, still taking one first test pin 12 and one second test pin 13 as an example of a pair of test pins, in some embodiments of the present disclosure, when the first bonding area 11 may be provided with a pair of test pins, the first bonding area 11 is provided with a protection line 14 connected to the pair of test pins, and the routing of the protection line 14 is arranged around the periphery of the display area 10. In some embodiments of the present disclosure, as shown in fig. 6, two pairs of test pins may be disposed on the first bonding area 11, two protection lines 14 are disposed on the first bonding area 11, specifically, the protection lines 14 include a first protection line 141 and a second protection line 142, and the beauty team test pins are respectively connected to one protection line. In one example, as shown in fig. 6, the substrate 1 is shown in fig. 6 as being circular. The first bonding area 11 is provided with two pairs of left and right test pins, a pair of test pins located on the left side is connected to the first protection line 141, and a pair of test pins located on the right side is connected to the second protection line 142. The first protection line 141 is semicircular and is routed along the left edge of the display area 10, the second protection line 142 is also semicircular and is routed along the right edge of the display area 10, and the first protection line 141 and the second protection line 142 are overlapped and not connected to each other on the opposite side of the first bonding area 11, so that the first protection line 141 and the second protection line 142 jointly surround the periphery of the display area 10 for a circle.

In the embodiment of the present disclosure, the protection line 14 is disposed around a circumference of the display area 10, so that the transmission end trace of the transmission end pin and the reception end trace of the reception end pin are both located between the protection line 14 and the edge of the display area 10 of the display substrate 1, that is, the trace of the protection line 14 surrounds the transmission end trace and the reception end trace, and thus the transmission end trace and the reception end trace can be protected.

In some embodiments, the protection line 14 includes a second metal layer and a second transparent conductive layer stacked together, as shown in fig. 2, and a width w of the second transparent conductive layer is the same as a distance d between two sides of the first test pin 12 and the second test pin 13 that are far away from each other. The second metal layer of the protection line 14 is connected to the first metal layer 121 of the first test pin 12 and the first metal layer 121 of the second test pin 13 or fabricated on the same layer. The second transparent conductive layer of the protection line 14 is connected to the first test pins 12 and the first transparent conductive layer 122 of the second test pins 13 or fabricated in the same layer.

In the embodiment of the present disclosure, the protection line 14 includes a second metal layer and a second transparent conductive layer, as shown in fig. 2, a width w of the second transparent conductive layer and a width w of the first test pin 12₁Width w of second test pin 13₂And a gap width w between the first test pin 12 and the second test pin 13₃The sum is equal. Based on this, the routing width of the protection line 14 is wider, so that the width of the ESD discharge channel is increased, and ESD on the display substrate 1 can be better discharged. In addition, since the protection line 14 includes the second metal layer and the second transparent conductive layer, the first test pin 12 and the second test pin 13 are grounded through the protection line 14, that is, the first metal layer 121 of the first test pin 12 and the first transparent conductive layer 122 of the second test pin 13 are grounded, so that the first test pin 12 and the second test pin 13 can be grounded better.

In some embodiments, the display panel further includes a first alignment mark 15, where the first alignment mark 15 is disposed on the first bonding area 11;

a second alignment mark 27, wherein the second alignment mark 27 is disposed on the second bonding area 21, and the position of the second alignment mark 27 matches with the first alignment mark 15.

In the embodiment of the present disclosure, the first alignment mark 15 and the second alignment mark 27 are opposite to each other, and are used for positioning the first flexible circuit board 2 when the first flexible circuit board 2 is bonded to the first bonding area 11, so that the third test pin 22 and the fourth test pin 23 on the first flexible circuit board 2 are connected to the first test pin 12 and the second test pin 13 on the first bonding area 11. The first alignment mark 15 and the second alignment mark 27 may be metal sheets, and in order to facilitate alignment between the first alignment mark 15 and the second alignment mark 27, the first alignment mark 15 and the second alignment mark 27 may be disposed outside the first test pin 12 and the third test pin 22, i.e., on a side of the first test pin 12 and the third test pin 22 away from other pins.

For example, as shown in fig. 2, the number of the first alignment marks 15 and the number of the second alignment marks 27 may be two, when the number of the first alignment marks 15 and the number of the second alignment marks 27 are two, each pin of the first bonding area 11 is located between two first alignment marks 15, and each pin of the second bonding area 21 is located between two second alignment marks 27.

In some embodiments, the first alignment marker 15 is grounded and the second alignment marker 27 is grounded.

In some embodiments, the first alignment marker 15 is grounded, or the second alignment marker 27 is grounded.

In the embodiment of the disclosure, as shown in fig. 7, both the first alignment mark 15 and the second alignment mark 27 may be grounded to further enhance the protection of the ESD leakage path between the first test pin 12 and the second test pin 13, the receiving end path corresponding to the receiving end pin, and the emitting end path corresponding to the emitting end pin, so as to further improve the anti-static performance of the display panel.

The above-described disclosed concept in the embodiments of the present disclosure is also applicable to a touch panel.

Specifically, an embodiment of the present disclosure provides a touch panel, including:

the touch substrate is provided with a touch display area and a third bonding area positioned on at least one side of the display area, the third bonding area is provided with a fifth test pin and a sixth test pin, the fifth test pin is electrically connected with the sixth test pin, and the fifth test pin and the sixth test pin are grounded;

the second flexible circuit board is bonded in the third bonding area, the third bonding area is arranged on the second flexible circuit board, the third bonding area is provided with a seventh testing pin, an eighth testing pin, a third testing pad and a fourth testing pad, the seventh testing pin is connected with the sixth testing pin and the third testing pad, and the eighth testing pin is connected with the fifth testing pin and the fourth testing pad.

In the embodiment of the disclosure, the fifth test pin and the sixth test pin on the touch substrate, and the seventh test pin and the eighth test pin on the second flexible circuit board may refer to any one of the first test pin 12, the second test pin 13, the third test pin 22, and the fourth test pin 23, which is not described herein again.

In some embodiments, as shown in fig. 5, the touch display area of the touch substrate 600 includes a buffer layer 601, and a bridge layer 602, an insulating layer 603, a touch pattern layer 604, and a protection layer 605 located on one side of the buffer layer 601 and sequentially distributed along a direction away from the buffer layer 601. In one possible embodiment, the first transparent conductive layer 122 and the bridge layer 602 are fabricated at the same layer, and the second transparent conductive layer 124 and the touch pattern layer 604 are fabricated at the same layer.

In the touch panel provided by the embodiment of the disclosure, the fifth test pin and the sixth test pin for bonding impedance test on the touch panel are grounded, a good ESD discharge channel is formed between the fifth test pin and the sixth test pin, so that ESD is conveniently discharged from the discharge channel, and therefore, the antistatic performance of the touch panel is improved, and further, the antistatic performance of the display device is improved.

It is understood that the substantial difference between the touch panel in this embodiment and the display panel in the foregoing embodiment is the difference in the structure of the touch panel itself, and the structure and the arrangement of each test pin, the structure and the arrangement of each test pad, the structure of the protection line, the connection relationship with each test pin, and the like in this embodiment can be the same as those in the foregoing embodiment.

The embodiment of the present disclosure further provides a display device, which includes the display panel or the touch panel. Because the display panel and the touch panel have good antistatic performance, the display device comprising the display panel or the touch panel also has good antistatic performance. The display device includes, but is not limited to, an electronic bracelet, an electronic watch, a mobile phone, a tablet computer, and the like.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The above description is only for the preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure are included in the scope of protection of the present disclosure.

Claims (17)

1. A display panel, comprising:

the display device comprises a display substrate, a first bonding area and a second bonding area, wherein the display substrate is provided with a display area and the first bonding area is positioned on at least one side of the display area, the first bonding area is provided with a first test pin and a second test pin, the first test pin is electrically connected with the second test pin, and the first test pin and the second test pin are grounded;

the first flexible circuit board, first flexible circuit board nation decide in first nation decides the district, the second nation decides the district on the first flexible circuit board has, the second nation decides the district and is provided with third test pin and fourth test pin to and first test pad and second test pad, the third test pin with first test pin reaches first test pad is connected, the fourth test pin with the second test pin reaches the second test pad is connected.

2. The display panel according to claim 1, wherein the first test pad and the second test pad are both grounded.

3. The display panel according to claim 1, wherein the first test pin is connected to the second test pin through a connection portion, and the connection portion comprises a first metal layer and a first transparent conductive layer which are stacked.

4. The display panel according to claim 1, further comprising:

the first test pin and the second test pin are grounded through the protection line;

the third test pin passes through the test line and is connected with the first test pad, and the fourth test pin passes through the test line and is connected with the second test pad.

5. The display panel according to claim 4, wherein the protection line comprises a second metal layer and a second transparent conductive layer stacked together, and a width of the second transparent conductive layer is the same as a distance between two sides of the first test pin and the second test pin away from each other.

6. The display panel according to claim 4, wherein the protective line is provided around a circumference of the display region.

7. The display panel according to claim 1, further comprising:

a first alignment mark disposed in the first bonding area;

and the second alignment identifier is arranged in the second bonding area, and the position of the second alignment identifier is matched with that of the first alignment identifier.

8. The display panel according to claim 7, wherein the first alignment mark is grounded, and/or the second alignment mark is grounded.

9. The display panel according to claim 1, further comprising:

the copper sheet is arranged in the area where the second bonding area does not have the wiring, and the first test pad and the second test pad are connected with the copper sheet.

10. The display panel of claim 1, wherein the test pins comprise a substrate base plate and a pin first metal layer, a pin first insulating layer, a pin first transparent conductive layer, a pin second transparent conductive layer and a pin second insulating layer which are located on one side of the substrate base plate and sequentially distributed along a direction away from the substrate base plate, wherein the pin second transparent conductive layer is connected with the pin first transparent conductive layer through a first via hole, and the test pins comprise at least one of the first test pin, the second test pin, the third test pin and the fourth test pin.

11. The display panel according to claim 10, wherein the display area of the display panel includes a substrate and a pixel circuit located on one side of the substrate, and the pixel circuit includes an active layer, a first gate insulating layer, a first metal layer of the display area, a second gate insulating layer, a second metal layer of the display area, an interlayer dielectric layer, and a third metal layer of the display area, which are sequentially distributed along a direction away from the substrate, wherein the first metal layer of the pin and the first metal layer of the display area are fabricated in the same layer, and the first transparent conductive layer of the pin and the third metal layer of the display area are fabricated in the same layer.

12. The display panel of claim 11, wherein the display area of the display panel comprises at least one organic light emitting device, and the at least one organic light emitting device comprises an anode layer, a pixel defining layer, an organic light emitting layer, and a cathode layer sequentially distributed along a direction away from the pixel circuit, wherein the pin second transparent electrode layer is fabricated on the same layer as the anode layer.

13. A touch panel, comprising:

the touch substrate is provided with a touch display area and a third bonding area positioned on at least one side of the display area, the third bonding area is provided with a fifth test pin and a sixth test pin, the fifth test pin is electrically connected with the sixth test pin, and the fifth test pin and the sixth test pin are grounded;

the second flexible circuit board, the flexible circuit board bind in the third bonding district, the third bonding district has on the second flexible circuit board, the third bonding district is provided with seventh test pin and eighth test pin to and third test pad and fourth test pad, seventh test pin with the sixth test pin reaches the third test pad is connected, the eighth test pin with the fifth test pin reaches the fourth test pad is connected.

14. The touch panel of claim 13, wherein the fourth test pad and the fifth test pad are grounded.

15. The touch panel of claim 14, wherein the test pins comprise a substrate and a first metal layer, a first insulating layer, a first transparent conductive layer, a second transparent conductive layer and a second insulating layer, which are located on one side of the substrate and sequentially distributed along a direction away from the substrate, wherein the second transparent conductive layer is connected to the first transparent conductive layer through a first via, and the test pins comprise at least one of the eighth test pin, the fifth test pin, the sixth test pin and the seventh test pin.

16. The touch panel of claim 15, wherein the touch display area of the touch substrate comprises a buffer layer, and a bridge layer, an insulating layer, a touch pattern layer and a protective layer that are located on one side of the buffer layer and sequentially distributed along a direction away from the buffer layer, wherein the first transparent conductive layer of the lead and the bridge layer are fabricated on the same layer, and the second transparent conductive layer and the touch pattern layer are fabricated on the same layer.

17. A display device, characterized in that the display device comprises the display panel of any one of claims 1 to 12, or the display device comprises the touch panel of any one of claims 13 to 16.

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