CN215897341U - Power input/output multiplexing circuit - Google Patents
Power input/output multiplexing circuit Download PDFInfo
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- CN215897341U CN215897341U CN202121993327.5U CN202121993327U CN215897341U CN 215897341 U CN215897341 U CN 215897341U CN 202121993327 U CN202121993327 U CN 202121993327U CN 215897341 U CN215897341 U CN 215897341U
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Abstract
The utility model discloses a power input and output multiplexing circuit, which overcomes the troubles of high cost and long development period of the conventional power management chip or plug-in power switch chip. The power input and output multiplexing circuit improves the flexibility of product design, reduces the production cost of products and does not generate larger energy consumption. The power input/output multiplexing circuit shortens the product development cycle, and can be applied to various electronic products which are compatible with various voltage batteries and have various single interfaces for power input/output.
Description
Technical Field
The utility model relates to a multiplexing circuit, in particular to a power input and output multiplexing circuit.
Background
In the prior art, the power management chip or the plug-in power switch chip is used, and the power management chip and the plug-in power switch chip are used, so that the production and manufacturing cost is increased, the system adaptation is involved, the development difficulty is increased, and the development cost is increased.
SUMMERY OF THE UTILITY MODEL
Aiming at the defects in the prior art, the technical problem to be solved by the utility model is to provide a power input and output multiplexing circuit, which is designed to overcome the problems of high cost and long development period of the conventional power management chip or external power switch chip, improve the flexibility of product design, reduce the production cost of products, avoid large energy consumption and shorten the development period of the products.
In order to solve the technical problem, the utility model is realized by the following scheme: the utility model provides a power input/output multiplexing circuit, comprising:
the negative electrode of the direct current power supply is grounded;
the MCU processor U1 is provided with 8 functional PIN PINs;
four PMOS transistors, respectively, a PMOS transistor T1, a PMOS transistor T2, a PMOS transistor T3, and a PMOS transistor T4, wherein a source of the PMOS transistor T2 is connected to a negative electrode of the dc POWER supply, a drain thereof is connected to a drain of the PMOS transistor T3, and a drain of the PMOS transistor T3 is further connected to the VCC-1 pin of the MCU processor U1, a source of the PMOS transistor T3 is connected to a source of the PMOS transistor T4, a drain of the PMOS transistor T1 is connected to a drain of the PMOS transistor T4, and a drain of the PMOS transistor T1 is further connected to an external input POWER supply POWER _ IN/OUT;
a resistor R1, a resistor R2, a resistor R3 and a resistor R5, wherein the resistor R1 and the resistor R2 are connected in series, a circuit node between the resistor R1 and the resistor R2 is connected to the gate of the PMOS transistor T2, the resistor R1 is grounded at a non-connection end of the resistor R2, the resistor R2 is connected to a non-connection end of the resistor R1 and a source of the PMOS transistor T1, the resistor R3 is connected to a source of the PMOS transistor T1, the other end of the resistor R6342 is connected to the resistor R5, the other end of the resistor R5 is grounded, and a circuit node between the resistor R4 and the resistor R5 is connected to a PAD-2 pin of the MCU processor U1;
a zener diode D1 having an anode connected to the source of the PMOS transistor T1 and a cathode connected to the drain of the PMOS transistor T2;
one end of the capacitor C1 is connected to the cathode of the voltage stabilizing diode D1, and the other end of the capacitor C1 is grounded;
a resistor R4, an NPN transistor Q1, a resistor R6 and a resistor R7, wherein the resistor R4 is connected between the gate of the PMOS transistor T1 and the drain of the PMOS transistor T1, the collector of the NPN transistor Q1 is connected to the gate of the PMOS transistor T1, the emitter of the NPN transistor Q1 is grounded, the bases of the NPN transistor Q1 are respectively connected with the resistor R6 and the resistor R7, the other end of the resistor R6 is connected to the PA2-4 pin of the MCU processor U1, and the other end of the resistor R7 is connected to the emitter of the NPN transistor Q1;
a resistor R8, an NPN transistor Q2, a resistor R10 and a resistor R12, wherein the resistor R8 is connected between the gate of the PMOS transistor T3 and the drain of the PMOS transistor T3, the collector of the NPN transistor Q2 is connected to the gate of the PMOS transistor T1, the emitter of the NPN transistor Q2 is grounded, the bases of the NPN transistor Q2 are respectively connected with the resistor R10 and the resistor R12, the other end of the resistor R10 is connected to the PA1-3 pin of the MCU processor U1, and the other end of the resistor R12 is connected to the emitter of the NPN transistor Q2;
a resistor R9, an NPN transistor Q3, a resistor R11 and a resistor R13, wherein the resistor R9 is connected between the gate of the PMOS transistor T4 and the drain of the PMOS transistor T4, the collector of the NPN transistor Q3 is connected to the gate of the PMOS transistor T1, the emitter of the NPN transistor Q3 is grounded, the bases of the NPN transistor Q3 are respectively connected with the resistor R11 and the resistor R13, the other end of the resistor R11 is connected to the PA1-3 pin of the MCU processor U1, and the other end of the resistor R13 is connected to the emitter of the NPN transistor Q3;
and a capacitor C2, having one end connected to the drain of the PMOS transistor T1 and the other end connected to ground.
Further, the PMOS transistor T1, the PMOS transistor T2, the PMOS transistor T3 and the PMOS transistor T4 are all transistors of WPM2341A-3/TR type.
Further, the NPN transistor Q1, the NPN transistor Q2, and the NPN transistor Q3 are all PMBT3904 transistors.
Further, the zener diode D1 is a diode of a model SS 24.
Compared with the prior art, the utility model has the beneficial effects that: the power input/output multiplexing circuit overcomes the troubles of high cost and long development period of the conventional power management chip or plug-in power switch chip.
The power input and output multiplexing circuit improves the flexibility of product design, reduces the production cost of products and does not generate larger energy consumption.
The power input/output multiplexing circuit shortens the product development cycle, and can be applied to various electronic products which are compatible with various voltage batteries and have various single interfaces for power input/output.
Drawings
FIG. 1 is a first partial circuit diagram of a power input/output multiplexing circuit according to the present invention.
Fig. 2 is a second partial circuit diagram of the power input/output multiplexing circuit according to the present invention.
FIG. 3 is a third partial circuit diagram of the power I/O multiplexing circuit of the present invention.
FIG. 4 is a fourth partial circuit diagram of the power I/O multiplexing circuit of the present invention.
FIG. 5 is a circuit diagram of the MCU processor of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, and thus the protection scope of the present invention is more clearly and clearly defined. It should be apparent that the described embodiments of the present invention are only some embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1: the concrete structure of the utility model is as follows:
referring to fig. 1-5, the partial circuit diagrams of fig. 1-4 are connected according to a-A, B-B, C-C, D-D in the figure to form a general diagram of the power input/output multiplexing circuit of the present invention.
The utility model relates to a power input/output multiplexing circuit, which comprises:
the negative electrode of the direct current power supply is grounded;
the MCU processor U1 is provided with 8 functional PIN PINs, and the MCU processor U1 adopts a processor of STM32 model;
four PMOS transistors, respectively, a PMOS transistor T1, a PMOS transistor T2, a PMOS transistor T3, and a PMOS transistor T4, wherein a source of the PMOS transistor T2 is connected to a negative electrode of the dc POWER supply, a drain thereof is connected to a drain of the PMOS transistor T3, and a drain of the PMOS transistor T3 is further connected to the VCC-1 pin of the MCU processor U1, a source of the PMOS transistor T3 is connected to a source of the PMOS transistor T4, a drain of the PMOS transistor T1 is connected to a drain of the PMOS transistor T4, and a drain of the PMOS transistor T1 is further connected to an external input POWER supply POWER _ IN/OUT;
a resistor R1, a resistor R2, a resistor R3 and a resistor R5, wherein the resistor R1 and the resistor R2 are connected in series, a circuit node between the resistor R1 and the resistor R2 is connected to the gate of the PMOS transistor T2, the resistor R1 is grounded at a non-connection end of the resistor R2, the resistor R2 is connected to a non-connection end of the resistor R1 and a source of the PMOS transistor T1, the resistor R3 is connected to a source of the PMOS transistor T1, the other end of the resistor R6342 is connected to the resistor R5, the other end of the resistor R5 is grounded, and a circuit node between the resistor R4 and the resistor R5 is connected to a PAD-2 pin of the MCU processor U1;
a zener diode D1 having an anode connected to the source of the PMOS transistor T1 and a cathode connected to the drain of the PMOS transistor T2;
one end of the capacitor C1 is connected to the cathode of the voltage stabilizing diode D1, and the other end of the capacitor C1 is grounded;
a resistor R4, an NPN transistor Q1, a resistor R6 and a resistor R7, wherein the resistor R4 is connected between the gate of the PMOS transistor T1 and the drain of the PMOS transistor T1, the collector of the NPN transistor Q1 is connected to the gate of the PMOS transistor T1, the emitter of the NPN transistor Q1 is grounded, the bases of the NPN transistor Q1 are respectively connected with the resistor R6 and the resistor R7, the other end of the resistor R6 is connected to the PA2-4 pin of the MCU processor U1, and the other end of the resistor R7 is connected to the emitter of the NPN transistor Q1;
a resistor R8, an NPN transistor Q2, a resistor R10 and a resistor R12, wherein the resistor R8 is connected between the gate of the PMOS transistor T3 and the drain of the PMOS transistor T3, the collector of the NPN transistor Q2 is connected to the gate of the PMOS transistor T1, the emitter of the NPN transistor Q2 is grounded, the bases of the NPN transistor Q2 are respectively connected with the resistor R10 and the resistor R12, the other end of the resistor R10 is connected to the PA1-3 pin of the MCU processor U1, and the other end of the resistor R12 is connected to the emitter of the NPN transistor Q2;
a resistor R9, an NPN transistor Q3, a resistor R11 and a resistor R13, wherein the resistor R9 is connected between the gate of the PMOS transistor T4 and the drain of the PMOS transistor T4, the collector of the NPN transistor Q3 is connected to the gate of the PMOS transistor T1, the emitter of the NPN transistor Q3 is grounded, the bases of the NPN transistor Q3 are respectively connected with the resistor R11 and the resistor R13, the other end of the resistor R11 is connected to the PA1-3 pin of the MCU processor U1, and the other end of the resistor R13 is connected to the emitter of the NPN transistor Q3;
and a capacitor C2, having one end connected to the drain of the PMOS transistor T1 and the other end connected to ground.
A preferred technical solution of this embodiment: the PMOS transistor T1, the PMOS transistor T2, the PMOS transistor T3 and the PMOS transistor T4 are all transistors of WPM2341A-3/TR type.
A preferred technical solution of this embodiment: the NPN type triode Q1, the NPN type triode Q2 and the NPN type triode Q3 are all of PMBT3904 type triodes.
A preferred technical solution of this embodiment: the voltage stabilizing diode D1 adopts a diode of SS24 type.
Example 2:
the utility model provides a power input/output multiplexing circuit which comprises an MCU (microprogrammed control unit) processor U1, a polymer battery (namely a direct-current power supply), four PMOS (P-channel metal oxide semiconductor) transistors, three NPN (negative-positive-negative) triodes, a Schottky diode, thirteen resistors and two capacitors. The schottky diode is zener diode D1.
IN the circuit, the gate of a PMOS transistor T2 is connected to GND through a resistor R1, the PMOS transistor T2 is turned on by default under the condition that a polymer battery BAT1 (i.e., a direct current POWER supply) is powered, so as to supply POWER to POWER _ SYS, 4pin outputs high level after the MCU processor U1 is started, the collector of an NPN triode Q1 is turned on due to high level, the base of the NPN triode Q1 is turned on due to high level, the collector of the NPN triode Q1 is connected to the gate of the PMOS transistor T1, at this time, the gate of the PMOS transistor T1 is turned on due to being pulled low, and an external input POWER supply POWER _ IN/OUT is connected to a zener diode D1 after passing through the PMOS transistor T1, and finally supplies POWER to POWER _ SYS.
When external output application is needed, 4pin of the MCU processor U1 outputs a low level, a collector of the NPN transistor Q1 is a high level, a base of the NPN transistor Q1 is a low level and is not turned on, a collector of the NPN transistor Q1 is connected to a gate of the PMOS transistor T1, at this time, the gate and the drain of the PMOS transistor T1 are the same and are not turned on due to a voltage difference, 3pin of the MCU processor U1 outputs a high level, the NPN transistor Q2 is turned on due to the high level of the collector, the base of the NPN transistor Q2 is a high level, a collector of the NPN transistor Q2 is connected to the gate of the PMOS transistor T3, at this time, the gate of the PMOS transistor T3 is turned on due to being pulled low, and the input/output conversion and multiplexing are achieved by supplying power to the outside through the PMOS transistor T4.
In summary, the power input/output multiplexing circuit of the utility model overcomes the disadvantages of high cost and long development period of the conventional power management chip or external power switch chip. The power input and output multiplexing circuit improves the flexibility of product design, reduces the production cost of products and does not generate larger energy consumption. The power input/output multiplexing circuit shortens the product development cycle, and can be applied to various electronic products which are compatible with various voltage batteries and have various single interfaces for power input/output.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (4)
1. A power input output multiplexing circuit, comprising:
the negative electrode of the direct current power supply is grounded;
the MCU processor U1 is provided with 8 functional PIN PINs;
four PMOS transistors, respectively, a PMOS transistor T1, a PMOS transistor T2, a PMOS transistor T3, and a PMOS transistor T4, wherein a source of the PMOS transistor T2 is connected to a negative electrode of the dc POWER supply, a drain thereof is connected to a drain of the PMOS transistor T3, and a drain of the PMOS transistor T3 is further connected to the VCC-1 pin of the MCU processor U1, a source of the PMOS transistor T3 is connected to a source of the PMOS transistor T4, a drain of the PMOS transistor T1 is connected to a drain of the PMOS transistor T4, and a drain of the PMOS transistor T1 is further connected to an external input POWER supply POWER _ IN/OUT;
a resistor R1, a resistor R2, a resistor R3 and a resistor R5, wherein the resistor R1 and the resistor R2 are connected in series, a circuit node between the resistor R1 and the resistor R2 is connected to the gate of the PMOS transistor T2, the resistor R1 is grounded at a non-connection end of the resistor R2, the resistor R2 is connected to a non-connection end of the resistor R1 and a source of the PMOS transistor T1, the resistor R3 is connected to a source of the PMOS transistor T1, the other end of the resistor R6342 is connected to the resistor R5, the other end of the resistor R5 is grounded, and a circuit node between the resistor R4 and the resistor R5 is connected to a PAD-2 pin of the MCU processor U1;
a zener diode D1 having an anode connected to the source of the PMOS transistor T1 and a cathode connected to the drain of the PMOS transistor T2;
one end of the capacitor C1 is connected to the cathode of the voltage stabilizing diode D1, and the other end of the capacitor C1 is grounded;
a resistor R4, an NPN transistor Q1, a resistor R6 and a resistor R7, wherein the resistor R4 is connected between the gate of the PMOS transistor T1 and the drain of the PMOS transistor T1, the collector of the NPN transistor Q1 is connected to the gate of the PMOS transistor T1, the emitter of the NPN transistor Q1 is grounded, the bases of the NPN transistor Q1 are respectively connected with the resistor R6 and the resistor R7, the other end of the resistor R6 is connected to the PA2-4 pin of the MCU processor U1, and the other end of the resistor R7 is connected to the emitter of the NPN transistor Q1;
a resistor R8, an NPN transistor Q2, a resistor R10 and a resistor R12, wherein the resistor R8 is connected between the gate of the PMOS transistor T3 and the drain of the PMOS transistor T3, the collector of the NPN transistor Q2 is connected to the gate of the PMOS transistor T1, the emitter of the NPN transistor Q2 is grounded, the bases of the NPN transistor Q2 are respectively connected with the resistor R10 and the resistor R12, the other end of the resistor R10 is connected to the PA1-3 pin of the MCU processor U1, and the other end of the resistor R12 is connected to the emitter of the NPN transistor Q2;
a resistor R9, an NPN transistor Q3, a resistor R11 and a resistor R13, wherein the resistor R9 is connected between the gate of the PMOS transistor T4 and the drain of the PMOS transistor T4, the collector of the NPN transistor Q3 is connected to the gate of the PMOS transistor T1, the emitter of the NPN transistor Q3 is grounded, the bases of the NPN transistor Q3 are respectively connected with the resistor R11 and the resistor R13, the other end of the resistor R11 is connected to the PA1-3 pin of the MCU processor U1, and the other end of the resistor R13 is connected to the emitter of the NPN transistor Q3;
and a capacitor C2, having one end connected to the drain of the PMOS transistor T1 and the other end connected to ground.
2. The power input/output multiplexing circuit of claim 1, wherein the PMOS transistor T1, the PMOS transistor T2, the PMOS transistor T3 and the PMOS transistor T4 are all WPM2341A-3/TR type transistors.
3. A power input/output multiplexing circuit according to claim 1, wherein said NPN transistor Q1, NPN transistor Q2 and NPN transistor Q3 are all PMBT3904 model transistors.
4. The power input/output multiplexing circuit of claim 1, wherein the zener diode D1 is a type SS24 diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121993327.5U CN215897341U (en) | 2021-08-24 | 2021-08-24 | Power input/output multiplexing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121993327.5U CN215897341U (en) | 2021-08-24 | 2021-08-24 | Power input/output multiplexing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215897341U true CN215897341U (en) | 2022-02-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202121993327.5U Active CN215897341U (en) | 2021-08-24 | 2021-08-24 | Power input/output multiplexing circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN215897341U (en) |
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2021
- 2021-08-24 CN CN202121993327.5U patent/CN215897341U/en active Active
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