CN215871617U - Signal interface, control chip and video processing equipment - Google Patents
Signal interface, control chip and video processing equipment Download PDFInfo
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Abstract
The utility model discloses a signal interface, a control chip and video processing equipment. Wherein, the device includes: the display device comprises a first interface connector, a control chip and a memory, wherein the first interface connector is used for receiving an extended display screen identification data EDID request sent by signal source equipment and sending the EDID request to the control chip, and the EDID request is used for requesting EDID of a display of an image to be displayed; the control chip is used for responding to the EDID request, reading the target EDID of the display from the memory and sending the read target EDID to the first interface connector; a memory for storing a target EDID of the display; the first interface connector is further configured to send the target EDID to the signal source device. The utility model solves the technical problems of complicated operation steps and high operation cost when the EDID locking function is realized in the related technology.
Description
Technical Field
The utility model relates to the field of communication, in particular to a signal interface and a control chip.
Background
At present, a media server as a device for providing a video source has become a mainstream, an interface is difficult to realize source plugging and then output an original picture, and in the related art, three schemes exist to solve the above problems: 1) the method can be realized by software configuration on an X86(The X86 architecture) host, and The EDID of The output device is locked by using software to ensure The effect of maintaining The source picture; 2) when the video source is processed and output by an FPGA (Field Programmable Gate Array), the layers are stored, so that the interface can output the original picture after plugging in and unplugging the source. 3) The conversion is done using a single dedicated video processing chip to achieve DP input and DP output, EDID modification can be achieved because the output signal is processed and regenerated in the process, independent of the previous input signal. However, the solution using the above solution has the following problems: 1) the software is manually set, and the operation process is relatively complex; 2) the FPGA processing mode has higher cost and longer development period; 3) the requirement on the chip is higher, and the products are fewer in the market and higher in price.
In view of the above problems, no effective solution has been proposed.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a signal interface and a control chip, which are used for at least solving the technical problems of complicated operation steps and high operation cost when an EDID locking function is realized in the related technology.
According to an aspect of an embodiment of the present invention, there is provided a signal interface including: the display device comprises a first interface connector, a control chip and a memory, wherein the first interface connector is used for receiving an extended display screen identification data EDID request sent by signal source equipment and sending the EDID request to the control chip, and the EDID request is used for requesting EDID of a display of an image to be displayed; the control chip is used for responding to the EDID request, reading the target EDID of the display from the memory and sending the read target EDID to the first interface connector; the memory is used for storing the target EDID of the display; the first interface connector is further configured to send the target EDID to the signal source device.
Optionally, the signal interface further includes: the first interface connector is further used for receiving a signal sent by the signal source device based on the EDID and sending the signal to the second interface connector; the second interface connector is used for receiving the signal sent by the first interface connector and sending the signal to the display for displaying.
Optionally, the signal interface further includes: the first conversion chip is used for converting the EDID request sent by the first signal type into an EDID request of a second signal type, wherein the first signal type is a signal type which cannot be identified by the control chip, and the second signal type is a signal type which can be identified by the control chip.
Optionally, the first signal type is a display interface DP signal, and the second signal type is a high definition multimedia interface HDMI signal.
Optionally, the target EDID includes: the display comprises a physical EDID of the display and a virtual EDID of the display, wherein the physical EDID is EDID read from the display, and the virtual EDID is EDID simulated according to the physical EDID.
Optionally, the memory includes a first storage unit and a second storage unit, wherein the first storage unit is configured to store the physical EDID, and the second storage unit is configured to store the virtual EDID.
Optionally, the memory comprises: the EEPROM is electrically erasable and programmable.
According to another aspect of the embodiments of the present invention, there is provided a control chip including: the display device comprises a receiving unit, a processing unit and a sending unit, wherein the receiving unit is used for receiving an extended display screen identification data EDID request sent by a signal source device from a first interface connector of a signal interface, and the EDID request is used for requesting EDID of a display of an image to be displayed; the processing unit is used for responding to the EDID request and reading the target EDID of the display from the memory of the signal interface; the sending unit is configured to send the target EDID to the first interface connector, and is configured to send the target EDID to the signal source device by the first interface connector.
Optionally, the processing unit includes a first control module and a second control module, and the target EDID includes: the display comprises a physical EDID of the display and a virtual EDID of the display, wherein the physical EDID is EDID read from the display, the virtual EDID is EDID simulated according to the physical EDID, the memory comprises a first storage unit and a second storage unit, the first storage unit stores the physical EDID, the second storage unit stores the virtual EDID, and the first control module is used for reading the physical EDID from the first storage unit; the second control module is used for reading the virtual EDID from the second storage unit.
Optionally, the control chip further includes: a conversion unit, configured to convert the EDID request received by the receiving unit from a first signal type to an EDID request of a second signal type, and send the EDID request of the second signal type to the processing unit, where the first signal type is a signal type that cannot be identified by the processing unit, and the second signal type is a signal type that can be identified by the processing unit.
According to another aspect of an embodiment of the present invention, there is provided a video processing apparatus including: any of the signal interfaces described herein.
In the embodiment of the utility model, the first connector is adopted to receive the EDID request sent by the signal source and send the EDID request to the control chip, and the control chip responds to the EDID request, so that the target EDID of the display can be read from the memory, the purpose of sending the read target EDID to the first interface connector is achieved, and the technical problems of complicated operation steps and high operation cost when the EDID locking function is realized in the related technology are further solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the utility model and together with the description serve to explain the utility model without limiting the utility model. In the drawings:
fig. 1 is a block diagram of a signal interface according to embodiment 1 of the present invention;
fig. 2 is a block diagram of the structure of a control chip according to embodiment 1 of the present invention;
FIG. 3 is a diagram of a video source processor architecture in the FPGA mode of the related art;
FIG. 4 is a diagram of a video source processor architecture employing a proprietary chip in the related art;
fig. 5 is a block diagram of a signal interface provided by an alternative embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the utility model described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a system, article, or apparatus that comprises a list of elements is not necessarily limited to those elements explicitly listed, but may include other elements not expressly listed or inherent to such system, article, or apparatus.
First, some terms or terms appearing in the description of the embodiments of the present application are applicable to the following explanations:
DP: display Port standardizes the digital video interface standard for connection of video sources to displays and the like.
EDID: extended display identification data, which contains parameters related to the display and its capabilities, including vendor information, maximum image size, color settings, vendor presets, limits on frequency range, etc.
EEPROM, Electrically Erasable Programmable read only memory, and memory chip without data loss after power failure. Used for erasing the existing information and reprogramming.
Example 1
According to an embodiment of the present invention, there is also provided a signal interface, and fig. 1 is a block diagram of a structure of the signal interface according to embodiment 1 of the present invention, as shown in fig. 1, the apparatus includes: a first interface connector 102, a control chip 104 and a memory 106, which will be described in detail below.
The first interface connector 102 is configured to receive an extended display screen identification data EDID request sent by the signal source device, and send the EDID request to the control chip, where the EDID request is used to request EDID of a display of an image to be displayed; a control chip 104 connected to the first interface connector 102, for responding to the EDID request, reading the target EDID of the display from the memory, and sending the read target EDID to the first interface connector; a memory 106 connected to the control chip 104 for storing the target EDID of the display; the first interface connector 102 is also used to transmit the target EDID to the signal source device.
According to the utility model, the first connector is adopted to receive the EDID request sent by the signal source and send the EDID request to the control chip, and the control chip responds to the EDID request, so that the target EDID of the display can be read from the memory, the purpose of sending the read target EDID to the first interface connector is achieved, and the technical problems of complicated operation steps and high operation cost when an EDID locking function is realized in the related technology are further solved.
As an optional embodiment, the first interface connector is configured to receive an extended display screen identification data EDID request sent by the signal source device, and send the EDID request to the control chip, where the EDID request is used to request EDID of a display of an image to be displayed. The signal source device may be a pc (personal computer), i.e., a personal computer, or may be other image output devices, which is not limited herein. The first interface connector receives an extended display screen identification data EDID request sent by the signal source device, requests the EDID of the display of the image to be displayed, and requests to obtain the target EDID of the display of the image to be displayed. The EDID request is sent to the control chip, so that the control chip can acquire the target EDID. After the first interface connector acquires the EDID, the first interface connector is further used for sending the target EDID to the signal source device so as to use the target EDID for image display on the display screen.
As an alternative embodiment, the control chip is configured to read a target EDID of the display from the memory in response to the EDID request, and send the read target EDID to the first interface connector. Namely, the control chip responds to the EDID request, obtains the feedback result of the target EDID and returns the feedback result to the first interface connector. Among them, the target EDID is of various types, for example: the display comprises a physical EDID of the display and a virtual EDID of the display, wherein the physical EDID is EDID read from the display, and the virtual EDID is EDID simulated according to the physical EDID. The physical EDIDs are various, and different physical EDIDs can be obtained according to different connected displays and different sockets on the displays. The virtual EDID of the display may be set according to a scene and a requirement of an actual application, for example, may be set to be synchronized with the physical EDID, set to record a physical EDID corresponding to a previous display screen, and the like. And reading the corresponding target EDID through setting under different scenes, and sending the target EDID to the first interface connector to realize calling of the target EDID.
As an alternative embodiment, the memory is used for storing the target EDID of the display. The memory can be an electrically erasable programmable read-only memory (EEPROM) to store the target EDID of the display. The memory may include a plurality of storage units, for example, the memory may include a first storage unit and a second storage unit, where the first storage unit is configured to store the physical EDID, and the second storage unit is configured to store the virtual EDID. When storing the physical EDID, the stored physical EDID may be different depending on the connected display, the socket, and the like. The stored virtual EDID can be set to be the physical EDID corresponding to the previous display when being connected to the current display through setting, and the virtual EDID is updated to be the physical EDID corresponding to the current display screen after being connected to the current display. In this optional embodiment, by storing the target EDIDs of the displays, when the displays are connected to different displays, the corresponding target EDIDs can be timely and accurately found according to actual needs.
As an alternative embodiment, the signal interface further comprises: a second interface connector. In the process of transmitting signals by the first interface connector and the second interface connector, the first interface connector is used for receiving signals sent by the signal source equipment based on EDID and sending the signals to the second interface connector; the second interface connector is used for receiving the signal sent by the first interface connector and sending the signal to the display for displaying. Through the alternative embodiment, the process that the signal source device sends the signal to the display can be realized. Specifically, the method may be implemented by receiving, by the first interface connector, a signal sent by the signal source device based on the EDID, and sending the signal to the second interface connector, where the second interface connector sends the signal to the display for displaying.
As an alternative embodiment, the signal interface further comprises: a first conversion chip. The first conversion chip is used for converting the EDID request sent by the first signal type into an EDID request of a second signal type, wherein the first signal type is a signal type which cannot be identified by the control chip, and the second signal type is a signal type which can be identified by the control chip. The first signal type includes a plurality of signals, for example, a display interface DP signal; the second signal type includes a variety of signals, such as High Definition Multimedia Interface (HDMI) signals. Taking the first signal type as a display interface DP signal and the second signal type as a high definition multimedia interface HDMI signal as an example, the first conversion chip is a DP-to-HDMI chip, and converts the DP signal that cannot be identified by the control chip into an HDMI signal that can be identified by the control chip, so as to perform an operation on the EDID request sent by the signal.
It should be noted that, the first interface connector may be connected to the signal source device through a connection line, and the second interface connector may be connected to the display screen through a connection line, where the connection line may be selected as a configuration or a type corresponding to different sockets of the signal source device or the display screen, so as to transmit signals.
Fig. 2 is a block diagram of a control chip according to embodiment 1 of the present invention, and as shown in fig. 2, the apparatus includes: a first interface connector 102, a control chip 104 and a memory 106, which will be described in detail below.
A receiving unit 202, configured to receive, from a first interface connector of the signal interfaces, an extended display screen identification data EDID request sent by the signal source device, where the EDID request is used to request EDID of a display of an image to be displayed; a processing unit 204, connected to the receiving unit 202, for reading the target EDID of the display from the memory of the signal interface in response to the EDID request; and a sending unit 206, connected to the processing unit 204, configured to send the object EDID to the first interface connector, where the first interface connector sends the object EDID to the signal source device.
As an alternative embodiment, the receiving unit is configured to receive, from the first interface connector of the signal interfaces, an extended display screen identification data EDID request sent by the signal source device, where the EDID request is used to request EDID of a display of an image to be displayed. When the control chip receives the EDID request of the first interface connector of the signal interface, the receiving unit receives the EDID request to request the EDID of the display of the image to be displayed.
As an alternative embodiment, the processing unit is configured to read the target EDID of the display from the memory of the signal interface in response to the EDID request. In the target EDID reading the display, the target EDID may further include various types, for example: the display comprises a physical EDID of the display and a virtual EDID of the display, wherein the physical EDID is EDID read from the display, and the virtual EDID is EDID simulated according to the physical EDID. In reading the object EDID of the display from the memory of the signal interface, the memory may also include a plurality of storage units, for example, a first storage unit and a second storage unit, where the first storage unit stores the physical EDID and the second storage unit stores the virtual EDID. The processing unit may also include a first control module and a second control module. The first control module is used for reading the physical EDID from the first storage unit in a first control module and a second control module which are included in the processing unit; and the second control module is used for reading the virtual EDID from the second storage unit. Through setting under different situations, the EDID in the corresponding control module is read as the target EDID, and the target EDID is sent to the first interface connector, so that the target EDID is called.
As an alternative embodiment, the sending unit is configured to send the target EDID to the first interface connector, and the first interface connector is configured to send the target EDID to the signal source device. After the processing unit reads the target EDID of the display, the sending unit is used for sending the target EDID to the signal source equipment so as to use the target EDID for image display of the display screen.
As an optional embodiment, the control chip further includes: and a conversion unit. The conversion unit is used for converting the EDID request received by the receiving unit from a first signal type into an EDID request of a second signal type and sending the EDID request of the second signal type to the processing unit, wherein the first signal type is a signal type which cannot be identified by the processing unit, and the second signal type is a signal type which can be identified by the processing unit. The first signal type includes a plurality of signals, for example, a display interface DP signal; the second signal type includes a variety of signals, such as High Definition Multimedia Interface (HDMI) signals. Taking the first signal type as a display interface DP signal and the second signal type as a high definition multimedia interface HDMI signal as an example, the conversion unit may convert the DP signal that cannot be recognized by the processing unit into an HDMI signal that can be recognized by the processing unit to perform an operation of the EDID request for signal transmission.
As an alternative embodiment, a video processing apparatus includes any one of the signal interfaces.
Based on the above embodiments and alternative embodiments, an alternative implementation is provided.
In the related art, in order to solve the problem that the interface is difficult to realize the output of the original picture after plugging and unplugging the source, three solutions are provided: 1) the method can be realized by software configuration on a host of an X86 architecture (The X86 architecture), and The EDID of The output device is locked by using software to ensure The effect of maintaining The source picture; 2) fig. 3 is a schematic diagram of a video source processor architecture adopting an FPGA (Programmable logic device) mode in the related art, and as shown in fig. 3, when a video source is processed and output by an FPGA, layer storage is performed, so that an interface can output an original picture after plugging and unplugging the source; 3) fig. 4 is a schematic diagram of a video source processor architecture employing a proprietary chip in the related art, and as shown in fig. 4, a single dedicated video processing chip is used for conversion, DP input is realized, and DP output, EDID modification can be realized because the output signal is processed and regenerated in the process, independently of the previous input signal. However, the solution using the above solution has the following problems: 1) one of the software implementation is that manual software setting is needed, the operation process is relatively complex, the user embodiment is relatively poor, and a client needs to be reconfigured when the computer is started every time; 2) the FPGA processing mode has higher cost and longer development period; 3) the requirement on the chip is higher, and the products are fewer in the market and higher in price.
In view of this, the optional embodiment of the present invention provides a signal interface, and fig. 5 is a signal interface provided in the optional embodiment of the present invention, as shown in fig. 5, when the DP interface cannot directly modify the EDID, the EDID is indirectly modified, so that the effect of no change in the output picture after plugging in and unplugging the signal source device is achieved, which will be described in detail below.
Introduction of the device:
a first interface connector: an output image device, for example, a PC is connected through a connection line.
DP to HDMI chip: and converting the DP signal into an HDMI signal, namely converting the signal type which cannot be identified by the EEPROM into the signal type which can be identified by the EEPROM.
An EEPROM: the memory stores the external EDID and the virtual EDID, wherein the external EDID can be set for the virtual EDID and can be set to be synchronous with the external EDID, and the corresponding EDID is output according to requirements.
HDMI changes DP chip: and converting the HDMI signal into a DP signal. That is, when the signal is output, the HDMI signal may be converted into the DP signal to output the DP signal, in addition to the HDMI signal.
A second interface connector: and the display screen is connected through a connecting wire.
The implementation process comprises the following steps:
because the connection negotiation of the DP is the negotiation of a physical layer, the EDID of the DP cannot be modified, the DP signal can only be converted into the HDMI signal chip through the DP signal, the value of the EDID is modified in the HDMI signal, and the HDMI signal is converted into the DP signal to be output through the HDMI signal-to-DP signal chip.
In the above-mentioned process of modifying the EDID, a memory storing the external EDID and the virtual EDID, such as an EEPROM memory, may be used to modify the EDID, and the EDID may be selected according to the actual application scenario.
Through the above alternative embodiment, at least the following advantageous effects can be achieved:
1) ease of use of the product: the complexity of software setting on the display card is solved, and the product user experience is improved.
2) The cost performance is optimal: compared with an FPGA scheme, the device adopted by the optional implementation mode of the utility model has the advantages of lower material cost and development cost, shorter development period and capability of rapidly pushing out products.
3) And the EDID locking and unlocking switching of the interface is realized.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A signal interface, comprising: a first interface connector, a control chip and a memory, wherein,
the first interface connector is used for receiving an extended display screen identification data EDID request sent by signal source equipment and sending the EDID request to the control chip, wherein the EDID request is used for requesting EDID of a display of an image to be displayed;
the control chip is used for responding to the EDID request, reading the target EDID of the display from the memory and sending the read target EDID to the first interface connector;
the memory is used for storing the target EDID of the display;
the first interface connector is further configured to send the target EDID to the signal source device.
2. The signal interface of claim 1, further comprising: a second interface connector, wherein,
the first interface connector is further configured to receive a signal sent by the signal source device based on the EDID, and send the signal to the second interface connector;
the second interface connector is used for receiving the signal sent by the first interface connector and sending the signal to the display for displaying.
3. The signal interface of claim 1, further comprising: a first conversion chip, wherein,
the first conversion chip is used for converting the EDID request sent by the first signal type into an EDID request of a second signal type, wherein the first signal type is a signal type which cannot be identified by the control chip, and the second signal type is a signal type which can be identified by the control chip.
4. The signal interface of claim 3, wherein the first signal type is a display interface (DP) signal and the second signal type is a High Definition Multimedia Interface (HDMI) signal.
5. The signal interface of claim 1, wherein the target EDID comprises: the display comprises a physical EDID of the display and a virtual EDID of the display, wherein the physical EDID is EDID read from the display, and the virtual EDID is EDID simulated according to the physical EDID.
6. The signal interface of claim 5, wherein the memory comprises a first storage unit and a second storage unit, wherein the first storage unit is configured to store the physical EDID and the second storage unit is configured to store the virtual EDID.
7. The signal interface of any one of claims 1 to 6, wherein the memory comprises: the EEPROM is electrically erasable and programmable.
8. A control chip, comprising: a receiving unit, a processing unit and a transmitting unit, wherein,
the receiving unit is used for receiving an extended display screen identification data EDID request sent by signal source equipment from a first interface connector of the signal interface, wherein the EDID request is used for requesting EDID of a display of an image to be displayed;
the processing unit is used for responding to the EDID request and reading the target EDID of the display from the memory of the signal interface;
the sending unit is configured to send the target EDID to the first interface connector, and is configured to send the target EDID to the signal source device by the first interface connector.
9. The control chip of claim 8, wherein the processing unit includes a first control module and a second control module, and wherein the target EDID includes: a physical EDID of the display and a virtual EDID of the display, wherein the physical EDID is an EDID read from the display, the virtual EDID is an EDID simulated according to the physical EDID, the memory includes a first storage unit storing the physical EDID and a second storage unit storing the virtual EDID, and wherein,
the first control module is used for reading the physical EDID from the first storage unit;
the second control module is used for reading the virtual EDID from the second storage unit.
10. A video processing apparatus, comprising: the signal interface of any one of claims 1 to 7.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115550590A (en) * | 2022-09-28 | 2022-12-30 | 珠海海奇半导体有限公司 | DP conversion equipment, display system and DP conversion display method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115550590A (en) * | 2022-09-28 | 2022-12-30 | 珠海海奇半导体有限公司 | DP conversion equipment, display system and DP conversion display method |
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