CN215871346U - Signal filtering system based on LabVIEW platform - Google Patents
Signal filtering system based on LabVIEW platform Download PDFInfo
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- CN215871346U CN215871346U CN202120392430.8U CN202120392430U CN215871346U CN 215871346 U CN215871346 U CN 215871346U CN 202120392430 U CN202120392430 U CN 202120392430U CN 215871346 U CN215871346 U CN 215871346U
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Abstract
A signal filtering system based on a LabVIEW platform comprises a sensor, wherein a signal output end of the sensor is connected with a signal input end of an oscilloscope through a hardware circuit, and a signal output end of the oscilloscope is connected with a signal input end of an upper computer; the analog signal sent by the sensor is output to a hardware circuit, the analog signal is processed by the hardware circuit and then is output by an AD sampling module in an oscilloscope, the oscilloscope can detect the output signal parameter of the hardware circuit, then the data of the AD module is sent to an upper computer through RS232, LabVIEW reads the sent data by using VISA, and the data is filtered again, so that a better filtering effect can be achieved; the method combining software and hardware can obviously improve the signal-to-noise ratio and improve the precision of the sensor.
Description
Technical Field
The utility model relates to a signal processing device, in particular to a signal filtering system based on a LabVIEW platform.
Background
The LabVIEW platform is a development environment of graphical programming language and is widely applied to the fields of equipment communication, signal processing and the like.
The analog signal of the current sensor generally needs to be pre-processed before being recognized and read by the control terminal. Pre-processing includes signal filtering, where either hardware filtering or software filtering alone does not achieve the desired effect.
Disclosure of Invention
In order to overcome the defects in the prior art, the utility model aims to provide a signal filtering system based on a LabVIEW platform, wherein after signal hardware is subjected to filtering gain, collected analog signals are filtered again by using software of an upper computer, a better filtering effect can be achieved, the signal-to-noise ratio is obviously improved by a software and hardware combined method, and the precision of a sensor is improved to a certain extent.
In order to achieve the purpose, the utility model adopts the following technical scheme:
a signal filtering system based on a LabVIEW platform comprises a sensor 1, wherein a signal output end of the sensor 1 is connected with a signal input end of an oscilloscope 3 through a hardware circuit 2, and a signal output end of the oscilloscope 3 is connected with a signal input end of an upper computer 4.
The sensor 1 is a voltage sensor.
The hardware circuit 2 is a multi-stage amplification filter circuit; the multistage amplification filter circuit comprises an input buffer circuit, a preposed first-stage amplification circuit, a second-stage amplification circuit and a power frequency trap circuit, and amplifies a small voltage signal input by the sensor 1 to 0-5V level, so that the small voltage signal can be processed by a subsequent system.
The input buffer circuit is an RC low-pass filter circuit, signals are input from an IN port and are connected with one end of a first capacitor C1 through a first resistor R1, the other end of the first capacitor C1 is grounded, and the filtered signals are sent to a preposed first-stage amplifying circuit through an OUT end.
The pre-primary amplifying circuit is a differential amplifying circuit and comprises a first operational amplifier U1, a second operational amplifier U2 and a high-precision amplifier U3; the output signal of the sensor is connected to a preposed primary amplifying circuit through IN, and is output to a secondary amplifying circuit through a 2 port of a high-precision amplifier U3 after being amplified; wherein the 1 terminal of the first operational amplifier U1 is connected with the 1 terminal of the second operational amplifier U2 for input signal, one terminal of the third resistor R3 is grounded, the other terminal is connected with the input terminals of the fourth resistor R4 and the fifth resistor R5 respectively, the output terminal of the fourth resistor R4 is connected with the 0 terminal of the first operational amplifier U1, the output terminal of the fifth resistor R5 is connected with the 0 terminal of the second operational amplifier U2, the sixth resistor R6 leads the output part of the first operational amplifier U1 to the 0 terminal of the first operational amplifier U1, the eighth resistor R8 leads the output part of the second operational amplifier U2 to the 0 terminal of the second operational amplifier U2 to form negative feedback, the output terminal of the first operational amplifier U1 is output to the 0 terminal of the high precision amplifier U3 through the seventh resistor R7, the output of the second operational amplifier U2 is output to the 1 terminal of the high precision amplifier U3 through the second resistor R2, the output of the high precision amplifier U3 is amplified, and then output to the next stage circuit U3, meanwhile, the ninth resistor R9 leads the output part 2 end of the high-precision amplifier U3 to the input end 0 of the high-precision amplifier U3 to form negative feedback to the high-precision amplifier U3, and one end of the tenth resistor R10 is connected with the ground, and the other end is connected with the port 1 of the high-precision amplifier U3.
The second-stage amplifying circuit is an inverting amplifying circuit and comprises an adjustable potentiometer RW1 and a third operational amplifier U6; the output end of the preposed primary amplifying circuit is connected with a port 0 of a third operational amplifier U6, a port 1 is grounded through a twentieth resistor R20, and an output port 2 is connected with a potentiometer RW1 through a nineteenth resistor R19 and serves as a negative feedback input end.
The power frequency notch circuit comprises a band-pass circuit and an adder, wherein the band-pass circuit comprises an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a second capacitor C2, a third capacitor C3 and a fourth operational amplifier U4, and the adder comprises a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18 and a fifth operational amplifier U5; wherein, the output end of the second-stage amplifying circuit is connected in parallel with the input ends of a fifteenth resistor R15 and an eleventh resistor R11, the output end of the fifteenth resistor R15 is connected with the 0 end of a fifth operational amplifier U5, the output end of the eleventh resistor R11 is respectively connected in parallel with the input ends of a second capacitor C2, a third capacitor C3 and a thirteenth resistor R13, the output end of the thirteenth resistor R13 is grounded, a second capacitor C2, the third capacitor C3 is also connected in parallel with the twelfth resistor R12, the output end of the third capacitor C3 is connected to the 0 port of the fourth operational amplifier U4, the 1 port of the fourth operational amplifier U4 is grounded, the signal is processed and then sent to the 0 port of the fifth operational amplifier U5 through the 2 port of the fourth operational amplifier U4, the 1 port of the fifth operational amplifier U5 is connected to the output of the 2 port through the seventeenth resistor R17 to form negative feedback, and in addition, the 1 port of the fifth operational amplifier U5 is also connected to the sixteenth resistor R16 and grounded; and finally, the 2 port of the fifth operational amplifier U5 is output to the next link through an eighteenth resistor R18 and is connected with a probe of an oscilloscope.
And after the oscilloscope 3 performs data sampling, the AD module transmits the data to the upper computer 4 through the RS 232.
The upper computer 4 reads data through a LabVIEW platform by using a VISA module and performs software filtering on the data; the software filtering modes include Butterworth filtering, Chebyshev filtering and adaptive filtering.
The signals of the first to fifth operational amplifiers are LF353, and the model of the high-precision amplifier U3 is OP 07.
The utility model has the beneficial effects that:
after the hardware filtering gain of the signal is achieved through the multistage amplification filtering circuit, the collected analog signal is filtered again through the LabVIEW platform by the upper computer 4 and VISA module software, and a good filtering effect can be achieved; the method combining software and hardware can obviously improve the signal-to-noise ratio and improve the precision of the sensor.
Drawings
Fig. 1 is an overall configuration diagram of the system of the present invention.
Fig. 2 is a system configuration diagram of the present invention.
Fig. 3 is a functional block diagram of the operation of the system of the present invention.
Fig. 4 is a functional block diagram of the hardware circuit of the present invention.
Fig. 5 is a diagram of an input buffer circuit of the present invention.
Fig. 6 is a circuit diagram of a pre-stage amplifier of the present invention.
Fig. 7 is a two-stage amplification circuit diagram of the present invention.
FIG. 8 is a diagram of a power frequency notch circuit of the present invention.
Figure 9 is a schematic of the amplitude frequency curve of the bandpass circuit of the present invention.
FIG. 10 is a schematic of the amplitude frequency curve of the notch circuit of the present invention.
In the figure: 1. a sensor; 2. a hardware circuit; 3. an oscilloscope; 4. and (4) an upper computer.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
Referring to fig. 1 to 4, the signal filtering system based on the LabVIEW platform comprises a sensor 1, wherein a signal output end of the sensor 1 is connected with a signal input end of an oscilloscope 3 through a hardware circuit 2, and a signal output end of the oscilloscope 3 is connected with a signal input end of an upper computer 4.
The sensor 1 is a voltage sensor.
The hardware circuit 2 is a multi-stage amplification filter circuit; the multistage amplification filter circuit comprises an input buffer circuit, a preposed first-stage amplification circuit, a second-stage amplification circuit and a power frequency trap circuit, and amplifies a small voltage signal input by the sensor 1 to 0-5V level, so that the small voltage signal can be processed by a subsequent system.
Referring to fig. 5, the input buffer circuit is an RC low-pass filter circuit, a signal is input from an IN port, and is connected to one end of a first capacitor C1 through a first resistor R1, the other end of the first capacitor C1 is grounded, and the filtered signal is sent to a pre-primary amplifier circuit through an OUT port, so as to filter a high-frequency interference component of the input signal; the first resistor R1 is 10K Ω, the first capacitor C1 is 51pF, and the RC cutoff frequency fc is 312 Khz.
Referring to fig. 6, the pre-stage amplifying circuit is a differential amplifying circuit, and the gain is 300; the circuit comprises a first operational amplifier U1, a second operational amplifier U2 and a high-precision amplifier U3, wherein resistors are unified into chip resistors and are packaged 0805; the output signal of the sensor is connected to a preposed primary amplifying circuit through IN, and is output to a secondary amplifying circuit through a 2 port of a high-precision amplifier U3 after being amplified; wherein the 1 terminal of the first operational amplifier U1 is connected with the 1 terminal of the second operational amplifier U2 for input signal, one terminal of the third resistor R3 is grounded, the other terminal is connected with the input terminals of the fourth resistor R4 and the fifth resistor R5 respectively, the output terminal of the fourth resistor R4 is connected with the 0 terminal of the first operational amplifier U1, the output terminal of the fifth resistor R5 is connected with the 0 terminal of the second operational amplifier U2, the sixth resistor R6 leads the output part of the first operational amplifier U1 to the 0 terminal of the first operational amplifier U1, the eighth resistor R8 leads the output part of the second operational amplifier U2 to the 0 terminal of the second operational amplifier U2 to form negative feedback, the output terminal of the first operational amplifier U1 is output to the 0 terminal of the high precision amplifier U3 through the seventh resistor R7, the output of the second operational amplifier U2 is output to the 1 terminal of the high precision amplifier U3 through the second resistor R2, the output of the high precision amplifier U3 is amplified, and then output to the next stage circuit U3, meanwhile, the ninth resistor R9 leads the output part 2 end of the high-precision amplifier U3 to the input end 0 of the high-precision amplifier U3 to form negative feedback to the high-precision amplifier U3, one end of the tenth resistor R10 is connected with the ground, and the other end of the tenth resistor R10 is connected with the port 1 of the high-precision amplifier U3; wherein: the third resistor R3 is 2K, the fourth resistor R4 is 5K, the fifth resistor R5 is 5K, the sixth resistor R6 is eight resistor R8 is nine resistor R9 is 51K, the seventh resistor R7 is 5.1K, the second resistor R2 is 5.1K, and the tenth resistor R10 is 5.3K.
Referring to fig. 7, the second-stage amplifying circuit is an inverting amplifying circuit, the gain of the second-stage amplifying circuit is adjustable within a range of 2 to 15, and the second-stage amplifying circuit comprises a potentiometer RW1 and a third operational amplifier U6, wherein the resistor of the potentiometer RW1 is adjustable within a range of 0 to 50K Ω; the output end of the preposed primary amplifying circuit is connected with a port 0 of a third operational amplifier U6, a port 1 is grounded through a twentieth resistor R20, and is connected with an output port 2 of a potentiometer RW1 through a nineteenth resistor R19 to serve as a negative feedback input end; wherein: the twentieth resistor R20 is 5K, and the nineteenth resistor R19 is 10K.
Referring to fig. 8, the power frequency notch circuit includes a band-pass circuit and an adder, the band-pass circuit includes an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a second capacitor C2, a third capacitor C3 and a fourth operational amplifier U4, and the adder includes a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18 and a fifth operational amplifier U5; wherein, the output end of the second-stage amplifying circuit is connected in parallel with the input ends of a fifteenth resistor R15 and an eleventh resistor R11, the output end of the fifteenth resistor R15 is connected with the 0 end of a fifth operational amplifier U5, the output end of the eleventh resistor R11 is respectively connected in parallel with the input ends of a second capacitor C2, a third capacitor C3 and a thirteenth resistor R13, the output end of the thirteenth resistor R13 is grounded, a second capacitor C2, the third capacitor C3 is also connected in parallel with the twelfth resistor R12, the output end of the third capacitor C3 is connected to the 0 port of the fourth operational amplifier U4, the 1 port of the fourth operational amplifier U4 is grounded, the signal is processed and then sent to the 0 port of the fifth operational amplifier U5 through the 2 port of the fourth operational amplifier U4, the 1 port of the fifth operational amplifier U5 is connected to the output of the 2 port through the seventeenth resistor R17 to form negative feedback, and in addition, the 1 port of the fifth operational amplifier U5 is also connected to the sixteenth resistor R16 and grounded; finally, the 2 port of the fifth operational amplifier U5 is output to the next link through an eighteenth resistor R18 and is connected with a probe of an oscilloscope; wherein: the second capacitor C2 is 330nF, the eleventh resistor R11 is 50K, the thirteenth resistor R13 is 270, the twelfth resistor R12 is 270K, the fourteenth resistor R14 is fifteenth resistor R15 is sixteenth resistor R16 is seventeenth resistor R17 is eighteenth resistor R18 is 10K.
And after the oscilloscope 3 performs data sampling, the AD module transmits the data to the upper computer 4 through the RS 232.
And the upper computer 4 reads data by using a VISA module through a LabVIEW platform and performs software filtering on the data.
The software filtering mode comprises Butterworth filtering, Chebyshev filtering and self-adaptive filtering; wherein, LabVIEW is provided with Butterworth and Chebyshev filters, and the adaptive filtering can be realized by matlab scripts.
The signals of the first to fifth operational amplifiers are LF353, and the model of the high-precision amplifier U3 is OP 07.
Verifying the design of the whole circuit, firstly verifying whether the gain of the simulation software can be adjusted to 1000-3000 by selecting Multism14.0 through simulation software, setting an input signal to be 0.1mV, and measuring the output amplitude of each link; through measurement, the finally output voltage can meet the requirements of 100-300mV adjustability and gain requirements.
The filtering and notching effects were verified and a cutoff frequency of 372HZ was measured.
The effect of the trap is verified, and whether the passband of the band-pass circuit is narrow or not, and the center frequency and the cut-off frequency are observed. Referring to fig. 9, it can be seen that the center frequency of the amplitude-frequency curve of the band-pass circuit is 50HZ, the cut-off frequencies are 48HZ and 52HZ, and the bandwidth is 4HZ, which meets the requirement.
Testing the performance of the overall notch circuit, the amplitude-frequency curve is shown in fig. 10, and it can be seen that the ordinate at 50hz on the horizontal axis is reduced, which proves that the 50hz component is reduced, and thus the noise of 50hz can be filtered out.
The working principle of the utility model is as follows:
the amplitude of an output signal of the sensor 1 is 0-4mV, an analog signal sent by the sensor 1 is output to the hardware circuit 2, the output of the analog signal is collected by an AD sampling module in the oscilloscope 3 after being processed by the hardware circuit 2, meanwhile, the oscilloscope 3 can detect the output signal parameter of the hardware circuit 2, then the data of the AD module is sent to the upper computer 4 through RS232, LabVIEW reads the sent data by using VISA, and the data is filtered again, and the final signal can realize the function of storage and playback.
Claims (6)
1. A signal filtering system based on a LabVIEW platform comprises a sensor (1), and is characterized in that: the signal output end of the sensor (1) is connected with the signal input end of the oscilloscope (3) through the hardware circuit (2), and the signal output end of the oscilloscope (3) is connected with the signal input end of the upper computer (4); the sensor (1) is a voltage sensor; the hardware circuit is a multi-stage amplification filter circuit; the multistage amplification filter circuit comprises an input buffer circuit, a preposed first-stage amplification circuit, a second-stage amplification circuit and a power frequency trap circuit, and amplifies a small voltage signal input by the sensor (1) to 0-5V level, so that the small voltage signal can be processed by a subsequent system.
2. The LabVIEW platform based signal filtering system of claim 1, wherein: the input buffer circuit is an RC low-pass filter circuit, signals are input from an IN port and are connected with one end of a first capacitor (C1) through a first resistor (R1), the other end of the first capacitor (C1) is grounded, and the filtered signals are sent to a preposed first-stage amplifying circuit through an OUT end.
3. The LabVIEW platform-based signal filtering system as claimed in claim 1 or 2, wherein: the preposed primary amplifying circuit is a differential amplifying circuit; comprises a first operational amplifier (U1), a second operational amplifier (U2), a high-precision amplifier (U3); the output signal of the sensor is connected to a preposed primary amplifying circuit through IN, and is output to a secondary amplifying circuit through a 2-port of a high-precision amplifier (U3) after being amplified; wherein the 1 end of the first operational amplifier (U1) is connected with the 1 end of the second operational amplifier (U2) to input signals, one end of the third resistor (R3) is grounded, the other end is respectively connected with the input ends of the fourth resistor (R4) and the fifth resistor (R5) in series, the output end of the fourth resistor (R4) is connected with the 0 end of the first operational amplifier (U1), the output end of the fifth resistor (R5) is connected with the 0 end of the second operational amplifier (U2), the sixth resistor (R6) leads the output part of the first operational amplifier (U1) to the input end 0 of the first operational amplifier (U1), the eighth resistor (R8) leads the output part of the second operational amplifier (U2) to the input end 0 of the second operational amplifier (U2) to form negative feedback, the output end of the first operational amplifier (U1) is output to the 0 end of the high-precision amplifier (U3) through the seventh resistor R7, the output end of the second operational amplifier (U2) is output to the output end of the second operational amplifier (U3) to the high-precision amplifier (U3) to output end of the high-precision amplifier (U3), negative feedback, the high-precision amplifier (U2) The terminal is amplified and then output to a next-stage circuit from a 2 port of the high-precision amplifier (U3), meanwhile, a ninth resistor (R9) leads the 2 end of the output part of the high-precision amplifier (U3) to the input terminal 0 of the high-precision amplifier (U3) to form negative feedback on the high-precision amplifier (U3), one end of a tenth resistor (R10) is connected with the ground, and the other end of the tenth resistor is connected with a 1 port of the high-precision amplifier (U3);
the second-stage amplifying circuit is an inverting amplifying circuit and comprises an adjustable potentiometer (RW 1) and a third operational amplifier (U6); the output end of the preposed primary amplifying circuit is connected with a port 0 of a third operational amplifier (U6), a port 1 is grounded through a twentieth resistor (R20), and is connected with a potentiometer (RW 1) through a nineteenth resistor (R19) to output a port 2 to serve as a negative feedback input end;
the power frequency notch circuit comprises a band-pass circuit and an adder, wherein the band-pass circuit comprises an eleventh resistor (R11), a twelfth resistor (R12), a thirteenth resistor (R13), a second capacitor (C2), a third capacitor (C3) and a fourth operational amplifier (U4), and the adder comprises a fourteenth resistor (R14), a fifteenth resistor (R15), a sixteenth resistor (R16), a seventeenth resistor (R17), an eighteenth resistor (R18) and a fifth operational amplifier (U5); wherein, the output end of the second-stage amplifying circuit is connected with the input ends of a fifteenth resistor (R15) and an eleventh resistor (R11) in parallel, the output end of the fifteenth resistor (R15) is connected with the 0 end of a fifth operational amplifier (U5), the output end of the eleventh resistor (R11) is respectively connected with the input ends of a second capacitor (C2), a third capacitor (C3) and a thirteenth resistor (R13) in parallel, the output end of the thirteenth resistor (R13) is grounded, the second capacitor (C2) and the third capacitor (C3) are also connected with a twelfth resistor (R12) in parallel, the output end of the third capacitor (C3) is connected with the 0 port of a fourth operational amplifier (U4), the 1 port of the fourth operational amplifier (U4) is grounded, after being processed, the signal is sent to the 0 port of the fifth operational amplifier (U5) through the 2 port of the fourth operational amplifier (U4), the 1 port of the fifth operational amplifier (U5) is connected with the output of the seventeenth resistor (R17), negative feedback is formed, and in addition, the port 1 of the fifth operational amplifier (U5) is also connected with a sixteenth resistor (R16) to be grounded; and finally, the 2 port of the fifth operational amplifier (U5) is output to the next link through an eighteenth resistor (R18) and is connected with a probe of the oscilloscope (3).
4. The LabVIEW platform based signal filtering system of claim 1, wherein: after the oscilloscope (3) samples data, the AD module transmits the data to the upper computer (4) through the RS 232.
5. The LabVIEW platform based signal filtering system of claim 1, wherein: the upper computer (4) reads data through a LabVIEW platform by using a VISA module and performs software filtering on the data; the software filtering modes include Butterworth filtering, Chebyshev filtering and adaptive filtering.
6. The LabVIEW platform based signal filtering system of claim 3, wherein: the signals of the first to fifth operational amplifiers are LF353, and the model of a high-precision amplifier (U3) is OP 07.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120392430.8U CN215871346U (en) | 2021-02-22 | 2021-02-22 | Signal filtering system based on LabVIEW platform |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120392430.8U CN215871346U (en) | 2021-02-22 | 2021-02-22 | Signal filtering system based on LabVIEW platform |
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| Publication Number | Publication Date |
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| CN215871346U true CN215871346U (en) | 2022-02-18 |
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| CN202120392430.8U Active CN215871346U (en) | 2021-02-22 | 2021-02-22 | Signal filtering system based on LabVIEW platform |
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