CN215818195U - 1.8G private network signal quality detection terminal - Google Patents

Abstract

The utility model discloses a 1.8G private network signal quality detection terminal, which comprises a packaging shell consisting of a bottom shell and an upper cover, wherein a circuit board is installed in the packaging shell through a fixing column, the circuit board comprises a main control board and an LTE communication board, and the main control board comprises: the MCU processor is connected with the power supply module, the FLASH memory, the watchdog, the USB HUB circuit, the DDR2 memory, the Ethernet interface and the RS485 interface, the USB HUB circuit is connected with the USB interface, the power supply module is connected with the 9-36V DC input port through the power supply protection interface protection circuit, and the Ethernet interface, the RS485 interface and the USB interface are connected with the data interface protection circuit; the LTE communication board includes: 1.8G public specific body communication module EM300, 1.8G public specific body communication module EM300 connects in step-down conversion module, and step-down conversion module connects in minipCIE interface, and minipCIE interface connection is in the power module and the USB HUB circuit of main control board. The signal quality of each service system network coverage of the electric power wireless communication private network can be monitored in real time, and the monitoring index parameters are uploaded to a network management platform.

Description

1.8G private network signal quality detection terminal

Technical Field

The utility model relates to the technical field of communication, in particular to a 1.8G private network signal quality detection terminal.

Background

The utility model aims to meet the requirements and provides the network signal quality detection equipment for the LTE-1.8G wireless private network communication system, which has high working stability and reliability and a simple structure.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a 1.8G private network signal quality detection terminal which can monitor the signal quality covered by each service system of an electric power wireless communication private network in real time and upload monitoring index parameters to a network management platform.

In order to solve the above technical problem, an embodiment of the present invention provides a 1.8G private network signal quality detection terminal, which includes a package housing formed by a bottom case and an upper cover, a circuit board is installed in the package housing through a fixing column, the circuit board includes a main control board and an LTE communication board, and the main control board includes: the MCU processor is connected with the power module, the FLASH memory, the watchdog, the USB HUB circuit, the DDR2 memory, the Ethernet interface and the RS485 interface, the USB HUB circuit is connected with the USB interface, the power module is connected with the 9-36V DC input port through the power protection interface protection circuit, and the Ethernet interface, the RS485 interface and the USB interface are connected with the data interface protection circuit;

the LTE communication board includes: 1.8G public specific body communication module EM300, 1.8G public specific body communication module EM300 is connected in step-down conversion module, step-down conversion module connects in miniPCE interface, and miniPCE interface connection is in the power module and the USB HUB circuit of main control board.

In the 1.8G private network signal quality detection terminal provided by the utility model, the main control board and the LTE communication board are of a split structure.

In the 1.8G private network signal quality detection terminal provided by the utility model, the power input control circuit of the LTE communication board comprises a triode N3, the B electrode of the triode N3 is connected with a resistor R47, the other end of the resistor R47 is connected with the 18 pin of a control chip U3, the E electrode of the triode N3 is grounded, the C electrode of the triode N3 is connected with a resistor R48, the other end of the resistor R48 is connected with a P-channel enhanced field effect transistor PMOS1, a resistor R74 is connected between the G electrode and the S electrode of the P-channel enhanced field effect transistor PMOS1, the S electrode of the P-channel enhanced field effect transistor PMOS1 is connected with a VDD5.0 power supply, the VDD5.0 power supply is connected with a capacitor C69 and an electrolytic capacitor E3 which are connected in parallel, the other ends of the electrolytic capacitor E3 and the capacitor C69 are grounded, the D electrode of the P-channel enhanced field effect transistor PMOS1 is connected with a diode D1, a diode D1 is connected with a diode D1 and a MINCIE 300 communication module in the circuit of the MINCIE plug circuit, and the diode D1 is also connected with an electrolytic capacitor E5 and a capacitor C70 and a C9 and a C70 which are connected in parallel, The other ends of the electrolytic capacitor E6, the electrolytic capacitor E5, the capacitor C70 and the electrolytic capacitor E6 are grounded.

Furthermore, a communication module power supply voltage reduction circuit is arranged between the power module and the miniPPE interface.

The utility model has the following beneficial effects:

1. the signal quality of each service system network coverage of the electric power wireless communication private network can be monitored in real time, and the monitoring index parameters are uploaded to a network management platform.

2. The terminal has high circuit stability and a simple structure.

3. The whole product is more economic in cost while ensuring reliability.

Drawings

Fig. 1 is a three-dimensional structure diagram of a 1.8G private network signal quality detection terminal.

Fig. 2 is an exploded structure diagram of a 1.8G private network signal quality detection terminal.

Fig. 3 is a schematic diagram of a 1.8G private network signal quality detection terminal.

Fig. 4 is a schematic circuit diagram of an MCU processor in the 1.8G private network signal quality detection terminal.

FIG. 5 is a circuit diagram of MCU processor communication port level configuration, in which, (a) is a circuit diagram of 17-pin external parameter setting of the control chip U3; (b) setting a circuit diagram for the 25-pin external parameters of the control chip U3; (c) a circuit diagram is set for the 24-pin external parameters of the control chip U3; (d) setting a circuit diagram for the 135 pin external parameters of the control chip U3; (e) setting a circuit diagram for external parameters of the 147 pin of the control chip U3; and (f) a circuit diagram for setting 17-pin external parameters of the control chip U3.

Fig. 6 is a schematic diagram of a power supply voltage-reducing circuit of a communication module of an LTE communication board.

Fig. 7 is an application circuit diagram of minicie of the connector of the motherboard connecting the communication module.

Fig. 8 is a circuit diagram of a SIM card socket in an LTE communication board, where (a) is the circuit diagram of the SIM card socket, and (b) is the circuit diagram of a transient suppression diode externally connected to pins 3, 5, and 6 in the circuit of the SIM card socket.

Fig. 9 is a circuit diagram of a PCIE pad in an LTE communication board.

Fig. 10 is a circuit diagram of a PCIE switch board, in which, (a) is a circuit diagram of a MiniPCI slot; (b) is an EM300-1 circuit diagram; (c) is a filter circuit diagram of VDD3.3V power supply in PCIE conversion board circuit.

FIG. 11 is a schematic diagram of a USB HUB circuit.

FIG. 12 is a schematic diagram of a USB interface circuit in the USB HUB circuit.

FIG. 13 is a schematic diagram of a USB interface static protection circuit in the USB HUB circuit.

Fig. 14 is a schematic diagram of a watchdog circuit.

Fig. 15 is a power supply circuit diagram of a control CPU and the like in the watchdog circuit.

Fig. 16 is a circuit diagram for setting external parameters of each pin in the MCU processor, in which, (a) is a circuit diagram for setting external parameters of 21 pins in the MCU processor; (b) and setting a circuit diagram for the 90-pin external DDR parameter.

FIG. 17 is a schematic diagram of a FLASH memory circuit.

Fig. 18 is a schematic circuit diagram of a DDR2 chip.

Fig. 19 is a schematic diagram of a 485 transceiver circuit.

Fig. 20 is a schematic diagram of a J3 connector circuit in the 485 transceiver circuit.

Fig. 21 is a schematic diagram of an external 232 serial port circuit.

Fig. 22 is a schematic circuit diagram of a connector J1 in an external 232 serial port circuit.

Fig. 23 is a schematic diagram of RJ45 and network transformer circuits.

Fig. 24 is a schematic diagram of an external circuit of the RJ45 and the control chip U12 of the network transformer circuit, which includes pins 13, 14, 16, 17, 19, 20, 22 and 23.

Figure 25 is a WPS indicator light circuit schematic.

FIG. 26 is a schematic diagram of a power indicator circuit.

FIG. 27 is a voltage filter circuit for different voltages in an MCU processor circuit, wherein (a) the filter circuit supplies 3V3 voltage; (b) a filter circuit for supplying 3V3 voltage; (c) a filter circuit for supplying 1V2 voltage; (d) a filter circuit for supplying 1V8 voltage.

Fig. 28 is a schematic diagram of a first power supply 5V output circuit of the power supply module.

Fig. 29 is a schematic diagram of an output circuit of the second power supply 3V3 of the power supply module.

Fig. 30 is a circuit diagram of a power input surge protection and lightning protection circuit in a power module.

Fig. 31 is a circuit diagram of the capacitive ac coupling between the housing ground and the negative terminal of the circuit in the power module.

FIG. 32 is a circuit diagram of a power input receptacle interface in a power module.

Detailed Description

In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the utility model easy to understand, the utility model is further described with the specific embodiments.

The embodiment of the utility model provides a 1.8G private network signal quality detection terminal, which is shown in a figure 1-3 and comprises a packaging shell 3 consisting of a bottom shell 1 and an upper cover 2, wherein a circuit board 4 is installed in the packaging shell through a fixing column, and the circuit board 4 comprises an MCU processor, a power supply module, an LTE communication module (carried on an LTE communication board), a USB interface, a watchdog and a USB interface.

Referring to FIG. 4, the MCU processor comprises a control chip U3 (e.g. MT7628AH-157PIN), PINs 1, 2, 7, 10, 13, 63, 115, 120 and 121 of the control chip U3 are grounded, PINs 3-6, 9, 11-12, 16, 37, 40, 42-46, 49-52, 126, 127 and 128 of the control chip U3 are grounded, the pins 130, 132, 133, 144, 153 and 156 are empty pins, the pins 8, 14, 15, 38, 41, 53, 60, 117, 123, 124, 134, 146, 149, 150 and 154 of the control chip U3 are connected to the power supply of 3V3, the pin 17 of the control chip U3 is connected to the resistor R46, the other end of the resistor R46 is connected to the ground (see FIG. 5), and the pin 18 of the control chip U3 is connected to the power input control circuit of the LTE communication board. The pin 19 of the control chip U3 is connected with the USB HUB circuit. The 20-pin of the control chip U3 is connected to a watchdog circuit. The pin 21 of the control chip U3 is connected with the power supply 3V3 through a resistor R14, the pin 21 switch SW2 of the control chip U3, the pins 22 and 23 of the control chip U3 are respectively connected with the power supply 1V2 and the power supply 3V3, the pin 24 of the control chip U3 is grounded through a resistor R43 (see figure 5c), the pins 25 to 28 of the control chip U3 are connected with the FLASH memory, the pin 25 of the control chip U3 is connected with the power supply 3V3 through a resistor R40 (see figure 5b), and the pin 29 of the control chip U3 is connected with a 485 transceiver circuit. 30-31 pins of a control chip U3 are connected with an external 232 serial port circuit, 32 pins of a control chip U3 are connected with a power supply 3V3, 33-36 pins of a control chip U3 are connected with an RJ45 and a network transformer circuit, 39 pins of a control chip U3 are grounded through a resistor R61, 47-48 pins of a control chip U3 are connected with a 485 transceiver circuit, 47-48 pins are respectively connected with a resistor R15 and a resistor R16, 54-57 pins of the control chip U3 are connected with an RJ45 and a network transformer circuit, 58 pins and 145 pins of the control chip U3 are connected with a power supply 1V2, 59 pins of the control chip U3 are grounded through a resistor R62, 61-62 pins of the control chip U3 are connected with a USB HUB circuit, 61 pins and 62 pins are respectively connected with a resistor R20 and a resistor R21, 64 pins-78 pins, 80-88 pins, 92-97 pins, 99 pins-103 pins and 105-114 pins 2 of a control chip U3 are connected with a 2, the 79 pin of the control chip U3 is connected with a power supply 1V8, the 89 pin, the 91 pin and the 131 pin of the control chip U3 are connected with a power supply 1V2, the 90 pin and the 104 pin of the control chip U3 are connected with a reference voltage VREF circuit of a DDR2, the 98 pin, the 116 pin and the 125 pin of the control chip U3 are connected with a power supply 1V 3, the 118 pin and the 119 pin of the control chip U3 are connected with an inductor L3, the inductor L3 is connected with a capacitor C3 and a capacitor C3 which are connected in parallel, the capacitor C3 and the capacitor C3 are connected in parallel, one end of the capacitor C3 and the other end of the capacitor C3 are connected with the power supply 1V 3 in parallel, the 122 pin of the control chip U3 is connected with a capacitor C3 and the capacitor C3 which are connected in parallel, the 129 pin of the control chip U3 is connected with a gate circuit, the 135 pin of the control chip U3 is connected with a ground through an electronic R3 (figure 5d), the pin of the control chip U3 is connected with a pin of the power supply 3R 3 and one end of the resistor R3 and the resistor R3 of the power supply 72 of the control chip U3 is connected with a lamp 72 and one end of the power supply 72 and the resistor R3 of the power supply 72 and the power supply 72 of the resistor R3 of the power supply 72 of the control chip U3, The reset switch S1 with one end grounded, the 139-143 pin of the control chip U3 connected with RJ45 and the network transformer circuit, the 147-148 pin of the control chip U3 connected with 485 transceiver circuit, the 147 pin also connected with ground through the pull-down resistor R41, the 151 pin of the control chip U3 connected with the capacitor C100 with the other end grounded and the external crystal oscillator XTAL1, the capacitor C100 with the other end grounded and the external crystal oscillator XTAL1 connected with ground, and the 152 pin of the control chip U3 connected with the ground ends of the capacitor C100 and the external crystal oscillator XTAL 1.

Referring to fig. 3, in this embodiment, the power interface and the USB interface of the 1.8G public entity communication module EM300 are connected to the minippice interface, the power output end of the communication module of the main control board and the USB HUB circuit are connected to the minippie interface, and here the 1.8G public entity communication module EM300 may adopt the ehte public entity communication module EM300-118 of huashi corporation.

And a communication module power supply voltage reduction circuit is arranged between the power module and the miniCIE interface. The communication module power supply voltage reduction circuit is a voltage reduction conversion (module) in fig. 3, fig. 6 shows a schematic diagram of the communication module power supply voltage reduction circuit of the LTE communication board, which includes a triode N3, a B pole of the triode N3 is connected with a resistor R47, the other end of the resistor R47 is connected with a pin 18 of a control chip U3, an E pole of the triode N3 is grounded, a C pole of the triode N3 is connected with a resistor R48, the other end of the resistor R48 is connected with a P-channel enhancement type field effect transistor PMOS1, a resistor R74 is connected between the G pole and the S pole of the P-channel enhancement type field effect transistor PMOS1, the S pole of the P-channel enhancement type field effect transistor PMOS1 is connected with a VDD5.0 power supply, the VDD5.0 power supply is connected with a capacitor C69 and an electrolytic capacitor E3 which are connected in parallel, the other ends of the electrolytic capacitor E3 and the capacitor C69 are grounded, a D pole of the P-channel enhancement type field effect transistor PMOS1 is connected with a diode D1 (the purpose of this diode D1 is as a voltage reduction diode D1, the 5V voltage input by the MOS tube is reduced to 4.2V for module operation through a diode D1), a diode D1 is connected with the EM300 communication module in the miniPCIE socket circuit, the diode D1 is further connected with an electrolytic capacitor E5, a capacitor C70 and an electrolytic capacitor E6 which are connected in parallel, and the other ends of the electrolytic capacitor E5, the capacitor C70 and the electrolytic capacitor E6 are grounded. The working principle of the power supply control circuit of the communication module EM300 is as follows: the 18 th pin of the MCU chip of the main control board controls the on-off of a P-channel MOS tube PMOS1 through a switch circuit consisting of resistors R47, R48, R74 and a triode N3. When the PMOS1 is conducted, a VDD5.0 power supply is connected to the anode of the diode D1 through the PMOS1 switch tube, the voltage is reduced to 4.2V, and the voltage is supplied to the communication module EM300, so that power supply control of the EM300 communication module is realized.

Fig. 7 is an application circuit diagram of a minippice of a connector of a motherboard-connected communication module, which implements communication and control between an MCU main control board and an EM300 of the communication module through the socket, wherein a minippie socket circuit in an LTE communication board includes an EM350 chip, pins 1, 3, 5, 6, 7, 11, 13, 16, 17, 19, 20, 22, 23, 25, 28, 30, 31, 32, 33, 34, 37, 42, 43, 44, 45, 46, 47, 48, 49 are empty pins, pins 4, 9, 15, 18, 21, 26, 27, 29, 35, 40, 50, 2, 24, 39, 41, 52, and 35 of the EM350 chip are grounded, pins 2, 24, 39, 41, 52, and 52 of the EM350 chip are grounded, pins 3551, 3663n, N, and N of a triode emitter of the EM 366335, the collector of the triode N2 is connected with a resistor R8, a resistor R8 is connected with a light-emitting diode LED7, the light-emitting diode LED7 is connected with a 3V3 power supply, pins 8, 10, 12 and 14 of the EM350 chip are connected with a SIM card seat circuit, and pins 36 and 38 of the EM350 chip are connected with a USB HUB circuit.

Referring to fig. 8, the SIM card holder includes a control chip U15, where pins 1, 3, 5, and 6 of the control chip U15 are connected to an EM350 chip, pins 4 and 9 of the control chip U15 are empty pins, pin 1 of the control chip U15 is grounded through a capacitor C71, pins 1 and 2 of the control chip U15 are connected to pins 10, 11, 12, and 13, pin 5 of the control chip U15 is connected to a transient suppression diode TVS12, the transient suppression diode TVS12 is grounded, pin 3 of the control chip U15 is connected to a transient suppression diode TVS13 through a resistor R34, the transient suppression diode TVS13 is grounded, pin 6 of the control chip U15 is connected to a transient suppression diode TVS14 through a resistor R36, and the transient suppression diode TVS14 is grounded. In fig. 8, a SIM card data interference rejection circuit is added, where the SIN card data interference rejection circuit includes a diode TVS12(RL0603E005M015K), a diode TVS13 (RL0603E005M015K), and a diode TVS14(RL0603E005M015K), the diode TVS12 is connected to a resistor R35 connected to pin 5 in the SIM card socket data circuit, the diode TVS13 is connected to a resistor R34 connected to pin 3 in the SIM card socket circuit, and the diode TVS14 is connected to a resistor R36 connected to pin 6 in the SIM card socket circuit.

Referring to fig. 9-10, a PCIE switch board circuit diagram, wherein (a) is a MiniPCI slot circuit diagram; (b) is an EM300-1 circuit diagram; (c) is a filter circuit diagram of VDD3.3V power supply in PCIE conversion board circuit. The PCIE seat aims at installing a PCIE conversion board, and pins 36 and 38 of the PCIE conversion board are USB communication interfaces of a communication module. This USB interface of communication module passes through the miniCIE socket GSM1 that PCIE adapter plate golden finger inserted the mainboard and is connected with the USB HUB chip U1 of mainboard, passes through the processing of USB HUB chip U1 again and communicates with the MCU chip U3 of mainboard. Pins 1, 3, 5, 7, 16, 19, 20, 23, 25, 30-34, 37, 42-46 and 48-49 of the MiniPCI slot are hollow pins, pins 2, 24, 39, 41 and 52 of the MiniPCI slot are grounded, pins 4, 9, 15, 18, 21, 26, 27, 29, 35, 40 and 50 of the MiniPCI slot are grounded, pin 6 of the MiniPCI slot is grounded to pin 54 of the EM300-1 chip, pin 8 of the MiniPCI slot is grounded to pin 73 of the EM300-1 chip, pin 10 of the MiniPCI slot is grounded to pin 74 of the EM300-1 chip, pin 11 of the MiniPCI slot is grounded to pin 31 of the EM300-1 chip, pin 12 of the MiniPCI slot is grounded to pin 75 of the EM300-1 chip, pin 13 of the MiniPCI slot is grounded to pin 45 of the EM300-1 chip, pin 14 of the MiniPCI slot is grounded to pin 17, pin 76 of the MiniPCI slot is grounded to pin 17 of the EM 1 chip, the 22 pins of the MiniPCI slot are connected with the 69 pins of the EM300-1 chip, the 28 pins of the MiniPCI slot are connected with the 70 pins of the EM300-1 chip, the 36 pins of the MiniPCI slot are connected with the 56 pins of the EM300-1 chip, the 38 pins of the MiniPCI slot are connected with the 55 pins of the EM300-1 chip, the 47 pins of the MiniPCI slot are connected with the 23 pins of the EM300-1 chip, and the 51 pins of the MiniPCI slot are connected with the 68 pins of the EM300-1 chip. In the EM300-1 circuit, pins 1-2, pins 4-11, pins 15-18, pins 20, pins 22, pins 24, pins 25-30, pins 33-37, pins 39-44, pins 47, pins 51-52, pins 59-60, pins 62-63, pins 65-66, pins 71, pins 77-79 and pins 86-92 of an EM300-1 chip are hollow pins, pins 3, 12, 14, 19, 21, 32, 38, 46, 50, 53, 57-58, pins 61, 64, 67, 72, 81 and 85 of the EM300-1 chip are grounded, pins 13 of the EM300-1 chip are connected with a connector ANT1(ANT1 is connected to an external antenna through an RF coaxial cable), pins 13 of the EM300-1 chip are connected with a resistor R3 of the other end of the EM300-1 chip, pins 31 of the EM300-1 chip are connected with a resistor R1, a45 pin of the EM300-1 chip is connected with a resistor R2, 48 pins and 49 pins of the EM300-1 chip are connected with a debugging serial port, a 69 pin of the EM300-1 chip is connected with a capacitor C1 with the other end grounded, a 70 pin of the EM300-1 chip is connected with a capacitor C2 with the other end grounded, an 80 pin of the EM300-1 chip is connected with a power supply VDD1.8, and an 82-84 pin of the EM300-1 chip is connected with a power supply VDD 3.3. The power supply 3.3V of the whole PCIE conversion board circuit is connected with a filter circuit, the filter circuit comprises a capacitor E1 and a capacitor E2 which are connected in parallel, and the other ends of the capacitor E1 and the capacitor E2 are grounded.

Referring to fig. 11-13, the USB HUB circuit includes: a control chip U1, a pin 0 and a pin 11 of a control chip U1 are grounded, a pin 1-2 of a control chip U1 is connected with a miniPPE socket circuit, a pin 3 and a pin 4 of a control chip U1 are connected with a USB1, a pin 5, a pin 10 and a pin 15 of a control chip U1 are connected with a 3V3 power supply, a pin 6-9, a pin 13, a pin 17-18 and a pin 19-21 of a control chip U1 are hollow pins, a pin 12 of the control chip U1 is connected with a 3V 60 power supply through a resistor R60, a pin 14 of the control chip U60 is grounded through a capacitor C60, a pin 16 of the control chip U60 is connected with the power supply 3V 60 through a resistor R60, a pin 22 of the control chip U60 is connected with the 3V 60 power supply through the resistor R60, a pin 23 of the control chip U60 is connected with the 3V 60 power supply, a pin 24 of the control chip U60 is grounded through a resistor R60, a pin 24 of the control chip U60, a resistor R60 is connected with the ground, a control chip C60, and a control chip MCU 60, a resistor (namely a control chip R60, a control chip module) (i.S) is connected with a processing module), the other end of the capacitor C8 is grounded, the other end of the resistor R45 is connected with a 3V3 power supply, the 27 pin of the control chip U1 is connected with the 3V3 power supply through the resistor R9, the 28 pin of the control chip U1 is connected with the 3V3 power supply through the resistor R11, the 29 pin of the control chip U1 is connected with the 3V3 power supply, the 30 pin and the 31 pin of the control chip U1 control module (i.e. MCU processor), the external crystal oscillator XTAL2 is connected between the 32 pin and the 33 pin of the control chip U1, one end of the external crystal oscillator XTAL2 is grounded through the capacitor C9, the other end is grounded through the capacitor C10, the 34 pin of the control chip U1 is grounded through the capacitor C7, the 35 pin of the control chip U1 is grounded through the resistor R7, the 36 pin of the control chip U1 is connected with the 3V3 power supply, fig. 12 is a USB interface circuit diagram in a USB HUB circuit, the USB chip 12 includes a USB chip, the 1 pin of which is grounded, the pin of the USB chip, the pin of the pin 1, the pin of the USB chip, the pin of the pin 3, the pin 364 pin 365, the pin 365 pin, the pin 3 pin of the pin, the pin of the pin 3 pin, the pin of the pin 72 of the pin, the pin of the pin 72 pin, the pin of the pin, the pin of the pin 8745 pin of the pin, the pin 72 of the pin, the pin of the pin, the pin of the pin 72 of the pin, the pin of the pin, the pin of the pin is connected with the pin, the pin 3 of the pin is connected with the pin, the pin 3 of the pin, the pin 3 of the pin, the pin 8 is connected with the shell ground, the pin 4 of the USB chip is connected with the VDD5.0 power supply through a fuse F2, the VDD5.0 power supply connection end of the fuse F2 is also connected with a static protector TVS16(SPE06RAL), and the static protector TVS16 is connected with the ground. Fig. 13 is a schematic diagram of a USB interface static protection circuit in the USB HUB circuit, and fig. 13 includes two static protectors TVS15 (TESD712G2B), one end of which is grounded and the other end of which is connected to the control chip U1.

Referring to fig. 14-15, the watchdog circuit comprises: a control chip U2, a pin 1 of the control chip U2 is connected with a resistor R80, the resistor R80 is connected with a power control circuit and a switch SW3, the switch SW3 is a toggle switch and is used for setting the type of the working mode, the power control circuit comprises a resistor R80 connected with the resistor R80 and a field effect transistor PMOS 80 (CEU6601), a drain D of the field effect transistor PMOS 80 is connected with a 3V 80 power supply and an electrostatic protector TVS 80 (TUSD03FBX), the other end of the electrostatic protector TVS 80 is grounded, a source S of the field effect transistor PMOS 80 and a resistor R80 are connected with a 3.3V power supply, a pin 2-7 of the control chip U80 is a hollow pin, a pin 8 of the control chip U80 is grounded, a pin 9 of the control chip U80 is connected with a capacitor C80, a pin 10 of the resistor R80, a pin 11 is connected with the resistor R80, the other end of the resistor R80 is connected with the resistor R80 and the resistor R80, a pin 12 of the control chip U80 is connected with a resistor R80, a resistor VDD, the resistor R80 and a resistor R360, the resistor R80 is connected with a resistor VDD, the other end of the resistor R38 is connected with the collector of the triode N4, the collector of the triode N5 and the capacitor C4, the emitter of the triode N4, the emitter of the triode N5 and the other end of the capacitor C4 are grounded, the base of the triode N4 is connected with the resistor R10, and the resistor R10 is connected with the control module.

Fig. 16 is a circuit diagram for setting external parameters of each pin in the MCU processor, in which (a) is a circuit diagram for setting external parameters of 21 pins in the MCU processor (in this figure, the switch S is a ripple switch, and 18 pins are set to a high level or a low level respectively by the switch for parameter setting).

Circuit of FLASH memory referring to fig. 17, the FLASH memory selects 8M byte FLASH, and the control chip is W25Q 64. DDR2 memory circuit referring to FIG. 18, the control chip of DDR2 memory is W9751.

Referring to fig. 19-20, the figure shows a 485 transceiver circuit (485 transceiver operation mode control signal circuit), the 485 transceiver circuit includes a control chip U4, pin 1 of the control chip U4 is connected to the MCU processor through a resistor R51, the resistor R51 is further connected to a resistor R66 of another end connection power supply 3V3, pin 2 and pin 3 of the control chip U4 are connected to a resistor R2, the resistor R2 is connected to the power supply VDD5.0, pin 2 and pin 3 are further connected to a triode N1, the emitter of the triode N1 is grounded, the base of the triode N1 is connected to the MCU processor through a resistor R50, pin 4 of the control chip U4 is connected to the MCU processor, pin 5 of the control chip U4 is grounded, a resistor R3 is connected between pin 6 and pin 7 of the control chip U4, pin 6 of the control chip U4 is further connected to a resistor R6 and a resistor R24, the resistor R6 is connected to the power supply VDD5.0, the resistor R24 is connected to another end of the electrostatic charge protector, and the resistor R36 1 is connected to the tvr 23 of the tvu 23, Resistance R4, the ground connection of the other end of resistance R4, the ground connection of the other end of resistance R23 termination electrostatic protection ware TVS2 (SPE06RAL), electrostatic protection ware TVS1, the ground connection of the other end of electrostatic protection ware TVS2, resistance R24 is close to electrostatic protection ware TVS1 end, resistance R23 is close to electrostatic protection ware TVS2 end and connects in connector J3, connector J3 is the USB connector, a TVS device for providing external storage, 485 among the transceiver circuit is antistatic protection design usage. In fig. 20, the connector J3 has a pin 2 connected to one end of the resistor R24 and a pin 1 connected to one end of the resistor R23.

Referring to fig. 21-22, the external 232 serial port circuit includes a control chip U5, an indirect capacitor C21 between pins 1 and 3 of a control chip U5, an indirect capacitor C20 between pins 4 and 5 of the control chip U5, a pin 11 of the control chip U5 is connected to a control module (i.e., an MCU processor) through a resistor R28, pins 7, 8, 9 and 10 of the control chip U5 are blank pins, a pin 12 of the control chip U5 is connected to the control module through a resistor R29, a pin 15 of the control chip U5 is grounded, a pin 13 of the control chip U5 is connected to an electrostatic protection device TVS3, a pin 14 of the control chip U5 is connected to an electrostatic protection device TVS4, the electrostatic protection device TVS3 and the other end of the electrostatic protection device TVS4 are grounded, a pin 6 of the control chip U5 is grounded through a capacitor C22, a pin 2 of the control chip U5 is connected to a capacitor C23, a capacitor C23 is connected to the other end of the capacitor C36 24, and a power supply C5 is connected to a control chip VDD 360, pins 14 and 13 of the control chip U5 are connected to a connector J1 (the connector J1 of fig. 22 is a connection terminal connector for data communication use of the RS232 protocol).

Referring to fig. 23-24, the RJ45 and network transformer circuit includes: a network transformer U12(HX82407S), a control module connected with pins 2, 3, 5, 6, 8, 9, 11 and 12 of the network transformer U12, a TVS7(TUSD03FBX) connected between pins 2 and 3, a TVS8(TUSD03FBX) arranged between pins 5 and 6 of the network transformer U12, a TVS5(TUSD03FBX) arranged between pins 8 and 9 of the network transformer U12, a TVS6(TUSD03FBX) arranged between pins 11 and 12 of the network transformer U12, a TVS6(TUSD03FBX) arranged between pins 23, 22, 20 and 19 of the network transformer U12, a connector J5(RJ 8-3) connected with pins J12, 17, 16, 14 and 13 of the network transformer U6 (RJ45-3), a gas discharge tube connected with pins 22 and 23 of the network transformer U12, a gas discharge tube 1, a gas discharge tube of the network transformer U4642, and a gas discharge tube GD 16 of the network transformer GD 4616, A pin 17 is connected with a gas discharge tube GD3, pins 13 and 14 of a network transformer U12 are connected with a gas discharge tube GD4, a pin 13 of a connector J5 and a pin 13 of a connector J6 are connected with a 3V3 power supply through a resistor R57, and a pin 16 of a connector J5 and a pin 16 of a connector J6 are connected with a control module. Referring to fig. 24, a discharge tube GD1 is connected to pins 22 and 23 of the network transformer U12, and the discharge tube GD1 is grounded; a discharge tube GD2 is connected with pins 19 and 20 of the network transformer U12, and the discharge tube GD2 is grounded; a discharge tube GD3 is connected with pins 16 and 17 of the network transformer U12, and a discharge tube GD3 is grounded; the discharge tube GD4 is connected to pins 13 and 14 of the network transformer U12, and the discharge tube GD4 is grounded.

Referring to fig. 25, the WPS indicator lamp circuit includes a light emitting diode LED3, a light emitting diode LED3 is connected to a resistor R17, and a resistor R17 is connected to a 3V3 power supply, referring to fig. 26, the power indicator lamp includes a light emitting diode LED2, a light emitting diode LED2 is grounded at one end and connected to a resistor R53 at the other end, and a resistor R53 is connected to a power supply 3V 3. The WPS indicating lamp circuit is used for indicating the WiFi working state, and the power supply indicating lamp circuit is used for indicating whether the equipment is powered.

FIG. 27 is a voltage filter circuit for different voltages in an MCU processor circuit, wherein (a) the filter circuit supplies 3V3 voltage; (b) a filter circuit for supplying 3V3 voltage; (c) a filter circuit for supplying 1V2 voltage; (d) a filter circuit for supplying 1V8 voltage; the circuit is a filter circuit for supplying power to different voltages, and the filter circuit can be connected with respective voltage interfaces in a butt joint mode.

Referring to fig. 28, the first power supply 5V output circuit includes a control chip U11, a pin 1 and a pin 6 of the control chip U11 are idle pins, a diode D3 is connected between a pin 2 and a pin 3 of the control chip U11, a pin 2 of the control chip U11 is connected to an inductor L23, a pin 3 of the control chip U11 is grounded, an inductor L23 is connected to a resistor R71 and a resistor R72 which are connected in series, a resistor R71 and a resistor R72 which are connected in series are grounded at one end, a resistor R71 and a resistor R71 which are connected in series are connected in parallel to a static protector TVS 71 (for example, a static protector TUSD03FBX for anti-static protection), the static protector TVS 71 is connected in parallel to a capacitor C71 which is grounded at one end, the capacitor C71 is connected in parallel to an electrolytic capacitor E71, an anode of the electrolytic capacitor E71 is connected to a voltage output terminal VDD5.0, the control chip U71 is connected to a pin 71 of the control chip U71 and the other end of the control chip U71 is connected to a pin 71 and the capacitor C71 is connected to the ground at the other end of the control chip U71 and the pin 71 of the control chip U71 and the capacitor C71 Capacitor C11, electrolytic capacitor E4, electrolytic capacitor E4's positive pole links to each other with voltage output VCC, and electrolytic capacitor E4's positive pole is connected to diode D2, and diode D2 is connected in inductance L2, is provided with the electrostatic protection ware TVS11 of other end ground connection between diode D2 and inductance L2, and inductance L2 is connected in self-recovery insurance paster F1, and self-recovery insurance paster F1 connects in power input VIN.

Referring to fig. 29, the output circuit of the second power supply 3.3V includes a control chip U16, pins 1 and 6 of the control chip U16 are empty pins, a diode D5 is connected between pins 2 and 3 of the control chip U16, one end of the diode D5 is grounded, a pin 2 of the control chip U16 is connected to an inductor L24, the inductor L24 is connected to a resistor R25 and a resistor R26 which are connected in series, the other end of the resistor R25 and the other end of the resistor R26 are grounded, a resistor R25 and a resistor R26 which are connected in series are connected in parallel to a capacitor C37 whose other end is grounded, a capacitor C37 is connected in parallel to an electrolytic capacitor E7, the anode of the electrolytic capacitor E7 is connected to the voltage output terminal 3.3V, a pin 4 of the control chip U16 is connected between a resistor R25 and a resistor R26, a pin 5 of the control chip U16 is grounded, a pin 7 and a pin 8 of the control chip U16 is connected to a ground, and a surge protection circuit is a surge protection circuit for protecting the input voltage of the VCC power supply C16, one end of the voltage dependent resistor MOV3 is connected to the power input end VIN, the other end is connected to the discharge tube GD5, one end of the discharge tube GD5 is connected to the negative pole of the circuit, and one end is connected to the outer shell (the outer shell mentioned earlier), and the ground wire is connected to the ground through the outer shell, so that the high-energy lightning stroke surge current is discharged. Fig. 31 shows a capacitive ac coupling circuit between the case ground and the negative terminal of the circuit, where the capacitor C12, the capacitor C13, the capacitor C14, the capacitor C15, and the capacitor C16 are grounded at one end and grounded at the other end. Fig. 32 shows an interface circuit of a power input socket, where one path of VIN is connected to the positive terminal of the power input, one path of VIN is connected to the negative terminal of the power input, and one path of VIN is connected to the ground of the housing.

The working principle of the terminal is as follows: after the terminal is powered on, the MCU controls the communication module EM300 to automatically dial up and access the LTE-1.8G electric power wireless private network, and periodically inquires parameters representing network coverage quality such as signal strength RSSI, signal to noise ratio SINR and the like of the current wireless private network through the EM300 communication module, and uploads the parameters to the management platform, so that the real-time monitoring of the coverage quality of the current wireless private network is realized. Meanwhile, when the terminal cannot connect the management platform due to poor quality of the private network, the terminal MCU controls the EM300 communication module to be switched to the 4G-LTE public network wireless network (mobile, Unicom and telecom 4G network) at fixed time, and the stored private network signal quality parameters are transmitted back to the management platform through the public network 4G network.

The 1.8G private network signal quality detection terminal is network signal quality detection equipment which is independently developed by Shanghai glow discharge and is specially used for an LTE-1.8G wireless private network communication system. The method has the main functions of monitoring the signal quality covered by each service system of the electric power wireless communication private network in real time, uploading the monitoring index parameters to a network management platform and providing data support for optimizing the network coverage quality.

(1) Specification parameters

External dimensions: 111mm (L) x 85mm (W) x 30mm (H)

Weight: 260g of

The working temperature is … … … -30 ℃ to +70 ℃;

the storage temperature is … … … -40 ℃ to +85 ℃;

power input: direct current is 9V-24V;

power less than 5W;

(2) external interface of terminal equipment

Power interface: the plus is connected with a power input (9-24 VDC); "-" is connected with the negative pole of the power supply;

is connected with a protective ground

USB interface: 1 is provided with

10/100M Ethernet interface: 2, the number of the cells is 2; LAN1 and LAN 2; when data is transmitted, the indicator light flickers.

RS232 serial communication port: 1 piece (debugging port)

RS485 bus interface: 1 is provided with

Communication antenna interface: SMA coaxial lines;

status indicator light

"4G" is normally bright: not accessing the network; flashing: PPP dialing success, accessed network

The 'power supply' is normally on: powering on the equipment; extinguishing: the apparatus is not powered

LAN socket green indicator: flashing: transmitting corresponding network port data;

normally bright: standby;

extinguishing: network card not connected

The 1.8G private network signal quality detection terminal is a gateway between a field network and a service network which are compatible with a public network and a private network. The device has the main functions of realizing the real-time monitoring of the private network signals by regularly inquiring parameters representing the service quality of the private network signals such as the RSSI \ RSRP, SINR and the like of the private network signals and regularly reporting data to a network management service platform. The equipment can also be used as a data communication terminal to access a service carrying local area network, and can detect and evaluate network service quality such as data delay of a related service local area network by using a general network communication diagnosis tool.

The functional characteristics are as follows:

high-performance MCU based on MIPS framework, strong processing capability and meeting harsh working environment

Adopting the Huashi company eLTE public specific communication module eM300-118 (the aforementioned "1.8G public specific communication module EM 300", namely the Huashi company eLTE public specific communication module eM300-118)

Support multiple modes of regular routing, post-routing, NAT, etc

Rich network interface, support 2-way 10/100M adaptive Ethernet port

The network management configuration is simple and easy to maintain; support multiple functions of system information management, gateway configuration, equipment management and the like

Remote network management supporting autonomous development of Shanghai glow discharge, and capable of remotely setting parameters, restarting and managing terminals on line

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the utility model, and that various changes in form and details may be made therein without departing from the spirit and scope of the utility model in practice.

Claims (4)

1.1.8G private network signal quality testing terminal, its characterized in that, it includes a encapsulation shell that constitutes by drain pan and upper cover, install the circuit board through the fixed column in the encapsulation shell, the circuit board includes main control board and LTE communication board, the main control board includes: the MCU processor is connected with the power module, the FLASH memory, the watchdog, the USB HUB circuit, the DDR2 memory, the Ethernet interface and the RS485 interface, the USB HUB circuit is connected with the USB interface, the power module is connected with the 9-36V DC input port through the power protection interface protection circuit, and the Ethernet interface, the RS485 interface and the USB interface are connected with the data interface protection circuit;

the LTE communication board includes: 1.8G public specific body communication module EM300, 1.8G public specific body communication module EM300 is connected in step-down conversion module, step-down conversion module connects in miniPCE interface, and miniPCE interface connection is in the power module and the USB HUB circuit of main control board.

2. The 1.8G private network signal quality detection terminal according to claim 1, wherein the main control board and the LTE communication board are of a split structure.

3. The 1.8G private network signal quality detection terminal of claim 1, wherein the power input control circuit of the LTE communication board comprises a transistor N3, the B electrode of the transistor N3 is connected with a resistor R47, the other end of the resistor R47 is connected with the pin 18 of the control chip U3, the E electrode of the transistor N3 is grounded, the C electrode of the transistor N3 is connected with a resistor R48, the other end of the resistor R48 is connected with a P-channel enhancement type field effect transistor PMOS1, a resistor R74 is connected between the G electrode and the S electrode of the P-channel enhancement type field effect transistor PMOS1, the S electrode of the P-channel enhancement type field effect transistor PMOS1 is connected with a VDD5.0 power supply, the VDD5.0 power supply is connected with a capacitor C69 and an electrolytic capacitor E3 which are connected in parallel, the other ends of the electrolytic capacitor E3 and the capacitor C69 are grounded, the D electrode of the P-channel enhancement type field effect transistor PMOS1 is connected with a diode D1, a diode 493D 1 is connected with an EM communication module 300 in the iPLCIE socket circuit, and an electrolytic capacitor D1 is connected with an electrolytic capacitor E5 in parallel, The other ends of the capacitor C70, the electrolytic capacitor E6, the electrolytic capacitor E5, the capacitor C70 and the electrolytic capacitor E6 are grounded.

4. The 1.8G private network signal quality detection terminal according to claim 1, wherein a communication module power supply voltage reduction circuit is arranged between the power module and the miniPCIE interface.

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