CN215814901U - Display device - Google Patents

Abstract

The utility model provides a display device capable of reducing radiation noise. A display device according to an embodiment includes: a display Panel (PNL) having a first electronic circuit and a second electronic circuit; a first power line (Lp1) electrically connected to the first electronic circuit; a second power supply line (Lp2) electrically connected to the second electronic circuit; and a power supply circuit (3) that applies a first power supply voltage to the first power supply line and the second power supply line. A first resistor is connected to the first power supply line (Lp 1).

Description

Display device

Cross Reference to Related Applications

The present invention is based on and claims priority from japanese patent application No. 2020-143288, filed on 27/8/2020, and the entire content of this original patent application is incorporated herein by reference.

Technical Field

Embodiments of the present invention relate to a display device.

Background

The EMC (Electro-Magnetic Compatibility) standard for electronic devices such as display devices is becoming more and more strict. For example, it is required to reduce the level of emission noise (EMI) from the display device. Therefore, in a display panel such as a liquid crystal display panel, there is a demand for solving the problem that the level of various driving signals and radiation noise in the AM band from a power supply or the like becomes high.

SUMMERY OF THE UTILITY MODEL

The utility model provides a display device capable of reducing radiation noise.

A display device according to an embodiment includes: a display panel having a first electronic circuit and a second electronic circuit; a first power line electrically connected to the first electronic circuit; a second power line electrically connected to the second electronic circuit; and a power supply circuit configured to apply a first power supply voltage to the first power supply line and the second power supply line, wherein a first resistor is connected to the first power supply line.

The display device may further include a wiring substrate connected to the display panel, the wiring substrate including: a first lead electrically connected to the first electronic circuit; and a second lead located at a distance from the first lead, electrically connected to the power supply circuit, and constituting a part of the first power supply line together with the first lead, wherein the first resistor is a discrete resistor, is mounted on the wiring substrate, is electrically connected between the first lead and the second lead, and is connected to the first power supply line in series.

The display panel may further include a first connection wiring electrically connected between the first electronic circuit and the power supply circuit and constituting a part of the first power supply line, and a second connection wiring electrically connected between the second electronic circuit and the power supply circuit and constituting a part of the second power supply line, and the first resistor may be provided in the display panel and connected in parallel to the first connection wiring.

The first resistor may have a first end connected to a first connection portion of the first connection line and a second end connected to a second connection portion of the first connection line, and a resistance value between the first end and the second end of the first resistor may be larger than a resistance value between the first connection portion and the second connection portion of the first connection line.

The first resistor may be a wiring, and a resistance value of a material forming the first resistor may be larger than a resistance value of a material forming the first connection wiring and may be larger than a resistance value of a material forming the second connection wiring.

The display panel may further include: scanning a line; a signal line; a switching element electrically connected to the scanning line and the signal line; and a pixel electrode electrically connected to the switching element, wherein the first connection wiring, the second connection wiring, and the signal line are formed of the same material, and the first resistor and the scan line are formed of the same material.

The first resistor may be a wiring, and a part of the first resistor may be located at a position spaced apart from the first connection wiring in a plan view.

The display panel may further include: scanning a line; a signal line; a switching element electrically connected to the scanning line and the signal line; and a pixel electrode electrically connected to the switching element, wherein the first connection wiring, the second connection wiring, and the signal line are formed of the same material, and the first resistor and the scan line are formed of the same material.

The first resistor may be a wiring, and a resistance value of a material forming the first resistor may be larger than a resistance value of a material forming the first connection wiring and may be larger than a resistance value of a material forming the second connection wiring.

The display panel may further include: scanning a line; a signal line; a switching element electrically connected to the scanning line and the signal line; and a pixel electrode electrically connected to the switching element, wherein the first connection wiring, the second connection wiring, and the signal line are formed of the same material, and the first resistor and the scan line are formed of the same material.

The first resistor may be a wiring, and a part of the first resistor may be located at a position spaced apart from the first connection wiring in a plan view.

The display panel may further include: scanning a line; a signal line; a switching element electrically connected to the scanning line and the signal line; and a pixel electrode electrically connected to the switching element, wherein the first connection wiring, the second connection wiring, and the signal line are formed of the same material, and the first resistor and the scan line are formed of the same material.

The display panel may further include a first connection wiring and a second connection wiring, and the first connection wiring may include: a first wiring portion electrically connected to the first electronic circuit; and a second wiring portion located at a distance from the first wiring portion and electrically connected to the power supply circuit, wherein the second connection wiring is electrically connected between the second electronic circuit and the power supply circuit and constitutes a part of the second power supply line, and the first resistor is provided in the display panel, electrically connected between the first wiring portion and the second wiring portion, and connected to the first power supply line in series.

The first resistor may be a wiring, and a resistance value of a material forming the first resistor may be larger than a resistance value of a material forming the first connection wiring and may be larger than a resistance value of a material forming the second connection wiring.

The display panel may further include: scanning a line; a signal line; a switching element electrically connected to the scanning line and the signal line; and a pixel electrode electrically connected to the switching element, wherein the first connection wiring, the second connection wiring, and the signal line are formed of the same material, and the first resistor and the scan line are formed of the same material.

The first resistor may be a wiring, and a part of the first resistor may be located at a position spaced apart from the first connection wiring in a plan view.

The display panel may further include: scanning a line; a signal line; a switching element electrically connected to the scanning line and the signal line; and a pixel electrode electrically connected to the switching element, wherein the first connection wiring, the second connection wiring, and the signal line are formed of the same material, and the first resistor and the scan line are formed of the same material.

The first power supply line and the second power supply line may be electrically connected to the same first power supply terminal of the power supply circuit.

The display device may further include: a third power line electrically connected to the first electronic circuit; a fourth power line electrically connected to the second electronic circuit; and a second resistor connected to the third power supply line, wherein the power supply circuit applies a second power supply voltage different from the first power supply voltage to the third power supply line and the fourth power supply line.

The voltage level of the second power supply voltage may be lower than the voltage level of the first power supply voltage.

Drawings

Fig. 1 is a plan view showing a display device according to a first embodiment.

Fig. 2 is a circuit diagram showing the display panel shown in fig. 1.

Fig. 3 is a cross-sectional view showing a display region of the display panel.

Fig. 4 is a circuit diagram showing the display device.

Fig. 5 is a diagram showing voltage waveforms and current waveforms of the drive signals in the first embodiment and the comparative example.

Fig. 6 is a plan view showing a part of the display device, and is a diagram showing a state in which a resistor is mounted on a wiring substrate.

Fig. 7 is a plan view showing a non-display region of the display panel, and is a view showing a plurality of pads and a plurality of power supply lines.

Fig. 8 is a plan view showing a non-display region of the display panel, and is a diagram showing a plurality of circuits and a plurality of power supply lines.

Fig. 9 is a plan view showing a part of the display device according to the first modification of the first embodiment, and is a diagram showing a state in which a resistor is provided on the display panel.

Fig. 10 is a plan view showing a part of the display panel according to the first modification, and is a diagram showing a state in which resistors are connected in parallel to a power supply line.

Fig. 11 is a plan view showing a part of the display panel according to the second modification of the first embodiment, and is a diagram showing a state in which a power supply line is disconnected and one resistance is disconnected.

Fig. 12 is a plan view showing a part of a display panel according to a third modification of the first embodiment, and is a diagram showing a state in which resistors are connected in parallel to a power supply line.

Fig. 13 is a circuit diagram showing a display device according to a second embodiment.

Fig. 14 is a plan view showing a non-display region of the display panel according to the second embodiment, and is a view showing a plurality of pads and a plurality of power supply lines.

Fig. 15 is a plan view showing a non-display region of the display panel according to the second embodiment, and is a diagram showing a plurality of circuits and a plurality of power supply lines.

Detailed Description

Embodiments and modifications of the present invention will be described below with reference to the drawings. The disclosure is merely an example, and it is needless to say that the embodiment which can be easily conceived by those skilled in the art can be included in the scope of the present invention. The drawings are for more clearly explaining the present invention, and the width, thickness, shape, and the like of each portion may be schematically shown as compared with the actual state. In the present specification and the drawings, the same elements as those described in the already-shown drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(first embodiment)

First, a first embodiment will be explained. In this embodiment, a liquid crystal display device will be described as an example of the display device DSP. The main configuration disclosed in this embodiment mode can be applied to a self-light-emitting display device such as an organic electroluminescence display device, an electronic paper-type display device such as an electrophoretic display device, a display device to which MEMS (Micro Electro Mechanical Systems) is applied, a display device to which electrochromic properties are applied, and the like. The main configuration disclosed in this embodiment mode is not limited to the display device, and can be applied to electronic apparatuses other than the display device.

Fig. 1 is a plan view showing a display device DSP according to the first embodiment.

As shown in fig. 1, in one example, the first direction X, the second direction Y, and the third direction Z are perpendicular to each other, but may intersect at an angle other than 90 degrees. The first direction X and the second direction Y correspond to a direction parallel to a main surface of a substrate constituting the display device DSP, and the third direction Z corresponds to a thickness direction of the display device DSP. In the present specification, a direction toward the tip of an arrow indicating the third direction Z is referred to as "up", and a direction toward the opposite direction from the tip of the arrow is referred to as "down". In the case of the expressions "second member above the first member" and "second member below the first member", the second member may be in contact with the first member or may be separated from the first member. Further, the display device DSP is provided with an observation position on the tip side of an arrow indicating the third direction Z, and the observation from the observation position to the X-Y plane defined by the first direction X and the second direction Y is referred to as a plan view.

The display device DSP includes a display panel PNL, a driver IC1, a wiring board 2, and a power supply circuit 3. In the present embodiment, the wiring substrate 2 is a Flexible Printed Circuit (FPC). However, the wiring substrate 2 may be a Printed Circuit Board (PCB).

The display panel PNL is a liquid crystal display panel, and includes a first substrate SUB1, a second substrate SUB2, and the like. The display panel PNL includes a display area DA for displaying an image and a frame-shaped non-display area NDA surrounding the display area DA. The non-display area NDA includes an extended protrusion area EA where the first substrate SUB1 is located but the second substrate SUB2 is not located.

The driver IC1 is mounted on the extended protrusion area EA of the display panel PNL (first substrate SUB 1). The wiring substrate 2 is connected to the extended protrusion area EA of the first substrate SUB 1. The driver IC1 may be mounted on the wiring board 2. The driver IC1 incorporates a display driver that outputs signals necessary for displaying an image.

Fig. 2 is a circuit diagram illustrating the display panel PNL shown in fig. 1.

As shown in fig. 2, the display panel PNL includes a plurality of pixels PX in the display area DA. The plurality of pixels PX are arranged in a matrix along the first direction X and the second direction Y.

The display panel PNL includes m scanning lines G (G1 to Gm), n signal lines S (S1 to Sn), and a common line CL. M and n are each an integer of 2 or more. The scanning lines G and the signal lines S intersect each other in the display area DA. The common line CL extends in the non-display area NDA.

The scanning line G is connected to the scanning line driving circuit GD. The signal line S is connected to the signal line driving circuit SD. In the present embodiment, the signal line driving circuit SD is a demultiplexer. The common line CL is connected to the driver IC 1. The driver IC1 is connected to the timing controller T. The timing controller T is connected to the scanning line driving circuit GD and the signal line driving circuit SD.

The scanning lines G, the scanning line driving circuit GD, the signal lines S, the signal line driving circuit SD, the common lines CL, and the timing controller T are formed on the first substrate SUB1 shown in fig. 1. Signals necessary for the operation of the scanning line driving circuit GD are supplied from the timing controller T and the power supply circuit 3 shown in fig. 1. Signals necessary for the operation of the signal line drive circuit SD are supplied from the driver IC1, the timing controller T, and the power supply circuit 3.

The display panel PNL includes a liquid crystal layer LC. Each pixel PX includes a switching element SW, a pixel electrode PE, a common electrode CE, a liquid crystal layer LC, and the like. The switching element SW is formed of, for example, a TFT (thin film transistor), and is electrically connected to the scanning line G and the signal line S. The pixel electrode PE is electrically connected to the switching element SW. The common electrode CE is electrically connected to the common line CL. The common electrode CE is shared by a plurality of pixels PX.

The scanning line driving circuit GD outputs a control signal for switching between a conductive state and a non-conductive state of the switching element SW connected to the scanning line G. The signal line driving circuit SD outputs a video signal to the signal line S while the switching element SW is in the on state. Thereby, a desired pixel potential is written to the pixel electrode PE. In addition, the driver IC1 supplies a common potential to the common line CL. Thereby, the common electrode CE becomes a common potential. In each pixel PX, each pixel electrode PE faces the common electrode CE, and the liquid crystal layer LC is driven by an electric field generated by a potential difference between a pixel potential of the pixel electrode PE and a common potential of the common electrode CE. The holding capacitor CS is formed between an electrode having the same potential as the common electrode CE and an electrode having the same potential as the pixel electrode PE, for example.

Fig. 3 is a sectional view showing the display area DA of the display panel PNL. The illustrated example corresponds to an application example of an FFS (Fringe Field Switching) mode, which is one of display modes using a horizontal electric Field. The display panel PNL may have any one of the following structures: a configuration corresponding to a display mode using a lateral electric field along the main surface of the substrate, a configuration corresponding to a display mode using a vertical electric field along the normal to the main surface of the substrate, a configuration corresponding to a display mode using an oblique electric field that is oblique in an oblique direction with respect to the main surface of the substrate, and a configuration corresponding to a display mode using the lateral electric field, the vertical electric field, and the oblique electric field in appropriate combination. The substrate main surface herein means a surface parallel to the X-Y plane.

As shown in fig. 3, the first substrate SUB1 includes an insulating substrate 10, insulating layers 11 to 15, a light shielding layer US, a semiconductor layer SC, a scanning line G, a signal line S, a connection electrode RE, a common electrode CE, a pixel electrode PE, and an alignment film AL 1. The insulating substrate 10 is a transparent substrate such as a glass substrate or a resin substrate. The light shielding layer US is located between the insulating substrate 10 and the insulating layer 11. In the illustrated example, the light shielding layer US is formed to overlap both the gate electrodes, but may be provided at a distance from each other.

The semiconductor layer SC is located between the insulating layer 11 and the insulating layer 12. The semiconductor layer SC is formed of, for example, polysilicon, but may be formed of amorphous silicon or an oxide semiconductor. Two gate electrodes GE as a part of the scanning line G are located between the insulating layer 12 and the insulating layer 13. The signal line S and the connection electrode RE are located between the insulating layer 13 and the insulating layer 14. The signal line S and the connection electrode RE are in contact with the semiconductor layer SC, respectively.

The common electrode CE is located between the insulating layer 14 and the insulating layer 15. The pixel electrode PE is located between the insulating layer 15 and the alignment film AL 1. A part of the pixel electrode PE faces the common electrode CE. The common electrode CE and the pixel electrode PE are formed of a transparent conductive material such as Indium Tin Oxide (ITO) or indium-doped zinc oxide (IZO). The pixel electrode PE passes through the contact hole CH penetrating the insulating layers 14 and 15 at a position overlapping the opening AP of the common electrode CE, and contacts the connection electrode RE. The insulating layers 11 to 13 and the insulating layer 15 are inorganic insulating layers formed of a transparent inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may have a single-layer structure or a multi-layer structure. The insulating layer 14 is an organic insulating layer formed of a transparent organic insulating material such as an acrylic resin.

The second substrate SUB2 includes an insulating substrate 20, a light-shielding layer BM, a color filter layer CF, an overcoat layer OC, and an alignment film AL 2. The insulating substrate 20 is a transparent substrate such as a glass substrate or a resin substrate. The light-shielding layer BM and the color filter layer CF are located between the insulating substrate 20 and the overcoat layer OC. The orientation film AL2 covers the overcoat layer OC.

The liquid crystal layer LC is located between the first substrate SUB1 and the second substrate SUB2, and is held between the alignment films AL1 and AL 2. The liquid crystal layer LC is formed of a positive type (dielectric anisotropy is positive) liquid crystal material or a negative type (dielectric anisotropy is negative) liquid crystal material.

The optical element OD1 including the polarizing plate PL1 is disposed below the first substrate SUB 1. The optical element OD2 including the polarizing plate PL2 is disposed above the second substrate SUB 2. The optical elements OD1 and OD2 may include a retardation plate, a scattering layer, an antireflection layer, and the like as needed. The illumination device IL is positioned below the optical element OD 1.

The display device DSP of the present embodiment is a transmissive display device, and has a transmissive display function of selectively transmitting light from the lower surface side of the first substrate SUB1 to display an image. However, the display device DSP may be any one of the following display devices: a reflective display device having a reflection display function of selectively reflecting light from the upper surface side of the second substrate SUB2 to display an image, and a transflective display device having a transmissive display function and a reflective display function.

Fig. 4 is a circuit diagram showing the display device DSP.

As shown in fig. 4, the display panel PNL, the driver IC1, and the wiring substrate 2 are electrically connected. The wiring substrate 2 receives an external input of the power Vw and the data signal Sa. The power Vw input to the wiring board 2 is supplied to the driver IC1 and the power supply circuit 3, and the data signal Sa input to the wiring board 2 is supplied to the driver IC 1.

The driver IC1 gives the first output signal So1 to the signal line drive circuit SD and the second output signal So2 to the timing controller T. The timing controller T includes a first circuit CK1, a second circuit CK2, and a third circuit CK 3.

The display device DSP further includes a first power line Lp1 and a third power line Lp 3. The first power supply line Lp1 is electrically connected to the first power supply terminal 3a of the power supply circuit 3, and the third power supply line Lp3 is electrically connected to the second power supply terminal 3b of the power supply circuit 3. The power supply circuit 3 applies a first power supply voltage Vp1 to the first power supply line Lp1, and applies a second power supply voltage Vp2 different from the first power supply voltage Vp1 to the third power supply line Lp 3. The voltage level of the second supply voltage Vp2 is lower than the voltage level of the first supply voltage Vp 1. In the present embodiment, the first power voltage Vp1 is a gate high Voltage (VGH), and the second power voltage Vp2 is a gate low Voltage (VGL). For example VGH +10V, VGL +5V, or VGH +5V, VGL-5V, or VGH-5V, VGL-10V.

The display device DSP includes a resistor R1 and a resistor R2. The resistor R1 is connected to the first power supply line Lp1 and functions as a first resistor. The resistor R2 is connected to the third power supply line Lp3 and functions as a second resistor. Therefore, the first power voltage Vp1 is adjusted to the first power voltage Vp1a through the resistor R1. The second supply voltage Vp2 is adjusted to a second supply voltage Vp2a through a resistor R2. The display device DSP may include only one of the resistor R1 and the resistor R2.

A first power supply line Lp1 and a third power supply line Lp3 are connected to the scanning line driver circuit GD, the signal line driver circuit SD, the first circuit CK1, the second circuit CK2, and the third circuit CK 3. The scanning line driver circuit GD, the signal line driver circuit SD, the first circuit CK1, the second circuit CK2, and the third circuit CK3 each function as a first electronic circuit using an active element such as a TFT.

The scan line driver circuit GD, the signal line driver circuit SD, the first circuit CK1, the second circuit CK2, and the third circuit CK3 are each supplied with a first power supply voltage Vp1a via a first power supply line Lp1, and are supplied with a second power supply voltage Vp2a via a third power supply line Lp 3. The signal line drive circuit SD is also input with a first output signal So1 from the driver IC 1.

The first circuit CK1, the second circuit CK2, and the third circuit CK3 are also inputted with a second output signal So2 from the driver IC1, respectively. The first circuit CK1 and the second circuit CK2 are electrically connected to the scan line driver circuit GD, and the third circuit CK3 is electrically connected to the signal line driver circuit SD. The scan line driving circuit GD receives the first driving signal Sd1 from the first circuit CK1, and receives the second driving signal Sd2 from the second circuit CK 2. The third driving signal SD3 is input to the signal line driving circuit SD from the third circuit CK 3. The scanning line driving circuit GD outputs a control signal SG to the scanning lines G, and the signal line driving circuit SD outputs a video signal Vsig to the signal lines S.

As described above, the first circuit CK1, the second circuit CK2, and the third circuit CK3 are supplied with the first power supply voltage Vp1a and the second power supply voltage Vp2a, respectively, instead of the first power supply voltage Vp1 and the second power supply voltage Vp 2. Accordingly, the first, second, and third driving signals Sd1, Sd2, and Sd3 are resistance-adjusted.

Here, the first drive signal Sd1 is focused on as representative of the plurality of drive signals. The first drive signal Sd1 of the present embodiment is described in comparison with the first drive signal Sd1 of the comparative example. The display device DSP of the comparative example is different from the display device DSP of the present embodiment in that it is configured without the resistors R1 and R2. Fig. 5 is a diagram showing the voltage waveform and the current waveform of the drive signal (first drive signal Sd1) in the present embodiment and the comparative example.

As shown in fig. 5, according to the voltage waveform of the first drive signal Sd1 of the comparative example, the rising period and the falling period of the pulse are relatively short. In contrast, as is clear from the voltage waveform of the first drive signal Sd1 of the present embodiment, the rising period and the falling period of the pulse are relatively long.

Thus, the peak current of the first drive signal Sd1 can be made different between the present embodiment and the comparative example. That is, by dulling the rise and fall of the voltage waveform of the first drive signal Sd1 of the present embodiment, the peak current of the first drive signal Sd1 of the present embodiment can be relatively suppressed. In this case, the level of the radiated noise (EMI) from the display device DSP can be reduced in the present embodiment as compared with the comparative example.

The same applies to the second drive signal Sd2 and the third drive signal Sd3, as to the matters related to the first drive signal Sd1 described above.

Fig. 6 is a plan view showing a part of the display device DSP, and shows a state in which the resistors R1 and R2 are mounted on the wiring board 2.

As shown in fig. 6, the wiring substrate 2 includes a first lead Le1, a second lead Le2, a third lead Le3, and a fourth lead Le 4. The first lead Le1 and the second lead Le2 constitute a part of the first power supply line Lp 1. The third lead Le3 and the fourth lead Le4 constitute a part of the third power supply line Lp 3.

The first lead Le1 is electrically connected to the scan line driver circuit GD, the signal line driver circuit SD, the first circuit CK1, the second circuit CK2, and the third circuit CK3, respectively. The second lead Le2 is located at a distance from the first lead Le1 and is electrically connected to the first power terminal 3a of the power supply circuit 3.

The third lead Le3 is electrically connected to the scan line driver circuit GD, the signal line driver circuit SD, the first circuit CK1, the second circuit CK2, and the third circuit CK3, respectively. The fourth lead Le4 is located at a distance from the first lead Le1, the second lead Le2, and the third lead Le3, and is electrically connected to the second power terminal 3b of the power supply circuit 3.

The resistor R1 is a discrete resistor and is mounted on the wiring board 2. The resistor R1 is electrically connected between the first lead Le1 and the second lead Le2, and is connected in series to the first power supply line Lp 1.

Similarly, the resistor R2 is a discrete resistor and is mounted on the wiring board 2. The resistor R2 is electrically connected between the third lead Le3 and the fourth lead Le4, and is connected in series to the third power supply line Lp 3.

When the resistor R is a discrete resistor, there is an advantage that a plurality of types of resistors R having different resistance values can be replaced when evaluating the level of radiation noise, and the resistance value can be adjusted to a desired value. The resistor R having a target resistance value may be mounted in mass production. Further, the resistance value of the resistor R can be adjusted in a wide range, and there is an advantage that the variation in resistance value between the same type of resistors R is relatively small.

Fig. 7 is a plan view showing the non-display region NDA of the display panel PNL, and shows a plurality of pads p and a plurality of power supply lines Lp. In the figure, the power supply line Lp is hatched.

As shown in fig. 7, the display panel PNL (first substrate SUB1) includes a first connection line Lw1 and a third connection line Lw 3.

As shown in fig. 4, 6, and 7, the first connecting wiring Lw1 constitutes a part of the first power supply line Lp1, and is electrically connected between the circuit group (the scanning line driving circuit GD, the signal line driving circuit SD, the first circuit CK1, the second circuit CK2, and the third circuit CK3) and the first power supply terminal 3a of the power supply circuit 3. The third connecting wiring Lw3 forms a part of the third power supply line Lp3, and is electrically connected between the circuit group (the scanning line driving circuit GD, the signal line driving circuit SD, the first circuit CK1, the second circuit CK2, and the third circuit CK3) and the second power supply terminal 3b of the power supply circuit 3.

A plurality of pads p of the olb (outer lead bonding) are arranged in the extended protrusion area EA of the first substrate SUB 1. The first connection line Lw1 is connected to the pad p1 and the pad p2 among the plurality of pads p, and the third connection line Lw3 is connected to the pad p3 and the pad p 4.

For connection between the wiring substrate 2 and the display panel PNL (first substrate SUB1), for example, a thermocompression bonding method using an ACF (anisotropic conductive film) is used. According to this method, the electrical connection between the plurality of pads p of the first substrate SUB1 and the plurality of pads of the wiring substrate 2 is ensured. The first connection wiring Lw1 is electrically connected to the first lead Le1 of the wiring substrate 2 via the pads p1, p 2. The third connection wiring Lw3 is electrically connected to the third lead Le3 of the wiring substrate 2 via the pads p3, p 4.

Fig. 8 is a plan view showing the non-display region NDA of the display panel PNL, and shows the plurality of circuits CK and the plurality of power supply lines Lp.

As shown in fig. 8, the first circuit CK1, the second circuit CK2, and the third circuit CK3 are located in the non-display area NDA of the first substrate SUB 1. The first connection wiring Lw1 and the third connection wiring Lw3 extend in the non-display region NDA. The first connection wiring Lw1 has a plurality of branch lines Lb1, Lb2, Lb 3. The third connecting wiring Lw3 has a plurality of branch lines Lr1, Lr2, Lr 3.

The branch lines Lb1, Lr1 extend toward the first circuit CK1, and are electrically connected to the first circuit CK 1. The branch lines Lb2, Lr2 extend toward the second circuit CK2, and are electrically connected to the second circuit CK 2. The branch lines Lb3 and Lr3 extend toward the third circuit CK3 and are electrically connected to the third circuit CK 3.

As shown in fig. 4 and 8, the first power supply voltage Vp1a and the second power supply voltage Vp2a are input to each circuit CK. Each circuit CK is not inputted with both the first power supply voltage Vp1 and the first power supply voltage Vp1 a. Similarly, each circuit CK is not inputted with both of the second power supply voltage Vp2 and the second power supply voltage Vp2 a.

According to the display device DSP according to the first embodiment configured as described above, the display device DSP includes the resistors R1 and R2. The resistors R1 and R2 are connected to the power supply path of the signal generation circuit in the display panel PNL for the purpose of reducing the level of radiation noise (EMI) from the display panel PNL. Since the waveform of the generated drive signal Sd can be blunted, the peak current can be suppressed, and radiation noise can be reduced.

By mounting the resistors R1 and R2 on the wiring board 2, the resistors R1 and R2 can be added to the display device DSP. The resistance constant can be flexibly changed according to the required level of EMI. Therefore, the resistance value can be appropriately adjusted in consideration of the deviation from the image quality due to the waveform blunting.

As described above, the display device DSP capable of reducing radiation noise can be obtained.

(first modification of the first embodiment)

Next, a first modification of the first embodiment will be described. The display device DSP is configured in the same manner as in the first embodiment, except for the configuration described in the first modification. Fig. 9 is a plan view showing a part of the display device DSP according to the first modification, and is a diagram showing a state in which the resistor R is provided in the display panel PNL.

As shown in fig. 9, the display device DSP includes resistors R1a and R1b instead of the resistor R1 and includes resistors R2a and R2b instead of the resistor R2. In the first modification, the resistors R1a, R1b, R2a, and R2b are provided on the display panel PNL (first substrate SUB 1). The resistors R1a and R1b are located in the non-display area NDA and connected to the first connection wiring Lw1 in parallel. The resistors R2a and R2b are located in the non-display region NDA and connected in parallel to the third connection wiring Lw 3.

The resistors R1a and R1b function as first resistors, respectively. The resistors R2a and R2b function as second resistors, respectively. The number of resistors connected to the first connection line Lw1 and the third connection line Lw3 is not limited to two, and may be one or three or more.

In the wiring substrate 2, the first lead Le1 and the second lead Le2 are continuous and electrically connected. The third lead Le3 and the fourth lead Le4 are continuous and electrically connected.

Here, attention is paid to the first connection wiring Lw1 as a representative of the two connection wirings Lw. The first connection wiring Lw1 will be described together with the resistors R1a and R1 b. The same applies to the third connection wiring Lw3 and the resistors R2a and R2b, as to the first connection wiring Lw1 and the resistors R1a and R1 b. Fig. 10 is a plan view showing a part of the display panel PNL according to the first modification, and is a diagram showing a state in which the resistors R1a and R1b are connected in parallel to the first connection wiring Lw1 of the first power supply line Lp 1.

As shown in fig. 10, the resistor R1a has a first end E1 and a second end E2. The first end E1 is connected to the first connection wiring Lw1 at the first connection portion a 1. The second end E2 is connected to the first connection wiring Lw1 at a second connection portion a 2. The resistance value between the first end E1 and the second end E2 of the resistor R1a is larger than the resistance value between the first connection portion a1 and the second connection portion a2 of the first connection wiring Lw 1.

The resistor R1b has a third end E3 and a fourth end E4. The third end E3 is connected to the first connection wiring Lw1 at a third connection portion A3. The fourth end E4 is connected to the first connection wiring Lw1 at a fourth connection portion a 4. The resistance value between the third end E3 and the fourth end E4 of the resistor R1b is larger than the resistance value between the third connection portion A3 and the fourth connection portion a4 of the first connection wiring Lw 1.

In the first modification, the resistor R is a wiring. The resistance value of the material forming the resistors R1a, R1b is larger than the resistance value of the material forming the first connection wiring Lw 1.

As shown in fig. 3 and 10, the first connecting wiring Lw1 and the signal line S are formed of the same material and are located between the insulating layer 13 and the insulating layer 14. The resistors R1a and R1b and the scan line G are formed of the same material and are located between the insulating layer 12 and the insulating layer 13.

For example, the resistors R1a and R1b and the scanning line G are formed of an alloy containing Mo, such as Mo and MoW (molybdenum tungsten). The first connection wiring Lw1 and the signal line S each have a three-layer laminated structure (Ti-based/Al-based/Ti-based) including a lower layer made of a metal material containing Ti as a main component, such as Ti (titanium) or an alloy containing Ti, an intermediate layer made of a metal material containing Al as a main component, such as Al (aluminum) or an alloy containing Al, and an upper layer made of a metal material containing Ti as a main component, such as Ti or an alloy containing Ti.

As in the first modification, the resistor R may be provided on the display panel PNL (the first substrate SUB 1). In the first modification, the same effects as those of the first embodiment can be obtained. In the first modification, the connection wiring Lw and the resistor R may not be disconnected, unlike the wiring pattern shown in fig. 11 described later.

(second modification of the first embodiment)

Next, a second modification of the first embodiment will be described. The display device DSP is configured in the same manner as in the first modification described above, except for the configuration described in the second modification. Fig. 11 is a plan view showing a part of the display panel PNL according to the second modification, and is a diagram showing a state in which the first connection wiring Lw1 of the first power supply line Lp1 is disconnected and the resistor R1b is disconnected.

As shown in fig. 10, in a plan view, a part of the resistor R1a is located at a distance from the first connection wiring Lw1, and a part of the resistor R1b is located at a distance from the first connection wiring Lw 1. Therefore, the laser beam can be irradiated to at least one of the first connection line Lw1, the resistor R1a, and the resistor R1b to disconnect at least one of the first connection line Lw1, the resistor R1a, and the resistor R1 b. Further, when the laser beam is irradiated to the target wiring, the peripheral wiring is not adversely affected.

As shown in fig. 9 and 11, the first connecting line Lw1 includes a first line segment W1 and a second line segment W2. The first wiring portion W1 is electrically connected to the scan line driver circuit GD, the signal line driver circuit SD, the first circuit CK1, the second circuit CK2, and the third circuit CK 3. The second wiring portion W2 is located at a distance from the first wiring portion W1, and is electrically connected to the power supply circuit 3.

Between the first connection portion a1 and the second connection portion a2, the first connection wiring Lw1 is disconnected. In addition, the resistor R1a is not turned off. That is, the first wiring portion W1 is provided on the side where the first connection portion a1 is connected to the resistor R1a, and the second wiring portion W2 is provided on the side where the second connection portion a2 is connected to the resistor R1 a.

The resistor R1a is electrically connected between the first wiring portion W1 and the second wiring portion W2, and is connected in series to the first power line Lp1 (first connection wiring Lw 1). Therefore, the first connection portion a1 and the second connection portion a2 are electrically connected via the resistor R1 a.

Resistor R1b is open. Between the third connection portion A3 and the fourth connection portion a4, the second wiring portion W2 is not disconnected. The third connection portion A3 and the fourth connection portion a4 are connected not via the resistor R1b but via the second wiring portion W2 of the first connection wiring Lw 1.

In the second modification, since the wiring pattern shown in fig. 11 is formed, first, the first connection wiring Lw1 and the resistors R1a and R1b shown in fig. 10 are formed, and then, the laser beam is irradiated to the first connection wiring Lw1 between the first connection portion a1 and the second connection portion a2 and the resistor R1b, respectively.

However, the wiring pattern shown in fig. 11 may be formed without using a laser. For example, the first connecting line Lw1 divided into two of the first line portion W1 and the second line portion W2 may be formed in advance by adjusting the photomask, and the disconnected resistor R1b may be formed in advance. Alternatively, the first substrate SUB1 may be formed without the resistor R1 b.

Since the resistor R can be provided in the display panel PNL (the first substrate SUB1), when the level of radiation noise (EMI) is evaluated, the resistance can be adjusted by irradiating the target wiring with a laser beam. The resistance can be adjusted by irradiation of a laser beam when the level of radiation noise is evaluated, and the resistance can be adjusted by adjustment of a photomask in mass production. Since the resistor may not be mounted on the display panel PNL (the first substrate SUB1), there is an advantage that the resistance value between the power supply circuit 3 and the first electronic circuit can be adjusted without increasing the number of mounted components.

In addition, the first connecting wiring Lw1 may not be disconnected between the first connection portion a1 and the second connection portion a 2. In this case, the resistor R1a is turned off.

In addition, the first connecting wiring Lw1 may be disconnected between the third connector A3 and the fourth connector a 4. In this case, the resistor R1b is not turned off.

In the second modification, the first connection wiring Lw1 and the resistors R1a and R1b are focused on, but the same applies to the third connection wiring Lw3 and the resistors R2a and R2 b.

(third modification of the first embodiment)

Next, a third modification of the first embodiment will be described. The display device DSP is configured in the same manner as in the first modification described above, except for the configuration described in the third modification. Fig. 12 is a plan view showing a part of the display panel PNL according to the third modification, and is a diagram showing a state in which the resistors R1a and R1b are connected in parallel to the first connection wiring Lw1 of the first power supply line Lp 1.

As shown in fig. 12, various modifications are possible by means of relatively increasing the resistance value between the first end E1 and the second end E2 of the resistor R1a and relatively increasing the resistance value between the third end E3 and the fourth end E4 of the resistor R1 b. For example, the resistors R1a and R1b may be further extended by meandering the resistors R1a and R1b (wirings). For example, the length between the first end E1 and the second end E2 of the resistor R1a may be 2 times or more the length between the first connection portion a1 and the second connection portion a2 of the first connection wiring Lw 1.

In the above case, the first connecting wiring Lw1 and the resistors R1a and R1b may be formed of the same conductive material. The resistance value between the first end E1 and the second end E2 of the resistor R1a can be made larger than the resistance value between the first connection portion a1 and the second connection portion a2 of the first connection wiring Lw 1.

In the third modification, the first connection wiring Lw1 and the resistors R1a and R1b are focused on, but the same applies to the third connection wiring Lw3 and the resistors R2a and R2 b.

(second embodiment)

Next, the second embodiment will be explained. The display device DSP is configured in the same manner as in the first embodiment except for the configuration described in the second embodiment. Fig. 13 is a circuit diagram showing a display device DSP according to the second embodiment.

As shown in fig. 13, the first circuit CK1 functions as a first electronic circuit, and the scanning line driver circuit GD, the signal line driver circuit SD, the second circuit CK2, and the third circuit CK3 each function as a second electronic circuit. The display device DSP further includes a second power line Lp2 and a fourth power line Lp 4. The first power supply line Lp1 and the second power supply line Lp2 are electrically connected to the same first power supply terminal 3a of the power supply circuit 3. The third power supply line Lp3 and the fourth power supply line Lp4 are electrically connected to the same second power supply terminal 3b of the power supply circuit 3. The power supply circuit 3 applies the first power supply voltage Vp1 to the first power supply line Lp1 and the second power supply line Lp2, and applies the second power supply voltage Vp2 to the third power supply line Lp3 and the fourth power supply line Lp 4.

The first power supply line Lp1 and the third power supply line Lp3 are connected to the first circuit CK 1. The first circuit CK1 receives a first power supply voltage Vp1a via a first power supply line Lp1, and receives a second power supply voltage Vp2a via a third power supply line Lp 3.

The second power supply line Lp2 and the fourth power supply line Lp4 are connected to the scanning line driving circuit GD, the signal line driving circuit SD, the second circuit CK2, and the third circuit CK 3. The scan line driver circuit GD, the signal line driver circuit SD, the second circuit CK2, and the third circuit CK3 receive the first power supply voltage Vp1 via the second power supply line Lp2, and receive the second power supply voltage Vp2 via the fourth power supply line Lp 4.

As described above, the first power supply voltage Vp1 and the second power supply voltage Vp2 are applied to the second circuit CK2 and the third circuit CK3, respectively. The first circuit CK1 is applied with the first supply voltage Vp1a and the second supply voltage Vp2a instead of the first supply voltage Vp1 and the second supply voltage Vp 2. Therefore, the first driving signal Sd1 is resistance-adjusted.

The supply voltage Vp affects all the cells in the circuit. Therefore, when both the first power supply voltage Vp1 and the first power supply voltage Vp1a are applied to each circuit, and both the second power supply voltage Vp2 and the second power supply voltage Vp2a are applied, it is difficult to adjust the resistance of each cell. This is because the resistor R1 is added to the root of the first power line Lp1, and the resistor R2 is added to the root of the third power line Lp 3.

In the present second embodiment, the waveform of the first drive signal Sd1 is the same as that of the first embodiment shown in fig. 5, and the waveforms of the second drive signal Sd2 and the third drive signal Sd3 are the same as those of the comparative example shown in fig. 5.

The first circuit CK1 can output the first drive signal Sd1 whose resistance has been adjusted, and can contribute to reduction of radiation noise. The second circuit CK2 outputs the second drive signal Sd2 without resistance adjustment, and the third circuit CK3 outputs the third drive signal Sd3 without resistance adjustment. As described above, it may be desirable to apply the second drive signal SD2 and the third drive signal SD3, which are not resistance-adjusted, to the scanning line drive circuit GD and the signal line drive circuit SD. This enables the scanning line driving circuit GD and the signal line driving circuit SD to be driven satisfactorily.

Fig. 14 is a plan view showing the non-display region NDA of the display panel PNL, and shows a plurality of pads p and a plurality of power supply lines Lp. In the figure, the first power line Lp1 and the third power line Lp3 are diagonally provided, and the second power line Lp2 and the fourth power line Lp4 are dot-patterned.

As shown in fig. 14, the display panel PNL (the first substrate SUB1) further includes a second connection line Lw2 and a fourth connection line Lw 4.

As shown in fig. 13 and 14, the first connecting wiring Lw1 which constitutes a part of the first power line Lp1 and the third connecting wiring Lw3 which constitutes a part of the third power line Lp3 are electrically connected to the third circuit CK 3. The second connecting wiring Lw2 forms a part of the second power supply line Lp2, and is electrically connected to the circuit group (the scanning line driving circuit GD, the signal line driving circuit SD, the second circuit CK2, and the third circuit CK 3). The fourth connecting wiring Lw4 forms a part of the fourth power supply line Lp4, and is electrically connected to the circuit group (the scanning line driving circuit GD, the signal line driving circuit SD, the second circuit CK2, and the third circuit CK 3).

The second connecting wiring Lw2 is connected to the pad p1 and the pad p2 among the plurality of pads p, the fourth connecting wiring Lw4 is connected to the pad p3 and the pad p4, the first connecting wiring Lw1 is connected to the pad p5, and the third connecting wiring Lw3 is connected to the pad p 6. The first power supply voltage Vp1 and the second power supply voltage Vp2 are supplied to the connection wiring Lw through two pads p, and the first power supply voltage Vp1a and the second power supply voltage Vp2a are supplied to the connection wiring Lw through one pad p. The resistance can also be adjusted by adjusting the number of pads p connected to the connection wiring Lw.

As shown in fig. 3 and 14, in the second embodiment, the first to fourth connecting wirings Lw1 to Lw4 and the signal line S are formed of the same material and are located between the insulating layer 13 and the insulating layer 14. The resistors R1 and R2 and the scan line G are formed of the same material and are located between the insulating layer 12 and the insulating layer 13.

Fig. 15 is a plan view showing the non-display region NDA of the display panel PNL, and shows the plurality of circuits CK and the plurality of power supply lines Lp.

As shown in fig. 15, the first to fourth connecting wirings Lw1 to Lw4 extend in the non-display region NDA. The second connection wiring Lw2 has a plurality of branch lines Lb2, Lb 3. The fourth connecting wiring Lw4 has a plurality of branch lines Lr2 and Lr 3. The branch lines Lb2, Lr2 extend toward the second circuit CK2, and are electrically connected to the second circuit CK 2. The branch lines Lb3 and Lr3 extend toward the third circuit CK3 and are electrically connected to the third circuit CK 3.

The first connecting wiring Lw1 extends between the second connecting wiring Lw2 and the fourth connecting wiring Lw4, and an end portion of the first connecting wiring Lw1 extends toward the first circuit CK 1. The third connecting wiring Lw3 extends between the first connecting wiring Lw1 and the fourth connecting wiring Lw4, and an end of the third connecting wiring Lw3 extends toward the first circuit CK 1. The first connection wiring Lw1 and the third connection wiring Lw3 are electrically connected to the first circuit CK 1.

According to the display device DSP according to the second embodiment configured as described above, the display device DSP includes the resistors R1 and R2. Since the waveform of the generated first drive signal Sd1 can be blunted, the peak current can be suppressed. In the second embodiment, the display device DSP capable of reducing the radiation noise can be obtained.

The power supply lines in the display panel PNL are separated so that only desired power supply paths are resistance-adjusted in advance. Since the power supply line is not only a power supply line having a large resistance, the risk of malfunction of the circuit can be avoided.

Although the embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the present invention. These new embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the utility model. These embodiments and modifications thereof are included in the scope and gist of the utility model, and are included in the utility model described in the claims and the equivalent scope thereof.

For example, the scanning line driving circuit GD may be located on the right side of the display region DA. Alternatively, the display device DSP may further include another scanning line driving circuit GD on the right side of the display area DA. The signal line driving circuit SD may be located above the display area DA. Alternatively, the display device DSP may further include another signal line driving circuit SD above the display area DA.

A plurality of ICs including the driver IC1 may be mounted on the extended protrusion area EA of the first substrate SUB 1. In this case, the IC may have a function of the scanning line driving circuit GD or a function of the signal line driving circuit SD. The IC (for example, the driver IC1) may be mounted on the wiring substrate 2 instead of the display panel PNL (the first substrate SUB 1).

Claims (20)

1. A display device is characterized by comprising:

a display panel having a first electronic circuit and a second electronic circuit;

a first power line electrically connected to the first electronic circuit;

a second power line electrically connected to the second electronic circuit; and

a power supply circuit configured to apply a first power supply voltage to the first power supply line and the second power supply line,

a first resistor is connected to the first power line.

2. The display device according to claim 1,

the display device further includes a wiring substrate connected to the display panel,

the wiring substrate includes:

a first lead electrically connected to the first electronic circuit; and

a second lead wire located at a position spaced apart from the first lead wire, electrically connected to the power supply circuit, and constituting a part of the first power supply line together with the first lead wire,

the first resistor is a discrete resistor, is mounted on the wiring board, is electrically connected between the first lead and the second lead, and is connected to the first power supply line in series.

3. The display device according to claim 1,

the display panel further includes a first connection wiring and a second connection wiring,

the first connection wiring is electrically connected between the first electronic circuit and the power supply circuit, constituting a part of the first power supply line,

the second connection wiring is electrically connected between the second electronic circuit and the power supply circuit, and constitutes a part of the second power supply line,

the first resistor is provided on the display panel and connected to the first connection wiring in parallel.

4. The display device according to claim 3,

the first resistor has a first end connected to the first connection portion of the first connection wiring and a second end connected to the second connection portion of the first connection wiring,

a resistance value between the first end portion and the second end portion of the first resistor is larger than a resistance value between the first connection portion and the second connection portion of the first connection wiring.

5. The display device according to claim 4,

the first resistance is a wiring line and,

the resistance value of a material forming the first resistor is larger than the resistance value of a material forming the first connection wiring, and is larger than the resistance value of a material forming the second connection wiring.

6. The display device according to claim 5,

the display panel further has:

scanning a line;

a signal line;

a switching element electrically connected to the scanning line and the signal line; and

a pixel electrode electrically connected to the switching element,

the first connection wiring, the second connection wiring, and the signal line are formed of the same material,

the first resistor and the scan line are formed of the same material.

7. The display device according to claim 4,

the first resistance is a wiring line and,

a part of the first resistor is located at a position spaced apart from the first connection wiring in a plan view.

8. The display device according to claim 7,

the display panel further has:

scanning a line;

a signal line;

a switching element electrically connected to the scanning line and the signal line; and

a pixel electrode electrically connected to the switching element,

the first connection wiring, the second connection wiring, and the signal line are formed of the same material,

the first resistor and the scan line are formed of the same material.

9. The display device according to claim 3,

the first resistance is a wiring line and,

the resistance value of a material forming the first resistor is larger than the resistance value of a material forming the first connection wiring, and is larger than the resistance value of a material forming the second connection wiring.

10. The display device according to claim 9,

the display panel further has:

scanning a line;

a signal line;

a switching element electrically connected to the scanning line and the signal line; and

a pixel electrode electrically connected to the switching element,

the first connection wiring, the second connection wiring, and the signal line are formed of the same material,

the first resistor and the scan line are formed of the same material.

11. The display device according to claim 3,

the first resistance is a wiring line and,

a part of the first resistor is located at a position spaced apart from the first connection wiring in a plan view.

12. The display device according to claim 11,

the display panel further has:

scanning a line;

a signal line;

a switching element electrically connected to the scanning line and the signal line; and

a pixel electrode electrically connected to the switching element,

the first connection wiring, the second connection wiring, and the signal line are formed of the same material,

the first resistor and the scan line are formed of the same material.

13. The display device according to claim 1,

the display panel further includes a first connection wiring and a second connection wiring,

the first connecting wiring has:

a first wiring portion electrically connected to the first electronic circuit; and

a second wiring portion located at a distance from the first wiring portion and electrically connected to the power supply circuit,

the second connection wiring is electrically connected between the second electronic circuit and the power supply circuit, and constitutes a part of the second power supply line,

the first resistor is provided on the display panel, electrically connected between the first wiring portion and the second wiring portion, and connected to the first power line in series.

14. The display device according to claim 13,

the first resistance is a wiring line and,

the resistance value of a material forming the first resistor is larger than the resistance value of a material forming the first connection wiring, and is larger than the resistance value of a material forming the second connection wiring.

15. The display device according to claim 14,

the display panel further has:

scanning a line;

a signal line;

a switching element electrically connected to the scanning line and the signal line; and

a pixel electrode electrically connected to the switching element,

the first connection wiring, the second connection wiring, and the signal line are formed of the same material,

the first resistor and the scan line are formed of the same material.

16. The display device according to claim 13,

the first resistance is a wiring line and,

a part of the first resistor is located at a position spaced apart from the first connection wiring in a plan view.

17. The display device according to claim 16,

the display panel further has:

scanning a line;

a signal line;

a switching element electrically connected to the scanning line and the signal line; and

a pixel electrode electrically connected to the switching element,

the first connection wiring, the second connection wiring, and the signal line are formed of the same material,

the first resistor and the scan line are formed of the same material.

18. The display device according to claim 1,

the first power line and the second power line are electrically connected to the same first power terminal of the power circuit.

19. The display device according to claim 1,

the display device further includes:

a third power line electrically connected to the first electronic circuit;

a fourth power line electrically connected to the second electronic circuit; and

a second resistor connected to the third power supply line,

the power supply circuit applies a second power supply voltage different from the first power supply voltage to the third power supply line and the fourth power supply line.

20. The display device according to claim 19,

the voltage level of the second power supply voltage is lower than the voltage level of the first power supply voltage.

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