CN215733583U

CN215733583U - High-performance anti-reverse circuit suitable for various acquisition chips

Info

Publication number: CN215733583U
Application number: CN202121950152.XU
Authority: CN
Inventors: 范耀辉; 刘壮
Original assignee: Hengda Haila Electronics Yangzhou Co ltd
Current assignee: Hella Shanghai Electronics Co Ltd
Priority date: 2021-08-19
Filing date: 2021-08-19
Publication date: 2022-02-01
Anticipated expiration: 2031-08-19

Abstract

The utility model discloses a high-performance anti-reverse circuit suitable for various acquisition chips, which belongs to the technical field of battery management systems and comprises the following components: an AFE chip; a field effect transistor Q2, in which the gate of the field effect transistor Q2 is connected to the VREG pin of the AFE chip, and the source of the field effect transistor Q2 is connected to the GND ground; a diode D1, the cathode of the diode D1 being connected to the drain of the field effect transistor Q2; the drain electrode of the field effect transistor Q1 and the drain electrode of the field effect transistor Q1 are connected with the V + positive electrode end of the battery cell module; the resistor R1 is connected to the gate and source of the field effect transistor Q1, the gate of the field effect transistor Q1 is connected to the input terminal of the resistor R2, and the output terminal of the resistor R2 is connected to the anode of the diode D1. The utility model adopts the design that the positive electrode is blocked and the negative electrode is sparse, and can effectively avoid the adverse effect of reverse current generated by hot plugging phenomenon in the production and operation of the battery system on the whole battery system.

Description

High-performance anti-reverse circuit suitable for various acquisition chips

Technical Field

The utility model relates to the technical field of battery management systems, in particular to a high-performance anti-reverse circuit suitable for various acquisition chips.

Background

Along with the rapid development of new energy automobiles and energy storage industries, batteries are widely applied to traditional electronic products, on one hand, the capacity of the batteries and the scale of a single system are continuously improved, and on the other hand, not all manufacturers have a standard and sound operation system.

The prior art has the following problems:

for example, the acquisition line is connected in a wrong order and is manufactured in a charged manner, and the like, reverse current can be generated, so that the acquisition equipment of the slave machine is damaged in different degrees, and a wire harness and even a battery pack are seriously burnt.

SUMMERY OF THE UTILITY MODEL

1. Technical problem to be solved

Aiming at the problems in the prior art, the utility model aims to provide a high-performance anti-reverse circuit suitable for various acquisition chips. The utility model adopts the design that the positive electrode is blocked and the negative electrode is sparse, and can effectively avoid the adverse effect of reverse current generated by hot plugging phenomenon in the production and operation of the battery system on the whole battery system.

2. Technical scheme

In order to solve the problems, the utility model adopts the following technical scheme:

a high performance anti-kickback circuit suitable for use with multiple acquisition chips, comprising:

an AFE chip;

a field effect transistor Q2, a gate of the field effect transistor Q2 is connected to the VREG pin of the AFE chip, and a source of the field effect transistor Q2 is connected to GND ground;

a diode D1, a cathode of the diode D1 being connected to a drain of a field effect transistor Q2;

the drain electrode of the field effect transistor Q1 is connected with the V + positive electrode end of the battery cell module;

a resistor R2, wherein the gate of the field effect transistor Q1 is connected with the input end of a resistor R2, and the output end of the resistor R2 is connected with the anode of a diode D1;

the resistor R1, the resistor R1 is connected with the grid and the source of the field effect transistor Q1, and the output end of the resistor R1 is connected with the input end of the resistor R2; and

and a diode D2, wherein the V-cathode end of the AFE chip is respectively connected with a GND ground end and the anode of the diode D2, and the cathode of the diode D2 is connected with a pin C1 of the AFE chip. The utility model adopts the design that the positive electrode is blocked and the negative electrode is sparse, and can effectively avoid the adverse effect of reverse current generated by hot plugging phenomenon in the production and operation of the battery system on the whole battery system.

In a preferred embodiment of the present invention, the field effect transistor Q1 is a PMOS transistor.

In a preferred embodiment of the present invention, the field effect transistor Q2 is an NMOS transistor.

As a preferable aspect of the present invention, the present invention further includes:

and a transistor Q3, wherein the source of the field effect transistor Q1 is connected with the collector of the transistor Q3, the emitter of the transistor Q3 outputs VREG level and is connected with the VREG pin of the AFE chip, and the base of the transistor Q3 is connected with the DRIVE pin of the AFE chip.

As a preferable embodiment of the present invention, the transistor Q3 is an NPN transistor.

the negative electrode of the battery pack C1 is connected with the V-negative electrode end of the AFE chip, and the positive electrode of the battery pack C1 is connected with a C1 pin of the AFE chip; and

and the positive electrode of the battery pack C1 is also connected with the negative electrode of the battery pack C2, and the positive electrode of the battery pack C2 is connected with a pin C2 of the AFE chip.

In a preferred embodiment of the present invention, the AFE chip is an ADBMS6830M type chip.

3. Advantageous effects

Compared with the prior art, the utility model has the advantages that:

(1) the input end of the V + positive terminal of the AFE chip adopts a field effect transistor Q1, a field effect transistor Q1 is a PMOS tube, and the grid electrode of the field effect transistor Q1 can be controlled by a power supply generated by an NPN type triode Q3 to work in the forward direction and cut off in the reverse direction.

(2) In the utility model, the diode D2 is adopted at the V-negative electrode end of the AFE chip to guide the forward pulse to the V + positive electrode end of the AFE chip, and the forward pulse is absorbed by the battery cell.

(3) The utility model mainly aims at an AFE chip which is provided by manufacturers such as TI, NXP and ADI and adopts an external NPN triode Q3 as a linear voltage regulator for power supply.

(4) The utility model has simple circuit, is suitable for the mainstream AFE acquisition scheme in the market, has strong practicability and saves cost.

(5) Compared with an anti-reverse diode, the circuit can save power consumption.

(6) The circuit of the utility model can effectively avoid the impact of reverse current generated by the connector in hot plugging on the AFE chip.

(7) The circuit can effectively prevent the AFE chip from being damaged due to reverse voltage in the reverse connection of the battery bus.

Drawings

Fig. 1 is a circuit schematic diagram of a high-performance anti-reverse circuit suitable for various acquisition chips.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and all other embodiments obtained by those skilled in the art without any inventive work are within the scope of the present invention.

In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "outer", "top/bottom", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "disposed," "sleeved/connected," "connected," and the like are to be construed broadly, e.g., "connected," which may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Example (b):

referring to fig. 1, a high performance anti-reverse circuit for multiple acquisition chips includes:

the AFE chip is preferably ADBMS6830M type;

a field effect transistor Q2, in which the gate of the field effect transistor Q2 is connected to the VREG pin of the AFE chip, the source of the field effect transistor Q2 is connected to the GND ground, and preferably, the field effect transistor Q2 is an NMOS transistor;

a diode D1, wherein the cathode of the diode D1 is connected to the drain of the field effect transistor Q2, preferably, the diode D1 is an anti-reverse diode;

the drain electrode of the field effect transistor Q1 and the drain electrode of the field effect transistor Q1 are connected with the V + positive electrode end of the cell module, preferably, the field effect transistor Q1 is a PMOS transistor;

a resistor R2, wherein the gate of the field effect transistor Q1 is connected with the input end of the resistor R2, and the output end of the resistor R2 is connected with the anode of the diode D1;

the resistor R1, the resistor R1 is connected with the grid and the source of the field effect transistor Q1, the output end of the resistor R1 is connected with the input end of the resistor R2;

a diode D2, wherein the V-cathode terminal of the AFE chip is respectively connected with the GND ground terminal and the anode of the diode D2, the cathode of the diode D2 is connected with the C1 pin of the AFE chip, and preferably, the diode D2 is an anti-reverse diode;

a triode Q3, wherein the source of a field effect transistor Q1 is connected with the collector of a triode Q3, the emitter of the triode Q3 outputs VREG level and is connected with the VREG pin of the AFE chip, the base of the triode Q3 is connected with the DRIVE pin of the AFE chip, and preferably, the triode Q3 is an NPN type triode;

the negative electrode of the battery pack C1 is connected with the V-negative electrode end of the AFE chip, and the positive electrode of the battery pack C1 is connected with a C1 pin of the AFE chip;

the positive electrode of the battery pack C2 is also connected with the negative electrode of the battery pack C2, and the positive electrode of the battery pack C2 is connected with a pin C2 of the AFE chip;

the working principle or working process of the utility model is as follows:

in a normal operating state, the V + positive terminal input to the AFE chip is supplied through the body diode in the field effect transistor Q1, so that the DRIVE pin of the AFE chip can output a high level, the transistor Q3 is driven to output a level VREG, the VREG pin of the AFE chip DRIVEs the field effect transistor Q2 to be pulled down to the ground, the source of the field effect transistor Q1 is pulled down to the ground, the voltage VGS applied to the resistor R1 is smaller than a conduction value through the voltage division of the resistor R1 and the terminal R2, the drain and the source are driven to be close to be conducted, so that a forward current flows through the field effect transistor Q1, the conduction loss is reduced, and the diode D2 does not work under normal operation;

the abnormal state is that when hot plug occurs and the V + positive terminal input to the AFE chip and the V-negative terminal input to the AFE chip are reversely connected, the current entering from the V + positive terminal input to the AFE chip is negative current, the current entering from the V-negative terminal input to the AFE chip is positive current, and the body diode in the field effect transistor Q1 is a forward diode, so the body diode in the field effect transistor Q1 cannot pass through, so the V + positive terminal input to the AFE chip is not supplied with power, the DRIVE pin of the AFE chip is not output, and the level VREG does not pull down the field effect transistor Q3 to the ground, so the whole field effect transistor does not work; the reverse level entering from the V-cathode end of the AFE chip is high level, and reaches the cathode of the anti-reflection diode D1 through the body diode in the field effect transistor Q2, and is cut off at the cathode, so the field effect transistor Q1 cannot be driven, because the internal resistance of the sampling circuit of the AFE chip is far greater than the resistance of the high level entering from the V-cathode end of the AFE chip reaching the battery pack C1 through the diode D2, the reverse surge generated at the moment of unplugging or inserting the connector reaches the anode of the battery pack C1 through the diode D2, at this moment, the battery pack C1 can be regarded as a super large capacitor, the surge current flowing into the battery pack C1 is basically ignored, and the high level entering from the V-cathode end of the AFE chip can be effectively prevented from directly impacting the ground GND of the AFE chip to damage the AFE chip and peripheral circuits.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the equivalent replacement or change according to the technical solution and the modified concept of the present invention should be covered by the scope of the present invention.

Claims

1. A high-performance anti-reverse circuit suitable for various acquisition chips is characterized by comprising:

an AFE chip;

and a diode D2, wherein the V-cathode end of the AFE chip is respectively connected with a GND ground end and the anode of the diode D2, and the cathode of the diode D2 is connected with a pin C1 of the AFE chip.

2. The high-performance anti-reverse circuit applicable to various acquisition chips as claimed in claim 1, wherein said field effect transistor Q1 is a PMOS transistor.

3. The high-performance anti-reverse circuit for multiple acquisition chips according to claim 2, wherein said field effect transistor Q2 is an NMOS transistor.

4. The high-performance anti-reverse circuit applicable to various acquisition chips according to claim 3, further comprising:

5. The high-performance anti-reverse circuit applicable to various acquisition chips as claimed in claim 4, wherein the transistor Q3 is an NPN transistor.

6. The high-performance anti-reverse circuit applicable to various acquisition chips according to claim 5, further comprising:

7. A high performance anti-reverse circuit for multiple acquisition chips according to any one of claims 1-6, wherein said AFE chip is ADBMS6830M type.

8. The high-performance anti-reverse circuit applicable to various acquisition chips according to claim 7, wherein the diode D1 and the diode D2 are anti-reverse diodes.