CN215731733U - Display substrate and display panel - Google Patents

Abstract

The application provides a display substrate and a display panel, which relate to the technical field of display, wherein the display substrate comprises a substrate, and a light shielding layer and at least one transistor which are positioned on the substrate; the transistor comprises an active layer, a first pole and a second pole, wherein the first pole and the second pole are positioned on one side of the active layer, which is far away from the substrate; the active layer overlaps with a region between the first pole and the second pole in a direction perpendicular to the substrate; wherein the light shielding layer is positioned on one side of the transistor far away from the substrate, and the light shielding layer at least overlaps with the region between the first pole and the second pole along the direction vertical to the substrate; the transistor in the display substrate has good negative bias temperature illumination stability, and the display panel prepared by the display substrate has good display effect.

Description

Display substrate and display panel

Technical Field

The application relates to the technical field of display, in particular to a display substrate and a display panel.

Background

The Oxide thin film transistor (Oxide TFT) has great potential advantages and application prospects in the technical field of display by virtue of the advantages of high mobility, good film forming uniformity, low preparation process temperature and the like. However, the current oxide thin film transistor has poor NBTIS (Negative Bias Temperature Illumination Stability) performance, which causes the display panel prepared by the oxide thin film transistor to have the problem of display unevenness, and reduces the display effect.

At present, it is desirable to provide a new display substrate to solve the above problems.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a display substrate and a display panel, wherein a transistor in the display substrate has good negative bias temperature illumination stability, and the display panel prepared by the display substrate has a good display effect.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

in one aspect, a display substrate is provided, which includes a substrate, and a light-shielding layer and at least one transistor on the substrate;

the transistor comprises an active layer, a first pole and a second pole, wherein the first pole and the second pole are positioned on one side of the active layer, which is far away from the substrate; the active layer overlaps with a region between the first pole and the second pole in a direction perpendicular to the substrate;

the light shielding layer is positioned on one side of the transistor far away from the substrate, and the light shielding layer at least overlaps with the region between the first pole and the second pole in the direction perpendicular to the substrate.

Optionally, an orthographic projection of the light shielding layer on the substrate further overlaps with an orthographic projection of the first pole on the substrate;

and/or the orthographic projection of the light shielding layer on the substrate is partially overlapped with the orthographic projection of the second pole on the substrate.

Optionally, the light shielding layer is located between the first pole and the second pole, and the light shielding layer is insulated from the first pole and the second pole, respectively.

Optionally, the display substrate includes an interlayer dielectric layer and a plurality of transistors, the interlayer dielectric layer covers the active layer of each transistor, and the interlayer dielectric layer is located between the first electrode of each transistor and the substrate;

the interlayer dielectric layer also extends to the region except the region where the transistor is located, and the shading layer also covers the interlayer dielectric layer except the region where the transistor is located.

Optionally, the display substrate further includes a light-emitting functional layer, the light-emitting functional layer is located on a side of the light-shielding layer away from the substrate, and the light-emitting functional layer includes a plurality of light-emitting functional portions;

wherein the light-shielding layer located outside the region where the transistor is located overlaps with the light-emitting functional portion in a direction perpendicular to the substrate.

Optionally, the display substrate further includes a planarization layer covering each of the transistors;

the light shielding layer is positioned on one side of the flat layer far away from the substrate.

Optionally, the display substrate includes a plurality of transistors and a plurality of first electrodes, each of the first electrodes is located on a side of the planarization layer away from the substrate, and two adjacent first electrodes are disposed at an interval;

the shading layer is located in a region between two adjacent first electrodes, and the shading layer is insulated from the first electrodes.

Optionally, an orthographic projection of the light shielding layer in a direction perpendicular to the substrate partially overlaps an orthographic projection of the first electrode in a direction perpendicular to the substrate.

Optionally, a portion of the first electrode overlapping with the light shielding layer in a direction perpendicular to the substrate is located on a side of the light shielding layer away from the substrate.

Optionally, a portion of the light shielding layer overlapping with the first electrode in a direction perpendicular to the substrate is located on a side of the first electrode away from the substrate.

Optionally, the display substrate further includes a pixel defining layer, a plurality of light emitting functional portions, and a second electrode covering each of the light emitting functional portions;

the pixel defining layer is provided with a plurality of openings, the light-emitting functional part is at least positioned in the openings, and the light-emitting functional part is positioned between the first electrode and the second electrode.

In another aspect, a display panel is provided, which includes the display substrate as described above.

The embodiment of the application provides a display substrate and a display panel, wherein the display substrate comprises a substrate, and a light shielding layer and at least one transistor which are positioned on the substrate; the transistor comprises an active layer, a first pole and a second pole, wherein the first pole and the second pole are positioned on one side of the active layer, which is far away from the substrate; the active layer overlaps with a region between the first and second poles in a direction perpendicular to the substrate; the light shielding layer is positioned on one side of the transistor far away from the substrate, and the light shielding layer at least overlaps with the region between the first pole and the second pole in the direction perpendicular to the substrate.

In this way, the light shielding layer is arranged to be at least overlapped with the area between the first pole and the second pole in the direction perpendicular to the substrate, and the active layer is overlapped with the area between the first pole and the second pole in the direction perpendicular to the substrate, so that the light shielding layer shields the part of the active layer which is not covered by the first pole and the second pole, light is prevented from being emitted to the active layer from the area between the first pole and the second pole, the influence of the light on the stability of the active layer is avoided, the NBTIS performance of the transistor in the display substrate is improved, and further, the display effect of the display panel prepared by the display substrate is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or related technologies of the present application, the drawings needed to be used in the description of the embodiments or related technologies are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display substrate in the related art according to an embodiment of the present application;

fig. 2-8 are schematic structural diagrams of eight different display substrates according to embodiments of the present disclosure;

fig. 9 is a schematic flowchart of a method for manufacturing a display substrate according to an embodiment of the present disclosure;

fig. 10 to 16 are schematic intermediate structures of a display substrate according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Oxide thin film transistors (Oxide TFTs) are sensitive to voltage, stress, temperature and light. In practical applications, the threshold voltage (Vth) of the transistor usually generates a negative bias under the condition of negative bias temperature illumination, so that Vth variations of the transistor in different regions of the display substrate are inconsistent, and a display panel manufactured by the display substrate has a problem of uneven display screen brightness (Mura).

Referring to fig. 1, a display substrate in the related art is provided, and for the transistor 100, on one hand, ambient light can be directly emitted from the light emitting side of the display substrate onto the transistor 100 in the display substrate; on the other hand, since the display substrate is an OLED (Organic Light-Emitting Diode) display substrate, Light emitted from a Light-Emitting functional layer 101 in the display substrate is reflected by a cathode 102 and then also irradiates a transistor 100 in the display substrate; on the other hand, the light emitted from the light-emitting functional layer 101 may also pass through various layers in the display panel to enter the glass substrate 103, and then be reflected from the glass substrate 103 to the transistor 100. Thus, the NBTIS performance of the transistor is severely reduced due to the irradiation of light, and the problem of uneven display of the picture of the display panel prepared by the display substrate is caused.

To this end, embodiments of the present application provide a display substrate, as shown with reference to fig. 2, 4 or 6, including a substrate 1, and a light-shielding layer 12 and at least one transistor 9 on the substrate 1; the transistor 9 comprises an active layer 93, and a first pole 91 and a second pole 92 located on a side of the active layer 93 remote from the substrate 1; the active layer 93 overlaps with a region between the first and second poles 91 and 92 in a direction perpendicular to the substrate 1;

wherein the light-shielding layer 12 is located on a side of the transistor 9 away from the substrate 1, and the light-shielding layer 12 overlaps at least a region between the first pole 91 and the second pole 92 in a direction perpendicular to the substrate 1.

Here, the specific material of the light-shielding layer 12 is not limited. Specifically, the material of the light shielding layer 12 may be a light-shielding non-conductive material, such as: metal oxides such as MoO, CuO, MnO2, or light-shielding conductive materials such as: cu, Mo, Al, Mg, etc. When the light-shielding layer 12 is made of a light-shielding conductive material, an insulating layer needs to be provided between the light-shielding layer 12 and another conductive film layer when the light-shielding layer 12 is provided at a position adjacent to the other conductive film layer. In all the embodiments of the present application, the material of the light-shielding layer 12 is a light-shielding non-conductive material.

The above light-shielding layer 12 overlaps at least the region between the first and second poles 91 and 92 in the direction perpendicular to the substrate 1 to mean: as shown in fig. 2, the light shielding layer 12 overlaps only the region between the first and second poles 91 and 92 in the direction perpendicular to the substrate 1; alternatively, as shown in fig. 4 and 6, the light shielding layer 12 overlaps with a region between the first and second poles 91 and 92 in a direction perpendicular to the substrate 1, and also overlaps with the first and/or second poles 91 and 92, respectively, in a direction perpendicular to the substrate 1. It should be noted that, for the structure shown in fig. 6, the light shielding layer 12 may also be retracted so that the light shielding layer 12 overlaps only the region between the first pole 91 and the second pole 92 in the direction perpendicular to the substrate 1, and for this case, the embodiment of the present application is not drawn.

The transistor 9 may be a thin film transistor; specifically, the Oxide thin film transistor (Oxide TFT) may be used, or a hydrogenated amorphous silicon thin film transistor (a-Si: H TFT) may be used, or a low temperature polysilicon thin film transistor (LTPS TFT) may be used. The above-mentioned oxide, hydrogenated amorphous silicon, and low-temperature polysilicon are all limitations on the material of the active layer of the thin film transistor. The embodiments of the present application are described using the above transistors as oxide thin film transistors as examples.

The first pole of the transistor can be a source electrode, and the second pole can be a drain electrode; alternatively, the first pole may be a drain and the second pole may be a source; the specific design may be determined according to the actual design of the display substrate, and is not limited herein.

The transistor may be a bottom gate transistor or a top gate transistor. Here, the embodiments of the present application are described by taking the above-described transistor as an example of a top gate transistor, without limitation.

The specific type of the display substrate is not limited herein. Specifically, the Display substrate may be an OLED Display substrate, an LCD (Liquid Crystal Display) Display substrate, or a Mini/Micro-LED Micro-Display substrate. The embodiments of the present application are all described by taking the above display substrate as an OLED display substrate.

Embodiments of the present application provide a display substrate comprising a substrate 1 and a light-shielding layer 12 and at least one transistor 9 located on the substrate 1; the transistor 9 comprises an active layer 93, and a first pole 91 and a second pole 92 located on a side of the active layer 93 remote from the substrate 1; the active layer 93 overlaps with a region between the first and second poles 91 and 92 in a direction perpendicular to the substrate 1; wherein the light-shielding layer 12 is located on a side of the transistor 9 away from the substrate 1, and the light-shielding layer 12 overlaps at least a region between the first pole 91 and the second pole 92 in a direction perpendicular to the substrate 1.

In this way, by arranging the light shielding layer 12 to overlap at least the region between the first pole 91 and the second pole 92 in the direction perpendicular to the substrate 1, and arranging the active layer 93 to overlap the region between the first pole 91 and the second pole 92 in the direction perpendicular to the substrate 1, the light shielding layer 12 shields the part of the active layer 93 not covered by the first pole 91 and the second pole 92, so that ambient light (such as the light 1 shown in fig. 2) is prevented from being incident on the active layer 93 from the region between the first pole 91 and the second pole 92, the influence of the ambient light on the stability of the active layer 93 is prevented, the NBTIS performance of the transistor 9 in the display substrate is improved, and further, the display effect of the display panel prepared from the display substrate is improved.

In addition, through setting up the light shield layer, can effectively reduce display substrate, the reflectivity, reach or be close to the level that the display substrate of traditional setting polaroid was reflective, promoted the display panel's of display substrate preparation display effect.

Alternatively, referring to fig. 4 or fig. 6, the orthographic projection of the light shielding layer 12 on the substrate 1 also overlaps with the orthographic projection of the first electrode 91 on the substrate 1; and/or the orthographic projection of the light shielding layer 12 on the substrate 1 is partially overlapped with the orthographic projection of the second pole 92 on the substrate 1.

Specifically, three cases are distinguished:

the first case is: the light shielding layer 12 overlaps with a region between the first and second poles 91 and 92 in a direction perpendicular to the substrate 1, and an orthographic projection of the light shielding layer 12 on the substrate 1 also partially overlaps with an orthographic projection of the first pole 91 on the substrate 1.

The second case is: the light shielding layer 12 overlaps with a region between the first and second poles 91 and 92 in a direction perpendicular to the substrate 1, and an orthographic projection of the light shielding layer 12 on the substrate 1 also partially overlaps with an orthographic projection of the second pole 92 on the substrate 1.

The third case is: the light shielding layer 12 overlaps with a region between the first and second poles 91 and 92 in a direction perpendicular to the substrate 1, an orthogonal projection of the light shielding layer 12 on the substrate 1 also overlaps with an orthogonal projection of the first pole 91 on the substrate 1, and an orthogonal projection of the light shielding layer 12 on the substrate 1 also overlaps with an orthogonal projection of the second pole 92 on the substrate 1.

In practical applications, when the orthographic projection of the light shielding layer 12 on the substrate 1 further overlaps the orthographic projection of the first electrode 91 on the substrate 1, and/or the orthographic projection of the light shielding layer 12 on the substrate 1 further overlaps the orthographic projection of the second electrode 92 on the substrate 1, the light shielding layer 12 is enabled to shield a part of the active layer 93 not covered by the first electrode 91 and the second electrode 92, and since the light shielding layer 12 is partially overlapped with the first electrode 91 and/or the second electrode 92 in a direction perpendicular to the substrate 1, ambient light is prevented from leaking out from a region between the first electrode 91 and the light shielding layer 12 and/or a region between the second electrode 92 and the light shielding layer 12 and then being incident on the active layer 93, so as to further improve the light shielding effect, avoid the influence of ambient light (such as the light 1 shown in fig. 4) on the stability of the active layer 93, and further improve the NBTIS performance of the transistor 9 in the display substrate, furthermore, the display effect of the display panel prepared by the display substrate is improved.

Alternatively, referring to fig. 2, the light shielding layer 12 is located between the first pole 91 and the second pole 92, and the light shielding layer 12 is insulated from the first pole 91 and the second pole 92, respectively.

It should be noted that, because the light shielding layer 12 is located between the first electrode 91 and the second electrode 92, and two ends of the light shielding layer 12 are respectively connected to the first electrode 91 and the second electrode 92, the material of the light shielding layer 12 may be a non-conductive material in order not to affect the electrical properties of the first electrode 91 and the second electrode 92 of the transistor 9; alternatively, when the light-shielding layer 12 is made of a conductive material, an insulating layer needs to be provided between the light-shielding layer 12 and the first electrode 91 and between the light-shielding layer 12 and the second electrode 92.

In the display substrate provided by the embodiment of the application, the light shielding layer 12 is disposed between the first pole 91 and the second pole 92, so that the light shielding layer 12 shields a part of the active layer 93 which is not covered by the first pole 91 and the second pole 92, light is prevented from being incident on the active layer 93, and influence of ambient light (such as light 1 shown in fig. 2) on stability of the active layer 93 is avoided, thereby enhancing tinbs performance of the transistor 9 in the display substrate, and further, enhancing display effect of the display panel prepared by the display substrate.

In addition, the non-conductive shading layer is arranged in the original product design, so that the negative influence on the existing circuit design can not be generated, and the design of other structures in the existing product is not required to be changed.

Alternatively, referring to fig. 3, the display substrate includes an interlayer dielectric layer 5 and a plurality of transistors 9, the interlayer dielectric layer 5 covers the active layer 93 of each transistor 9, and the interlayer dielectric layer 5 is located between the first electrode 91 of each transistor 9 and the substrate 1;

the interlayer dielectric layer 5 also extends to the region except the region where the transistor 9 is located, and the shading layer 12 also covers the interlayer dielectric layer 5 except the region where the transistor 9 is located.

It should be noted that, under the condition that the first pole 91 and the second pole 92 of the transistor 9 are made of metal materials, the light shielding layer 12 is arranged to cover the interlayer dielectric layer 5 except the region where the transistor 9 is located, so that the light shielding layer 12 and the first pole 91 and the second pole 92 of each transistor 9 together form an overall light shielding film layer, thereby simultaneously shielding ambient light and light emitted by the light emitting function part, and playing a better role in shielding the active layer 93, further improving the NBTIS performance of the transistor 9 in the display substrate, and improving the display effect of the display panel prepared by the display substrate.

Further, the display substrate further comprises a light-emitting function layer, the light-emitting function layer is located on one side of the light shielding layer 12 far away from the substrate 1, and the light-emitting function layer comprises a plurality of light-emitting function portions 10;

wherein the light-shielding layer 12 located outside the region where the transistor 9 is located overlaps the light-emitting functional portion 10 in the direction perpendicular to the substrate 1.

In the display substrate provided by the embodiment of the present application, by providing the light shielding layer 12 on the interlayer dielectric layer 5 except for the region where the transistor 9 is located, and since the light shielding layer 12 located outside the region where the transistor 9 is located overlaps with the light emitting function portion 10 in the direction perpendicular to the substrate 1; thus, the light-shielding layer 12 shields the part of the active layer 93 not covered by the first electrode 91 and the second electrode 92, so as to prevent ambient light (such as light 1 shown in fig. 3) from entering the active layer 93, and prevent light (such as light 2 shown in fig. 3) emitted by the light-emitting functional portion 10 from being reflected by the second electrode 8 (cathode) and then striking the active layer 93, and also prevent light (such as light 3 shown in fig. 3) emitted by the light-emitting functional portion 10 from entering the substrate 1 and then striking the active layer 93 through reflection, thereby largely preventing the ambient light or light emitted by the light-emitting functional portion from affecting the stability of the active layer 93, further improving the NBTIS performance of the transistor 9 in the display substrate, and further improving the display effect of the display panel manufactured by the display substrate.

Further alternatively, referring to fig. 5, in the case that the interlayer dielectric layer 5 further extends to a region other than the region where the transistor 9 is located, and the light shielding layer 12 further covers the interlayer dielectric layer 5 other than the region where the transistor 9 is located, two ends of the light shielding layer 12 further extend to the first pole 91 and the second pole 92 adjacent thereto. Thus, it is avoided that the ambient light or the light emitted by the light emitting function portion 10 leaks from the gap between the first electrode 91 and the light shielding layer 12 and the gap between the second electrode 92 and the light shielding layer 12 (the gap is caused by a process error and does not actually exist), and then is incident on the active layer 93, so that the light shielding effect is further improved, the NBTIS performance of the transistor 9 in the display substrate is further improved, and further, the display effect of the display panel manufactured by the display substrate is also improved.

Optionally, referring to fig. 6, the display substrate further includes a planarization layer 6, and the planarization layer 6 covers each transistor 9; wherein, the shading layer 12 is positioned on the side of the flat layer 6 far away from the substrate 1.

In the display substrate provided in the embodiment of the present application, by disposing the light shielding layer 12 on the side of the flat layer 6 away from the substrate 1, the light shielding layer 12 overlaps at least the region between the first pole 91 and the second pole 92 in the direction perpendicular to the substrate 1, and the active layer 93 overlaps the region between the first pole 91 and the second pole 92 in the direction perpendicular to the substrate 1, so that the light shielding layer 12 shields the portion of the active layer 93 not covered by the first pole 91 and the second pole 92, and prevents ambient light (such as the light 1 shown in fig. 6) from being incident on the active layer 93 from the region between the first pole 91 and the second pole 92, thereby preventing the ambient light from affecting the stability of the active layer 93, further improving the NBTIS performance of the transistor 9 in the display substrate, and further improving the display effect of the display panel manufactured by the display substrate.

Alternatively, referring to fig. 7, the display substrate includes a plurality of transistors 9 and a plurality of first electrodes 11, each first electrode 11 is located on a side of the planarization layer 6 away from the substrate 1, and two adjacent first electrodes 11 are disposed at intervals; the light shielding layer 12 is located in a region between two adjacent first electrodes 11, and the light shielding layer 12 is insulated from the first electrodes 11.

The first electrode may be an anode, and the anode may include a sublayer, such as: an ITO layer; alternatively, the anode may include three sublayers, for example, including an ITO layer, an Ag layer, and an ITO layer, which are stacked.

Under the condition that above-mentioned first electrode includes the ITO layer, the three sublayer in Ag layer and ITO layer, because the Ag layer is light tight layer, also have the shading effect, then, regional setting light shield 12 between two adjacent first electrodes 11, make light shield 12 and first electrode 11 constitute holistic shading rete jointly, thereby can shelter from the light that ambient light and luminous function portion sent simultaneously, play better effect of sheltering from to active layer 93, and then improved the NBTIS performance of transistor 9 in the display substrate, the display panel's that has improved by this display substrate preparation display effect.

Alternatively, referring to fig. 8, an orthographic projection of the light shielding layer 12 in a direction perpendicular to the substrate 1 partially overlaps with an orthographic projection of the first electrode 11 in a direction perpendicular to the substrate 1.

Specifically, the overlapping of the orthographic projection of the light shielding layer 12 in the direction perpendicular to the substrate 1 and the orthographic projection of the first electrode 11 in the direction perpendicular to the substrate 1 is divided into two cases:

the first case is: referring to fig. 8, a portion of the first electrode 11 overlapping the light shielding layer 12 in a direction perpendicular to the substrate 1 is located on a side of the light shielding layer 12 away from the substrate 1.

The second case is: a part of the light shielding layer 12 overlapping the first electrode 11 in a direction perpendicular to the substrate 1 is located on a side of the first electrode 11 away from the substrate 1.

In both cases, whether both end portions of the first electrode 11 cover the light shielding layer 12 or both end portions of the light shielding layer 12 cover the first electrode 11, it is possible to prevent the ambient light or the light emitted from the light-emitting functional portion from leaking from a gap that may exist between the light shielding layer 12 and the first electrode 11 (the gap is caused by a process error and does not necessarily exist actually), and to perform a further light shielding function.

Alternatively, as shown with reference to fig. 8, the display substrate further includes a Pixel Defining Layer (PDL)7, a plurality of light emitting functional sections 10, and a second electrode 8 covering each of the light emitting functional sections 10; the pixel defining layer 7 has a plurality of openings, the light emitting functional portion 10 is at least located in the openings, and the light emitting functional portion 10 is located between the first electrode 11 and the second electrode 8. The second electrode can be a cathode, and the cathode is made of magnesium-silver alloy.

In order to better improve the light shielding effect of the display substrate on the active layer 93 of the transistor 9, the Planarization Layer (PLN) and the Pixel Definition Layer (PDL) may be set to be black, for example, made of black organic material.

In practical applications, the display substrate further includes the organic layer 2, the buffer layer 3, and the gate insulating layer 4 as shown in fig. 8, the transistor 9 further includes the gate electrode 96, the source contact layer 94, and the drain contact layer 95 (or the source contact layer 95 and the drain contact layer 94), and of course, the display substrate further includes other structures and film layers, only the structures and film layers related to the aspects of the present invention are described herein, and the other structures and film layers are not further limited, and specific other structures and film layers may refer to those described in the related art.

Embodiments of the present application also provide a display panel including the above display substrate.

The display panel may be a flexible display panel (also referred to as a flexible screen) or a rigid display panel (i.e., a display panel that cannot be bent), which is not limited herein. The display panel may be an OLED display panel, and in the case that the display substrate does not include a light emitting functional layer, the display panel prepared by the display substrate may also be an LCD display panel or a Micro/Mini Micro display panel, which may be determined specifically according to the situation, and is not limited herein. The display panel has the advantages of good display effect and high stability.

The specific structure of the display substrate included in the display panel is not described again, and specific reference may be made to the related description of the display substrate in the foregoing.

Embodiments of the present application further provide a method for manufacturing a display substrate, as shown in fig. 9, the method includes:

s901, providing a substrate 1;

s902, forming at least one transistor 9; wherein the transistor 9 comprises an active layer 93, and a first pole 91 and a second pole 92 located at a side of the active layer 93 away from the substrate 1; the active layer 93 overlaps with a region between the first and second poles 91 and 92 in a direction perpendicular to the substrate 1;

s903, forming a light shielding layer 12; wherein the light-shielding layer 12 is located on a side of the transistor 9 away from the substrate 1, and the light-shielding layer 12 overlaps at least a region between the first pole 91 and the second pole 92 in a direction perpendicular to the substrate 1.

In the display substrate manufactured by the manufacturing method provided by the embodiment of the application, the light shielding layer 12 overlaps at least the region between the first pole 91 and the second pole 92 in the direction perpendicular to the substrate 1, and the active layer 93 overlaps the region between the first pole 91 and the second pole 92 in the direction perpendicular to the substrate 1, so that the light shielding layer 12 shields the part of the active layer 93 not covered by the first pole 91 and the second pole 92, and prevents ambient light (such as the light 1 shown in fig. 5) from entering the active layer 93 from the region between the first pole 91 and the second pole 92, thereby preventing the ambient light from affecting the stability of the active layer 93, further improving the NBTIS performance of the transistor 9 in the display substrate, and further improving the display effect of the display panel manufactured by the display substrate.

The following specifically describes a method for manufacturing a display substrate according to an embodiment of the present application, taking the structures of two display substrates shown in fig. 5 and fig. 8 as examples.

First, the preparation method of the display substrate shown in fig. 5 is:

s1, providing the substrate 1 as shown in fig. 10.

The substrate 1 is a rigid substrate, for example: and (3) glass.

S2, forming an organic layer 2 on the substrate 1; the material of the organic layer 2 is Polyimide (PI).

S3, a buffer layer 3 is formed on the organic layer 2.

The buffer layer 3 may be made of inorganic materials, such as: silicon nitride, silicon oxide or silicon oxynitride.

S4, forming an active thin film layer on the buffer layer 3; wherein the active thin film layer comprises the active layer 93, the source contact region 94 and the drain contact region 95 of the transistor 9.

The active layer 93, the source contact region 94, and the drain contact region 95 are formed simultaneously by patterning the active thin film layer and then doping.

S5, a gate insulating layer 4 is formed on the active layer 93, the source contact region 94, and the drain contact region 95.

Wherein the gate insulating layer 4 covers the active layer 93 and the buffer layer 3 in a region other than the transistors 9, and the gate insulating layer 4 has thereon a plurality of first via holes in a direction perpendicular to the substrate 1, the first via holes exposing the source contact region 94 and the drain contact region 95 of each of the transistors 9.

S6, the gate electrode 96 of each transistor 9 is simultaneously formed on the gate insulating layer 4.

S7, forming an interlayer dielectric layer 5 on the gate electrode 96; the interlayer dielectric layer 5 covers the gate electrode 96 and the gate insulating layer 4 outside the region where the transistor 9 is located.

And S8, forming a source drain metal layer on the interlayer dielectric layer 5.

Wherein the source drain metal layer comprises a first pole 91 and a second pole 92 of each transistor 9.

S9, a light shielding layer 12 as shown in fig. 11 is formed on the source-drain metal layer.

S10, forming a flat layer 6 on the light-shielding layer 12.

Wherein the planar layer 6 has a plurality of second vias in a direction perpendicular to the substrate 1, which expose partial areas of the second poles 92 of the respective transistors 9.

S11, the first electrode 11 is formed on the planarization layer 6 as shown in fig. 13.

Wherein the first electrode 11 is electrically connected to the second pole 92 of the transistor 9 via a second via.

S12, forming a pixel defining layer 7 on the first electrode 11; wherein the pixel defining layer 7 has a plurality of openings in a direction perpendicular to the substrate 1.

S13, forming a light emitting function layer on the pixel defining layer 7; wherein the light emitting function layer includes a plurality of light emitting function portions 10, and the light emitting function portions 10 are located at least in the openings of the pixel defining layer 7.

S14, forming a second electrode 8 on the light-emitting functional layer; the second electrode 8 covers all the light emitting functional sections 10 and the pixel defining layer 7 between the adjacent two light emitting functional sections 10.

Secondly, the preparation method of the display substrate shown in fig. 8 comprises:

s20, providing a substrate 1 and forming an organic layer 2 on the substrate 1.

Wherein the substrate 1 is a rigid substrate; the material of the organic layer 2 is Polyimide (PI).

S21, a buffer layer 3 is formed on the organic layer 2.

The buffer layer 3 may be made of inorganic materials, such as: silicon nitride, silicon oxide or silicon oxynitride.

S22, forming an active thin film layer on the buffer layer 3; wherein the active thin film layer comprises the active layer 93, the source contact region 94 and the drain contact region 95 of the transistor 9.

The active layer 93, the source contact region 94, and the drain contact region 95 are formed simultaneously by patterning the active thin film layer and then doping.

S23, a gate insulating layer 4 is formed on the active layer 93, the source contact region 94, and the drain contact region 95.

Wherein the gate insulating layer 4 covers the active layer 93 and the buffer layer 3 in an area other than the transistors 9, and the gate insulating layer 4 has thereon a plurality of first via holes in a direction perpendicular to the substrate 1, the first via holes exposing partial areas of the source contact region 94 and the drain contact region 95 of each of the transistors 9.

S24, the gate electrode 96 of each transistor 9 is simultaneously formed on the gate insulating layer 4.

S25, forming an interlayer dielectric layer 5 on the gate electrode 96; the interlayer dielectric layer 5 covers the gate electrode 96 and the gate insulating layer 4 outside the region where the transistor 9 is located.

S26, forming a source drain metal layer on the interlayer dielectric layer 5; wherein the source drain metal layer comprises a first pole 91 and a second pole 92 of each transistor 9.

S27, forming a flat layer 6 on the source drain metal layer as shown in FIG. 14; wherein the planar layer 6 has a plurality of second vias in a direction perpendicular to the substrate 1, which expose partial areas of the second poles 92 of the respective transistors 9.

S28, the light-shielding layer 12 shown in fig. 15 is formed on the planarization layer 6.

S29, forming the first electrode 11 shown in fig. 16 on the light shielding layer 12; wherein the first electrode 11 is electrically connected to the second pole 92 of the transistor 9 via a second via.

S30, forming a pixel defining layer 7 on the first electrode 11; wherein the pixel defining layer 7 has a plurality of openings in a direction perpendicular to the substrate 1.

S31, forming a light emitting function layer on the pixel defining layer 7; wherein the light emitting function layer includes a plurality of light emitting function portions 10, and the light emitting function portions 10 are located at least in the openings of the pixel defining layer 7.

S32, forming a second electrode 8 on the light-emitting functional layer; the second electrode 8 covers all the light emitting functional sections 10 and the pixel defining layer 7 between the adjacent two light emitting functional sections 10.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (12)

1. A display substrate, comprising: the transistor comprises a substrate, and a light shielding layer and at least one transistor which are positioned on the substrate;

the transistor comprises an active layer, a first pole and a second pole, wherein the first pole and the second pole are positioned on one side of the active layer, which is far away from the substrate; the active layer overlaps with a region between the first pole and the second pole in a direction perpendicular to the substrate;

the light shielding layer is positioned on one side of the transistor far away from the substrate, and the light shielding layer at least overlaps with the region between the first pole and the second pole in the direction perpendicular to the substrate.

2. The display substrate of claim 1,

the orthographic projection of the light shielding layer on the substrate is also overlapped with the orthographic projection of the first pole on the substrate;

and/or the orthographic projection of the light shielding layer on the substrate is partially overlapped with the orthographic projection of the second pole on the substrate.

3. The display substrate according to claim 1, wherein the light shielding layer is located between the first pole and the second pole, and the light shielding layer is insulated from the first pole and the second pole, respectively.

4. The display substrate of claim 3, wherein the display substrate comprises a plurality of transistors and an interlayer dielectric layer covering the active layer of each transistor, the interlayer dielectric layer being located between the first electrode of each transistor and the substrate;

the interlayer dielectric layer also extends to the region except the region where the transistor is located, and the shading layer also covers the interlayer dielectric layer except the region where the transistor is located.

5. The display substrate according to claim 4, wherein the display substrate further comprises a light-emitting functional layer on a side of the light-shielding layer away from the substrate, the light-emitting functional layer comprising a plurality of light-emitting functional portions;

wherein the light-shielding layer located outside the region where the transistor is located overlaps with the light-emitting functional portion in a direction perpendicular to the substrate.

6. The display substrate according to claim 1, further comprising a planarization layer covering each of the transistors;

the light shielding layer is positioned on one side of the flat layer far away from the substrate.

7. The display substrate according to claim 6, wherein the display substrate comprises a plurality of transistors and a plurality of first electrodes, each first electrode is located on one side of the flat layer away from the substrate, and two adjacent first electrodes are arranged at intervals;

the shading layer is located in a region between two adjacent first electrodes, and the shading layer is insulated from the first electrodes.

8. The display substrate according to claim 7, wherein an orthographic projection of the light shielding layer in a direction perpendicular to the substrate partially overlaps with an orthographic projection of the first electrode in a direction perpendicular to the substrate.

9. The display substrate according to claim 8, wherein a portion of the first electrode overlapping with the light shielding layer in a direction perpendicular to the substrate is located on a side of the light shielding layer away from the substrate.

10. The display substrate according to claim 8, wherein a part of the light shielding layer overlapping with the first electrode in a direction perpendicular to the substrate is located on a side of the first electrode away from the substrate.

11. The display substrate according to claim 7, wherein the display substrate further comprises a pixel defining layer, a plurality of light-emitting functional portions, and a second electrode covering each of the light-emitting functional portions;

the pixel defining layer is provided with a plurality of openings, the light-emitting functional part is at least positioned in the openings, and the light-emitting functional part is positioned between the first electrode and the second electrode.

12. A display panel comprising the display substrate according to any one of claims 1 to 11.

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