CN215680122U - Energy-saving circuit and energy-saving device of disk array - Google Patents
Energy-saving circuit and energy-saving device of disk array Download PDFInfo
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- CN215680122U CN215680122U CN202121474811.7U CN202121474811U CN215680122U CN 215680122 U CN215680122 U CN 215680122U CN 202121474811 U CN202121474811 U CN 202121474811U CN 215680122 U CN215680122 U CN 215680122U
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Abstract
The utility model provides an energy-saving circuit and an energy-saving device of a disk array, wherein the energy-saving circuit comprises a control chip, a power supply control circuit and a connector for connecting with an electronic inventory of the disk array; the control chip is electrically connected with the input end of the power supply control circuit, and the output end of the power supply control circuit is electrically connected with the input end of the connector; the control chip is used for controlling the on-off of the power supply control circuit so as to change the power supply state of the electronic disk.
Description
Technical Field
The utility model relates to the field of computer energy saving, in particular to an energy-saving circuit and an energy-saving device of a disk array.
Background
The disk array is a fast and ultra-large capacity external memory subsystem formed by a plurality of disk machines or optical disk machines according to certain rules, such as striping, blocking, cross access and the like. Under the control and management of the array controller, the method realizes fast, parallel or cross access and has stronger fault-tolerant capability. From the user's perspective, the disk array, although consisting of several, tens or even hundreds of disks, can still be considered as a single disk, and its capacity can be as high as several hundreds of gigabytes, so this technology is widely popular in multimedia systems.
However, as electronic products come into people's lives in a larger amount, energy-saving, green and environment-friendly electronic products become of great concern. Although the disk array related to the electronic product has high stability in data storage, the problem of energy consumption caused by the disk array related to the electronic product is not negligible, the existing scheme cannot well realize detection control of the disk array electronic disk, and the energy-saving effect of the disk array is not good.
SUMMERY OF THE UTILITY MODEL
The present invention is directed to an energy saving circuit and an energy saving device for a disk array, which can solve at least some of the above problems.
A first aspect of an embodiment of the present application provides an energy saving circuit for a disk array, where the energy saving circuit includes a control chip, a power supply control circuit, and a connector for connecting with an electronic inventory of the disk array;
the control chip is electrically connected with the input end of the power supply control circuit, and the output end of the power supply control circuit is electrically connected with the input end of the connector;
the control chip is used for controlling the on-off of the power supply control circuit so as to change the power supply state of the electronic disk.
In a possible implementation manner, the number of the electronic disks of the disk array is N, the control chip includes N pins, the number of the power supply control circuit and the number of the connectors are N, and each pin is electrically connected to one of the electronic disks in the disk array through one of the power supply control circuit and one of the connectors.
In one possible implementation manner, each power supply control circuit comprises a PMOS transistor and an NMOS transistor;
the grid electrode of the NMOS tube is electrically connected with one pin of the control chip, and the source electrode of the NMOS tube is grounded;
the drain electrode of the NMOS tube is electrically connected with the grid electrode of the PMOS tube and one end of the first resistor respectively;
the other end of the first resistor is electrically connected with a source electrode of the PMOS tube, and the source electrode of the PMOS tube is also used for being electrically connected with a first power supply;
and the drain electrode of the PMOS tube is electrically connected with the input end of the connector.
In one possible implementation, each of the control circuits further includes a first filter circuit and a second filter circuit;
one end of the first filter circuit is electrically connected with the grid electrode of the NMOS tube, and the other end of the first filter circuit is grounded;
one end of the second filter circuit is electrically connected with the drain electrode of the PMOS tube, and the other end of the second filter circuit is grounded;
the first filter circuit and the second filter circuit both comprise two parallel capacitors.
In a possible implementation manner, the power saving circuit further includes N status display circuits corresponding to the N electronic disks;
one end of each state display circuit is electrically connected with the output end of one connector, and the other end of each state display circuit is electrically connected with a second power supply.
In one possible implementation manner, each state display circuit comprises a light emitting diode and a second resistor which are connected in series;
one end of the light emitting diode, which is far away from the second resistor, is electrically connected with the output end of the connector, and one end of the second resistor, which is far away from the light emitting diode, is electrically connected with the second power supply.
In a possible implementation manner, the control chip is further configured to be electrically connected to an external device, and the disk array is electrically connected to the external device through a capacity detection chip;
the capacity monitoring chip is used for monitoring the actual capacity of the actually assembled electronic disk to obtain a comparison result of the actual capacity and the required disk capacity, and the external equipment sends control information of a level signal to the control chip according to the comparison result so as to adjust the level signal.
In a possible implementation manner, the control chip is electrically connected with the external device through a bidirectional binary synchronous serial bus.
In a possible implementation manner, a crystal oscillator is further connected to the control chip.
A first aspect of the embodiments of the present application provides an energy saving device for a disk array, where the energy saving device includes an energy saving circuit for a disk array according to the first aspect of the embodiments of the present application;
the control chip is electrically connected with the input end of the power supply control circuit and outputs a level signal for controlling the on-off of the power supply control circuit;
the connector is used for being electrically connected with the input end of the connector, and the output end of the connector is electrically connected with the electronic disk of the disk array to change the power supply state of the electronic disk according to the on-off state of the power supply control circuit.
The energy-saving circuit and the energy-saving device of the disk array have the advantages that:
the control chip is electrically connected with the input end of the power supply control circuit, the output end of the power supply control circuit is electrically connected with the input end of the connector, and the control chip controls the on-off of the power supply control circuit so as to change the power supply state of the electronic disk.
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible and comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a block diagram of a power saving circuit of a disk array according to an embodiment of the present invention;
fig. 2 is a power supply control circuit diagram included in a power saving circuit of a disk array according to an embodiment of the present invention;
fig. 3 is a pin diagram of a connector included in a power saving circuit of a disk array according to an embodiment of the present invention;
fig. 4 is a circuit diagram of a state display related to a power saving circuit of a disk array according to an embodiment of the present invention;
fig. 5 is a pin diagram of a control chip included in a power saving circuit of a disk array according to an embodiment of the present invention.
Icon:
a control chip 11; a power supply control circuit 12; a connector 13; an electronic disk 14;
a first resistor R1; a second resistor R2; a third resistor R3; a first capacitance C1; a second capacitance C2; a third capacitance C3; a fourth capacitance C4; a fifth capacitance C5;
a first PMOS transistor PMOS 1; a first NMOS transistor NMOS 1; a first pin P1; a first light emitting diode LED 1; a first power supply V1; a second power supply V2; the output terminal V1_ V1 of the control circuit;
a crystal oscillator Y1.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the utility model, as claimed, but is merely representative of selected embodiments of the utility model. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it is to be understood that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like, are used in an orientation or positional relationship as shown in the accompanying drawings, or as conventionally placed in use of the products of the present invention, or as conventionally understood by those skilled in the art, which are used only for convenience of description and simplicity of description, and do not show or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and thus are not to be construed as limiting the present invention.
Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Referring to fig. 1, the present embodiment provides a block diagram of a power saving circuit of a disk array. The energy-saving circuit of the disk array comprises a control chip, a power supply control circuit and a connector used for being connected with an electronic inventory of the disk array.
Specifically, the control chip 11 is electrically connected to an input terminal of the power supply control circuit 12, and an output terminal of the power supply control circuit 12 is electrically connected to an input terminal of the connector 13. The power supply control circuit 12 changes the on/off state of itself by receiving the level signal output by the control chip 11, for example, if the power supply control circuit 12 receives a low level signal, the power supply control circuit 12 is in an off state, and is not powered on at this time; if the power supply control circuit 12 receives a high level signal, the power supply control circuit 12 is in a conducting state, and is powered on.
Further, the control chip 11 is used for controlling the on/off of the power supply control circuit 12 to change the power supply state of the electronic disk 14. Specifically, the electronic disk 14 of the disk array is connected to the output terminal of the connector 13, and the input terminal of the connector 13 is electrically connected to the output terminal of the power supply control circuit 12, at this time, if the power supply control circuit 12 is in the off state, the connector 13 electrically connected to the power supply control circuit 12 is also in the off state, and further, the electronic disk 14 electrically connected to the connector 13 is not powered on and is in the off state.
The utility model provides an energy-saving circuit and an energy-saving device of a disk array, wherein the energy-saving circuit comprises a control chip, a power supply control circuit and a connector for connecting with an electronic inventory of the disk array, the control chip is electrically connected with the input end of the power supply control circuit, the output end of the power supply control circuit is electrically connected with the input end of the connector, the working state of an electronic disk can be changed by controlling the on-off state of the power supply control circuit, and the energy consumption of the disk array is further effectively controlled.
In a possible implementation manner, the number of the electronic disks 14 of the disk array is N, the control chip 11 includes N pins, the number of the power supply control circuit 12 and the number of the connectors 13 are N, and each pin is electrically connected to one electronic disk 14 of the disk array through one power supply control circuit 12 and one connector 13.
Specifically, by controlling the level signal output from one of the pins of the control chip 11, the on/off of the power supply control circuit 12 connected to the pin can be controlled according to the level signal, so as to change the operating state of the electronic disk 14.
Further, each power supply control circuit 12 includes a P-Channel MOS field effect transistor (PMOS for short) and an N-Channel MOS field effect transistor (NMOS for short), a gate of the NMOS is electrically connected to one pin of the control chip to receive the level signal sent from the control chip 11, and a source of the NMOS is grounded.
In addition, the drain of the NMOS transistor is electrically connected to the gate of the PMOS transistor and one end of the first resistor R1, respectively, the other end of the first resistor R1 is electrically connected to the source of the PMOS transistor, and the source of the PMOS transistor is further used for being electrically connected to the first power supply V1 to supply power to the power supply control circuit, optionally, the output voltage of the first power supply V1 is 5V.
Furthermore, each power supply control circuit 12 further includes a first filter circuit and a second filter circuit, one end of the first filter circuit is electrically connected to the gate of the NMOS transistor, and the other end of the first filter circuit is grounded; one end of the second filter circuit is electrically connected with the drain electrode of the PMOS tube, and the other end of the second filter circuit is grounded. The first filter circuit and the second filter circuit both comprise two parallel capacitors.
To make the above description clearer, please refer to fig. 2 exemplarily, and fig. 2 is a power supply control circuit diagram included in a power saving circuit of a disk array.
The power supply control circuit 12 comprises a first PMOS transistor PMOS1 and a first NMOS transistor NMOS1, a Gate (Gate Electrode for short) of the NMOS1 is electrically connected to a first pin P1 of the control chip, a Source (Source Electrode for short) of the NMOS1 is grounded, a Drain (Drain Electrode for short) of the NMOS1 is electrically connected to the G Electrode of the PMOS1 and one end of a first resistor R1, the other end of the first resistor R1 is electrically connected to the S Electrode of the PMOS1, and the S Electrode of the PMOS1 is electrically connected to a first power supply V1.
Optionally, in this embodiment, the control chip is a Complex Programmable Logic Device (CPLD).
Referring to fig. 3, fig. 3 is a pin diagram of a connector included in a power saving circuit of a disk array.
Specifically, when a low level is output through the first pin P1, the G pole and the S pole of the NMOS1 transistor are at zero potential, the NMOS1 transistor is not turned on, the first power supply V1 outputs a voltage of 5V, the PMOS1 is pulled up through the first resistor R1, the G pole of the PMOS1 transistor and the S pole of the PMOS1 are at equal potential, which is 5V, and the PMOS1 transistor is not turned on. If the output terminal V1_ V1 of the power supply control circuit is at 0V, and is in an off state and is not energized, the voltage at the input terminal V1_ V1 connected to the connector shown in fig. 3 to the electronic disk is also at 0V, and the connector is not energized, and the electronic disk 14 electrically connected to the connector 13 is not energized.
Conversely, when a high level is output through the first pin P1, the G pole of the NMOS1 transistor is at a high potential, the S pole of the NMOS1 transistor is at a zero potential, the NMOS1 transistor is turned on, the D pole of the NMOS1 transistor is also at a zero potential, the first power supply V1 outputs a voltage of 5V, the S pole of the PMOS1 transistor is 5V, the G pole of the PMOS1 transistor and the D pole of the NMOS1 transistor are at zero potentials, and the PMOS1 transistor is turned on. When the voltage at the output terminal V1_ V1 of the power supply control circuit 12 is 5V and is in a conducting state, and the voltage at the input terminal V1_ V1 connected to the electronic disk 14 as shown in fig. 3 is also 5V when power is supplied, the connector 13 is powered on, the electronic disk 14 electrically connected to the connector 13 is also powered on, and the electronic disk 14 operates normally.
The first filter circuit including the first capacitor C1 and the second capacitor C2, and the second filter circuit including the third capacitor C3 and the fourth capacitor C4 can couple interference signals, so that interference to the power supply control circuit 12 can be reduced.
Optionally, the control chip 11 is exemplified by a CPLD chip, and then there are 6 corresponding power supply control circuits 12, fig. 2 illustrates only one of the power supply control circuits, and the 5 power supply control circuits 12 electrically connected to the remaining 5 pins of the CPLD chip are the same as the power supply control circuit shown in fig. 2, which can be specifically referred to fig. 2, and are not described any more.
In a possible implementation, the power saving circuit of the disk array further includes N status display circuits corresponding to the N electronic disks 14, one end of each status display circuit is electrically connected to the second power supply, and optionally, each status display circuit includes a light emitting diode and a second resistor R2. Specifically, one end of the light emitting diode far away from the second resistor R2 is electrically connected to an output end of the connector 13, and one end of the second resistor R2 far away from the light emitting diode is electrically connected to the second power supply V2. Optionally, the output voltage of the second power supply V2 is 3.3V.
Specifically, referring to fig. 4, fig. 4 is a circuit diagram showing a state related to a power saving circuit of a disk array. In this embodiment, taking only one status display circuit of the N status display circuits as an example, one end of the second resistor R2 is electrically connected to the second power supply V2, the other end of the second resistor R2 is electrically connected to the first light emitting diode LED1, the other end of the first light emitting diode LED1 is electrically connected to the state _ LED1 of the connector shown in fig. 3, and the first light emitting diode LED1 indicates the power-on status of the electronic disk 14 electrically connected to the connector. If the first light emitting diode LED1 is not lit, it indicates that the corresponding electrically connected electronic disk 14 is not powered, and if the first light emitting diode LED1 is lit, it indicates that the corresponding electrically connected electronic disk 14 is powered. If the control chip 11 still uses the CPLD chip as an example, there are 6 corresponding status display circuits, and the remaining 5 status display circuits are the same as the status display circuit shown in fig. 4, which is specifically shown in fig. 4 and will not be described one by one here.
Referring to fig. 5, fig. 5 is a pin diagram of a control chip included in a power saving circuit of a disk array.
In a possible embodiment, the control chip 11 is further configured to be electrically connected to an external device, and the disk array is electrically connected to the external device through a capacity detection chip. Specifically, the capacity monitoring chip is configured to monitor an actual capacity of the actually assembled electronic disk 14, obtain a comparison result between the actual capacity and a required disk capacity, and the external device sends the level signal to the control chip 11 according to the comparison result to adjust the level signal, so as to control on/off of the corresponding power supply control circuit 12.
Illustratively, if the actual capacity of the electronic disk 14 detected by the capacity detection chip is higher than the required disk capacity, the comparison result is sent to the external device, and the external device sends low-level control information to the control chip 11, so that the control chip 11 sends a low level to the power supply control circuit 12, so that the power supply control circuit 12 is disconnected, and then the electronic disk 14 electrically connected correspondingly is controlled to be disconnected, and at this time, the electronic disk 14 is not powered on. If the actual capacity of the electronic disk 14 detected by the capacity detection chip is lower than the required disk capacity, the result is sent to the external device, and the external device sends high-level control information to the control chip 11, so that the control chip 11 sends high level to the power supply control circuit 12, the power supply control circuit 12 is powered on, and the electronic disk 14 which is correspondingly electrically connected is controlled to be powered on.
Optionally, the external device may send a low level or a high level to the power supply control circuit 12 corresponding to the pin through at least one pin as required according to the comparison result.
Optionally, the control chip 11 is electrically connected to the external device through a bidirectional binary synchronous serial bus, specifically, the control chip 11 takes a CPLD chip as an example, and the CPLD chip is electrically connected to the external device through its 6 th pin and 7 th pin.
Further, the control chip 11 is also connected with a crystal oscillator Y1 as shown in fig. 5, which can provide a highly frequency-stable ac signal for the control chip 11. Specifically, the 27 th pin of the control chip 11 is electrically connected to the output terminal of the crystal oscillator Y1 through a third resistor R3, the input terminal of the crystal oscillator Y1 is electrically connected to the second power supply V2, and the input terminal of the crystal oscillator Y1 is also connected to the fifth capacitor C5 in series and grounded.
In summary, in this embodiment, the control chip is electrically connected to the input terminal of the power supply control circuit, the output terminal of the power supply control circuit is electrically connected to the input terminal of the connector, the control chip controls the power supply control circuit to be turned on or off, and the capacity detection chip electrically connected to the disk array can accurately monitor the actual capacity of the electronic disk, so as to send control information of a level signal to the control chip through the external device, and finally change the power supply state of the electronic disk.
Corresponding to the energy saving circuit of the disk array, an embodiment of the present application further provides an energy saving device of a disk array, where the energy saving device includes an energy saving circuit of a disk array, and includes:
the control chip is electrically connected with the input end of the power supply control circuit and outputs a level signal for controlling the on-off of the power supply control circuit;
and the connector is used for being electrically connected with the input end of the connector, and the output end of the connector is electrically connected with the electronic disk of the disk array to change the power supply state of the electronic disk according to the on-off state of the power supply control circuit.
The control chip is electrically connected with the input end of the power supply control circuit, the output end of the power supply control circuit is electrically connected with the input end of the connector, and the working state of the electronic disk can be changed by controlling the on-off of the power supply control circuit, so that the energy consumption of the disk array is effectively controlled.
For a specific implementation process of the energy saving device for a disk array provided in this embodiment, reference may be made to the specific implementation process of the energy saving circuit for a disk array, which is not described in detail herein.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. The energy-saving circuit of the disk array is characterized by comprising a control chip, a power supply control circuit and a connector, wherein the connector is used for being connected with an electronic inventory of the disk array;
the control chip is electrically connected with the input end of the power supply control circuit, and the output end of the power supply control circuit is electrically connected with the input end of the connector;
the control chip is used for controlling the on-off of the power supply control circuit so as to change the power supply state of the electronic disk.
2. The power-saving circuit of a disk array according to claim 1, wherein the number of the electronic disks of the disk array is N, the control chip includes N pins, the number of the power supply control circuit and the number of the connectors are N, and each pin is electrically connected to one of the electronic disks of the disk array through one of the power supply control circuit and one of the connectors.
3. The power saving circuit of the disk array according to claim 2, wherein each of the power supply control circuits comprises a PMOS transistor and an NMOS transistor;
the grid electrode of the NMOS tube is electrically connected with one pin of the control chip, and the source electrode of the NMOS tube is grounded;
the drain electrode of the NMOS tube is electrically connected with the grid electrode of the PMOS tube and one end of the first resistor respectively;
the other end of the first resistor is electrically connected with a source electrode of the PMOS tube, and the source electrode of the PMOS tube is also used for being electrically connected with a first power supply;
and the drain electrode of the PMOS tube is electrically connected with the input end of the connector.
4. The power saving circuit of a disk array of claim 3, wherein each of the control circuits further comprises a first filter circuit and a second filter circuit;
one end of the first filter circuit is electrically connected with the grid electrode of the NMOS tube, and the other end of the first filter circuit is grounded;
one end of the second filter circuit is electrically connected with the drain electrode of the PMOS tube, and the other end of the second filter circuit is grounded;
the first filter circuit and the second filter circuit both comprise two parallel capacitors.
5. The power saving circuit of a disk array according to claim 2, wherein the power saving circuit further comprises N status display circuits corresponding to N electronic disks;
one end of each state display circuit is electrically connected with the output end of one connector, and the other end of each state display circuit is electrically connected with a second power supply.
6. The power-saving circuit of a disk array of claim 5, wherein each status display circuit comprises a light emitting diode and a second resistor connected in series;
one end of the light emitting diode, which is far away from the second resistor, is electrically connected with the output end of the connector, and one end of the second resistor, which is far away from the light emitting diode, is electrically connected with the second power supply.
7. The energy-saving circuit of the disk array according to claim 1, wherein the control chip is further configured to be electrically connected to an external device, and the disk array is electrically connected to the external device through a capacity detection chip;
the capacity monitoring chip is used for monitoring the actual capacity of the actually assembled electronic disk to obtain a comparison result of the actual capacity and the required disk capacity, and the external equipment sends control information of a level signal to the control chip according to the comparison result so as to adjust the level signal.
8. The power-saving circuit of a disk array of claim 7, wherein the control chip is electrically connected to the external device through a bi-directional binary synchronous serial bus.
9. The power-saving circuit of a disk array according to claim 1, wherein a crystal oscillator is further connected to the control chip.
10. An energy saving device for a disk array, wherein the energy saving device comprises the energy saving circuit for a disk array according to any one of claims 1 to 9;
the control chip is electrically connected with the input end of the power supply control circuit and outputs a level signal for controlling the on-off of the power supply control circuit;
the connector is used for being electrically connected with the input end of the connector, and the output end of the connector is electrically connected with the electronic disk of the disk array to change the power supply state of the electronic disk according to the on-off state of the power supply control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121474811.7U CN215680122U (en) | 2021-06-30 | 2021-06-30 | Energy-saving circuit and energy-saving device of disk array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121474811.7U CN215680122U (en) | 2021-06-30 | 2021-06-30 | Energy-saving circuit and energy-saving device of disk array |
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| Publication Number | Publication Date |
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| CN215680122U true CN215680122U (en) | 2022-01-28 |
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| CN202121474811.7U Active CN215680122U (en) | 2021-06-30 | 2021-06-30 | Energy-saving circuit and energy-saving device of disk array |
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| Country | Link |
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| CN (1) | CN215680122U (en) |
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- 2021-06-30 CN CN202121474811.7U patent/CN215680122U/en active Active
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Address after: 410000 room 801, accelerator production workshop, building B1, Haichuang science and Technology Industrial Park, No. 627 Lugu Avenue, Changsha high tech Development Zone, Changsha City, Hunan Province Patentee after: Hunan Xingtian Electronic Technology Co.,Ltd. Address before: 8a01, building B1, Lugu new Changhai center, Yuelu District, Changsha, Hunan 410000 Patentee before: HUNAN XING TIAN ELECTRONIC TECHNOLOGY Co.,Ltd. |
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Inventor after: Chen Dan Inventor after: Zhang Deming Inventor after: Yong Yixing Inventor before: Chen Dan Inventor before: Zhang Deming Inventor before: Fu Xinping Inventor before: Yong Yixing Inventor before: Li Jun |