CN215679354U

CN215679354U - RS232 serial port information acquisition circuit based on level conversion

Info

Publication number: CN215679354U
Application number: CN202121656038.6U
Authority: CN
Inventors: 张博超; 金春涛
Original assignee: Qingdao Ruiweishen Information Technology Co ltd
Current assignee: Qingdao Ruiweishen Information Technology Co ltd
Priority date: 2021-07-20
Filing date: 2021-07-20
Publication date: 2022-01-28
Anticipated expiration: 2031-07-20

Abstract

The utility model discloses an RS232 serial port information acquisition circuit based on level conversion, which mainly comprises the following contents: the first level driver is connected with the serial port information acquisition main controller, the second level driver is connected with the first level driver, the first RS232 isolation transceiver and the second RS232 isolation transceiver are connected with the second level driver, the first RS232 isolation transceiver and the second RS232 isolation transceiver are connected with the third level driver, the first RS232 serial port connector is connected with the first RS232 isolation transceiver, and the second RS232 serial port connector is connected with the second RS232 isolation transceiver. The utility model adopts a standard communication interface, so that a serial interface circuit can be connected between two devices in series quickly and conveniently, thereby completing the acquisition and recording of serial communication data; the whole circuit has an isolation application circuit, so that different devices are isolated from each other.

Description

RS232 serial port information acquisition circuit based on level conversion

Technical Field

The utility model relates to the technical field of serial port information acquisition, in particular to an RS232 serial port information acquisition circuit based on level conversion.

Background

In the communication industry, particularly in large complex systems, communication among a plurality of functional unit modules is completed through serial ports. The sub-modules communicate with each other through a specific communication protocol and a data format, so that the communication requirement of the whole system is met. Because the communication interface exists between the modules, the situations that the communication is abnormal and the sub-modules break down are inevitable. After a communication fault occurs, technical analysis is needed, so that the reason for generating the problem can be quickly and accurately found, the problem can be efficiently analyzed, and a problem solving scheme can be found. At this moment, the communication information records among the 2 devices, particularly the detailed communication information records, can provide clues for engineers to quickly solve problems, so that the serial port information acquisition circuit has wide use and very important application value, is equivalent to a black box for serial port communication, and is a good assistant for engineers to solve problems.

Disadvantages and drawbacks of the prior art:

(1) the existing serial port information acquisition equipment has the disadvantages of complex circuit interface design, inflexible installation mode and convenience;

(2) the existing circuit design has no protection function, mutual interference among circuits is easy to occur, and the stability of a system is reduced;

(3) the existing serial port information acquisition circuit is complex in functional design and high in cost for realizing the circuit;

(4) the existing circuit design can only be used for a special circuit, and the design and application have no universality.

SUMMERY OF THE UTILITY MODEL

Aiming at the defects in the prior art, the utility model discloses an RS232 serial port information acquisition circuit based on level conversion, which adopts a standard communication interface to ensure that a serial port interface circuit can be connected between two devices in series quickly and conveniently so as to finish the acquisition and recording of serial port communication data; the whole circuit has an isolation application circuit, so that mutual isolation among different devices is achieved, and the isolation and protection functions among circuit subsystems are achieved.

The technical scheme adopted by the utility model for solving the technical problems is as follows: an RS232 serial port information acquisition circuit based on level conversion comprises a serial port information acquisition main controller, a first level driver, a second level driver, a third level driver, a first RS232 isolation transceiver, a first RS232 serial port connector, a second RS232 serial port connector and a second RS232 isolation transceiver, the first level driver is connected with the serial port information acquisition main controller, the second level driver is connected with the first level driver, the first RS232 isolation transceiver and the second RS232 isolation transceiver are both connected with a second level driver, the third level driver is connected with the first level driver, the first RS232 isolation transceiver and the second RS232 isolation transceiver are both connected with the third level driver, the first RS232 serial port connector is connected with the first RS232 isolation transceiver, and the second RS232 serial port connector is connected with the second RS232 isolation transceiver.

As a preferred embodiment of the present invention, the serial port information acquisition master controller uses an STM32 single chip microcomputer.

In a preferred embodiment of the present invention, the first level driver is composed of a level shifter TXS0104 eqprq 1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, and a capacitor C2, the left end of the capacitor C1 and the pin 14 of the level shifter TXS0104 eqprq 1 are both connected to the power supply pin VCC1, the right end of the capacitor C2 and the pin 1 of the level shifter TXS0104 pwrq1 are both connected to the power supply pin VCC2, the right end of the capacitor C1 and the left end of the capacitor C2 are both grounded, the right end of the resistor R2 is connected to the pin 2 of the level shifter TXS0104 pwrq 2, the right end of the resistor R2 is connected to the pin 3 of the level shifter TXS0104 pwrq 2, the pin txr 2 is connected to the level shifter TXS0104 pwrq 36eq 364, the pin eq 2 is connected to the pin q 2, and the right end of the resistor TXS0104 eqr 2 is connected to the pin 2 and the pin TXS 2.

As a preferred embodiment of the present invention, the second level driver is composed of a level shifter TXS0104 eqprq 1, a resistor R6, a capacitor C3 and a capacitor C4, wherein the left end of the capacitor C3 and the pin 14 of the level shifter TXS0104 eqprq 1 are both connected to the power supply pin VCC1, the right end of the capacitor C4 and the pin 1 of the level shifter TXS0104 eqprq 1 are both connected to the power supply pin VCC2, the right end of the capacitor C1 and the left end of the capacitor C2 are both grounded, the left end of the resistor R6 is connected to the pin 8 of the level shifter TXS0104 eqprq 1, and the right end of the resistor R6 is connected to the power supply pin VCC 2.

As a preferred embodiment of the present invention, the third level driver is composed of a level shifter TXS0104 eqprq 1, a resistor R9, a capacitor C5 and a capacitor C6, wherein the left end of the capacitor C5 and the pin 14 of the level shifter TXS0104 eqprq 1 are both connected to the power supply pin VCC1, the right end of the capacitor C6 and the pin 1 of the level shifter TXS0104 eqprq 1 are both connected to the power supply pin VCC2, the right end of the capacitor C5 and the left end of the capacitor C6 are both grounded, the left end of the resistor R9 is connected to the pin 8 of the level shifter TXS0104 eqprq 1, and the right end of the resistor R9 is connected to the power supply pin VCC 2.

As a preferred embodiment of the present invention, the pin 2 of the level shifter TXS0104 eqprq 1 in the second level driver is connected to the pin 2 of the level shifter TXS0104 eqprq 1 in the third level driver through a resistor R7, and the pin 4 of the level shifter TXS0104 eqprq 1 in the second level driver is connected to the pin 4 of the level shifter TXS0104 eqprq 1 in the third level driver through a resistor R8.

In a preferred embodiment of the present invention, the first RS232 isolation transceiver is composed of an RS232 isolation transceiver ADM3251EARWZ-REEL, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C4 and a capacitor C12, the RS232 isolation transceiver ADM3251EARWZ-REEL pin 2, the RS232 isolation transceiver ADM3251EARWZ-REEL pin 3 and the upper end of the capacitor C7 are all connected to the power supply pin 1, the left end of the capacitor C8 is connected to the RS232 isolation transceiver ADM3251EARWZ-REEL pin 20, the right end of the capacitor C8 and the left end of the capacitor C9 are both connected to the RS232 isolation transceiver ADM3251 earwwz-REEL pin 19, the left end of the capacitor C10 is connected to the RS232 isolation transceiver ADM3251EARWZ-REEL 3218, the right end of the capacitor C transceiver 3 is connected to the RS232 isolation transceiver ADM3251 earwwwz-REEL 3273742, the left end of the capacitor C3818 is connected to the RS232 isolation transceiver roadm 3213, the left end of the capacitor C12 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 12.

In a preferred embodiment of the present invention, the first RS232 isolation transceiver is composed of an RS232 isolation transceiver ADM3251EARWZ-REEL, a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C4 and a capacitor C18, the RS232 isolation transceiver ADM3251EARWZ-REEL pin 2, the RS232 isolation transceiver ADM3251EARWZ-REEL pin 3 and the upper end of the capacitor C13 are all connected to the power supply pin 1, the left end of the capacitor C14 is connected to the RS232 isolation transceiver ADM3251EARWZ-REEL pin 20, the right end of the capacitor C14 and the left end of the capacitor C15 are both connected to the RS232 isolation transceiver ADM3251 earwwz-REEL pin 19, the left end of the capacitor C16 is connected to the RS232 isolation transceiver ADM3251EARWZ-REEL 3218, the right end of the capacitor C transceiver 3 is connected to the RS232 isolation transceiver ADM3251 earwwwz-REEL 3273742, the left end of the capacitor C3818 is connected to the RS232 isolation transceiver roadm 3213, the left end of the capacitor C18 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 12.

The utility model realizes the purpose of collecting the corresponding serial port information by carrying out interface conversion on the serial port types with different formats and protocols into the universal asynchronous transceiver and finally collecting the information of the universal asynchronous transceiver. The first RS232 serial port connector and the second RS232 serial port connector both use standard DB9 communication interfaces, so that the serial port information acquisition circuit can be conveniently and quickly accessed into a system; the first RS232 isolation transceiver and the second RS232 isolation transceiver have two functions, the first function is to realize isolation between circuits and protect an external communication circuit from generating functional influence and signal interference on a serial port information acquisition circuit, the second function is to realize level conversion of a serial port interface and realize unified and standard universal asynchronous transceiver signals, the well-known RS232 level is between-3V to-15V and between 3V to 15V, and the level can not be received and processed by a serial port information acquisition master controller, so that the RS232 level standard needs to be converted into a TTL level standard recognized by the serial port information acquisition master controller, and the circuit can be simultaneously applied to serial port information acquisition circuits of RS232, RS422 and RS 485; the first level driver, the second level driver and the third level driver have two functions, the first function is to realize the normal communication function of the communication equipment 1 and the communication equipment 2, the second function is to realize the information acquisition of the serial port interface circuit by the serial port information acquisition main controller, when the communication equipment 1 transmits data to the communication equipment 2, the serial port information acquisition main controller acquires the transmission information of the communication equipment 1, when the communication equipment 2 transmits data to the communication equipment 1, the serial port information acquisition main controller acquires the transmission information of the communication equipment 2, finally, the bidirectional data acquisition on a serial port link is realized, the complete acquisition of the serial port information among the 2 communication equipment is realized, and the communication among the 2 communication equipment is not influenced or interfered; the serial port information acquisition main controller is a general MCU or CPU main control, and can meet the application as long as a standard general asynchronous transceiver interface is provided; meanwhile, the serial port information saved by the serial port information acquisition main controller is usually saved in a text form of txt, so that powerful clues are provided for engineers to analyze and solve problems, and the problem solving efficiency is greatly improved.

The first RS232 serial port connector and the second RS232 serial port connector both comprise standard DB9 communication interfaces, and the first RS232 serial port connector and the second RS232 serial port connector connect 2 communication devices; the first RS232 isolation transceiver and the second RS232 isolation transceiver have the main functions of converting RS232 signals into TTL levels, have a circuit isolation function and play a circuit protection function, so that an acquisition circuit is not interfered and influenced by an external circuit; the first level driver, the second level driver and the third level driver carry out level conversion and loop-back processing on TTL signals output and input by the first RS232 isolation transceiver and the second RS232 isolation transceiver, wherein the level conversion circuit comprises 3 level drivers; the first level driver processes the sending signal, the second level driver processes the receiving signal, and the third level driver processes the level after the loop is combined; and the serial port information acquisition main controller receives an output signal from the third level driver, and finally realizes the acquisition and storage of the serial port information of 2 communication devices.

Compared with the prior art, the utility model has the following advantages: the standard communication interface is adopted, so that a serial port interface circuit can be connected between two devices in series quickly and conveniently, and the acquisition and recording of serial port communication data are completed; the whole circuit has an isolation application circuit, so that mutual isolation among different devices is achieved, and the isolation and protection functions among circuit subsystems are achieved; the serial port information acquisition uses a simple loop mode, so that the complexity of a designed circuit is greatly reduced, and the circuit cost is reduced; the circuit has a serial port level conversion circuit, and can be suitable for various serial port information acquisition circuits.

Drawings

FIG. 1 is a schematic diagram of the structure of the present invention;

FIG. 2 is a circuit diagram of a first level driver connected to a serial port information acquisition master controller according to the present invention;

FIG. 3 is a circuit diagram of the second level driver connected to the third level driver according to the present invention;

FIG. 4 is a circuit diagram of a first RS232 isolation transceiver according to the present invention;

fig. 5 is a circuit diagram of a second RS232 isolation transceiver according to the present invention.

Description of reference numerals:

1: serial port information acquisition master controller, 2: first level driver, 3: second level driver, 4: third level driver, 5: first RS232 isolation transceiver, 6: first RS232 serial connector, 7: second RS232 serial connector, 8: second RS232 isolator transceiver, R1, R2, R3, R4, R5, R6, R7, R8, R9: resistors, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18: capacitance, STM 32: singlechip, TXS0104 eqprq 1: level shifter, ADM3251 EARWZ-REEL: RS232 isolates the transceivers.

Detailed Description

The following description of the embodiments of the present invention refers to the accompanying drawings and examples:

it should be noted that the structures, proportions, sizes, and other dimensions shown in the drawings and described in the specification are only for the purpose of understanding and reading the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined by the following claims, and any modifications of the structures, changes in the proportions and adjustments of the sizes, without affecting the efficacy and attainment of the same, are intended to fall within the scope of the present disclosure.

In addition, the terms "upper", "lower", "left", "right", "middle" and "one" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as a scope of the present invention.

As shown in fig. 1 to 5, which illustrate specific embodiments of the present invention, as shown in the drawings, the RS232 serial port information acquisition circuit based on level conversion disclosed in the present invention includes a serial port information acquisition master 1, a first level driver 2, a second level driver 3, a third level driver 4, a first RS232 isolation transceiver 5, a first RS232 serial port connector 6, a second RS232 serial port connector 7, and a second RS232 isolation transceiver 8, where the first level driver 2 is connected to the serial port information acquisition master 1, the second level driver 3 is connected to the first level driver 2, the first RS232 isolation transceiver 5 and the second RS232 isolation transceiver 8 are both connected to the second level driver 3, the third level driver 4 is connected to the first level driver 2, the first RS232 isolation transceiver 5 and the second RS232 isolation transceiver 8 are both connected to the third level driver 4, the first RS232 serial port connector 6 is connected with the first RS232 isolation transceiver 5, and the second RS232 serial port connector 7 is connected with the second RS232 isolation transceiver 8.

Preferably, the serial port information acquisition main controller 1 adopts an STM32 single chip microcomputer.

Preferably, the first level driver 2 is composed of a level shifter TXS0104 eqprq 1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1 and a capacitor C2, the left end of the capacitor C1 and the pin 14 of the level shifter TXS0104 eqprq 1 are both connected to the power pin VCC1, the right end of the capacitor C2 and the pin 1 of the level shifter TXS0104 pwrq1 are both connected to the power pin VCC2, the right end of the capacitor C1 and the left end of the capacitor C2 are both grounded, the right end of the resistor R2 is connected to the pin 2 of the level shifter TXS0104 eqppwrq 2, the right end of the resistor R2 is connected to the pin eqps 0104 eqprq 2, the right end of the resistor R2 is connected to the pin eqps 0104 eqps 2, and the right end of the resistor TXS 2 is connected to the pin eqps 2 and the pin eqps 2.

Preferably, the second level driver 3 is composed of a level shifter TXS0104 eqprq 1, a resistor R6, a capacitor C3 and a capacitor C4, the left end of the capacitor C3 and the pin 14 of the level shifter TXS0104 eqprq 1 are both connected to the power supply pin VCC1, the right end of the capacitor C4 and the pin 1 of the level shifter TXS0104 eqprq 1 are both connected to the power supply pin VCC2, the right end of the capacitor C1 and the left end of the capacitor C2 are both grounded, the left end of the resistor R6 is connected to the pin 8 of the level shifter TXS0104 eqprq 1, and the right end of the resistor R6 is connected to the power supply pin VCC 2.

Preferably, the third level driver 4 comprises a level shifter TXS0104 eqprq 1, a resistor R9, a capacitor C5 and a capacitor C6, wherein the left end of the capacitor C5 and the pin 14 of the level shifter TXS0104 eqprq 1 are both connected to the power supply pin VCC1, the right end of the capacitor C6 and the pin 1 of the level shifter TXS0104 eqprq 1 are both connected to the power supply pin VCC2, the right end of the capacitor C5 and the left end of the capacitor C6 are both grounded, the left end of the resistor R9 is connected to the pin 8 of the level shifter TXS0104 eqprq 1, and the right end of the resistor R9 is connected to the power supply pin VCC 2.

Preferably, the pin 2 of the level shifter TXS0104 eqprq 1 in the second level driver 3 is connected to the pin 2 of the level shifter TXS0104 eqprq 1 in the third level driver 4 through a resistor R7, and the pin 4 of the level shifter TXS0104 eqprq 1 in the second level driver 3 is connected to the pin 4 of the level shifter TXS0104 eqprq 1 in the third level driver 4 through a resistor R8.

Preferably, the first RS232 isolation transceiver 5 is composed of an RS232 isolation transceiver ADM3251EARWZ-REEL, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11 and a capacitor C12, the upper ends of the RS232 isolating transceiver ADM3251EARWZ-REEL pin 2, the RS232 isolating transceiver ADM3251EARWZ-REEL pin 3 and the capacitor C7 are connected with a power supply pin VCC1, the left end of the capacitor C8 is connected with the RS232 isolation transceiver ADM3251EARWZ-REEL pin 20, the right end of the capacitor C8 and the left end of the capacitor C9 are both connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 19, the left end of the capacitor C10 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 18, the right end of the capacitor C10 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 17, the left end of the capacitor C11 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 14, the right end of the capacitor C11 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 13, the left end of the capacitor C12 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 12.

Preferably, the first RS232 isolation transceiver 8 is composed of an RS232 isolation transceiver ADM3251EARWZ-REEL, a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C17 and a capacitor C18, the upper ends of the RS232 isolating transceiver ADM3251EARWZ-REEL pin 2, the RS232 isolating transceiver ADM3251EARWZ-REEL pin 3 and the capacitor C13 are connected with a power supply pin VCC1, the left end of the capacitor C14 is connected with the RS232 isolation transceiver ADM3251EARWZ-REEL pin 20, the right end of the capacitor C14 and the left end of the capacitor C15 are both connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 19, the left end of the capacitor C16 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 18, the right end of the capacitor C16 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 17, the left end of the capacitor C17 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 14, the right end of the capacitor C17 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 13, the left end of the capacitor C18 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 12.

The utility model realizes the purpose of collecting the corresponding serial port information by carrying out interface conversion on the serial port types with different formats and protocols into the universal asynchronous transceiver and finally collecting the information of the universal asynchronous transceiver. The first RS232 serial port connector 6 and the second RS232 serial port connector 7 both use standard DB9 communication interfaces, so that the serial port information acquisition circuit can be conveniently and quickly accessed into a system; the first RS232 isolation transceiver 5 and the second RS232 isolation transceiver 8 have two functions, the first function is to realize isolation between circuits and protect an external communication circuit from generating functional influence and signal interference on a serial port information acquisition circuit, the second function is to realize level conversion of a serial port interface and realize unification of standard universal asynchronous transceiver signals, the well-known RS232 level is between-3V to-15V and between 3V to 15V, and the level can not be received and processed by a serial port information acquisition master controller 1, so that the RS232 level standard needs to be converted into a TTL level standard identified by the serial port information acquisition master controller 1, and the circuit can be simultaneously applied to serial port information acquisition circuits of RS232, RS422 and RS 485; the first level driver 2, the second level driver 3 and the third level driver 4 have two functions, the first function is to realize the normal communication function of the communication equipment 1 and the communication equipment 2, the second function is to realize the information acquisition of the serial port interface circuit by the serial port information acquisition main controller 1, when the communication equipment 1 sends data to the communication equipment 2, the serial port information acquisition main controller 1 acquires the sending information of the communication equipment, when the communication equipment 2 sends data to the communication equipment 1, the serial port information acquisition main controller 1 acquires the sending information of the communication equipment 2, and finally, the bidirectional data acquisition on a serial port link is realized, the whole acquisition of the serial port information among the 2 communication equipment is realized, and the communication among the 2 communication equipment is not influenced or interfered; the serial port information acquisition main controller 1 is a general MCU or CPU main controller, and can meet the application as long as a standard general asynchronous transceiver interface is provided; meanwhile, the serial port information stored by the serial port information acquisition main controller 1 is usually stored in a text form of txt, so that powerful clues are provided for engineers to analyze and solve problems, and the problem solving efficiency is greatly improved.

The first RS232 serial port connector 6 and the second RS232 serial port connector 7 both comprise standard DB9 communication interfaces, and the first RS232 serial port connector 6 and the second RS232 serial port connector 7 connect 2 communication devices; the first RS232 isolation transceiver 5 and the second RS232 isolation transceiver 8 mainly have the functions of converting RS232 signals into TTL levels, and have a circuit isolation function to play a circuit protection function so that an acquisition circuit is not interfered and influenced by an external circuit; the first level driver 2, the second level driver 3 and the third level driver 4 carry out level conversion and loop-back processing on TTL signals output and input by the first RS232 isolation transceiver 5 and the second RS232 isolation transceiver 8, wherein the level conversion circuit comprises 3 level drivers; the first level driver 2 processes the sending signal, the second level driver 3 processes the receiving signal, and the third level driver 4 processes the level after being combined into the loop; the serial port information acquisition main controller 1 receives the output signal from the third level driver 4, and finally, the acquisition and the storage of the serial port information of 2 communication devices are realized.

Although the preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present invention.

Many other changes and modifications can be made without departing from the spirit and scope of the utility model. It is to be understood that the utility model is not to be limited to the specific embodiments, but only by the scope of the appended claims.

Claims

1. The utility model provides a RS232 serial ports information acquisition circuit based on level conversion which characterized in that: including serial ports information acquisition master controller, first level driver, second level driver, third level driver, first RS232 isolation transceiver, first RS232 serial ports connector, second RS232 serial ports connector and second RS232 isolation transceiver, first level driver links to each other with serial ports information acquisition master controller, the second level driver is connected with first level driver, first RS232 isolation transceiver and second RS232 isolation transceiver all are connected with the second level driver, the third level driver is connected with first level driver, first RS232 isolation transceiver and second RS232 isolation transceiver all are connected with the third level driver, first RS232 serial ports connector links to each other with first RS232 isolation transceiver, second RS232 serial ports connector links to each other with second RS232 isolation transceiver.

2. The RS232 serial port information acquisition circuit based on level conversion according to claim 1, wherein: the serial port information acquisition main controller adopts an STM32 single chip microcomputer.

3. The RS232 serial port information acquisition circuit based on level conversion according to claim 1, wherein: the first level driver is composed of a level shifter TXS0104 eqprq 1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, and a capacitor C2, the left end of the capacitor C1 and the pin 14 of the level shifter TXS0104 eqprq 1 are both connected to the power supply pin VCC1, the right end of the capacitor C2 and the pin 1 of the level shifter TXS0104 eqprq 1 are both connected to the power supply pin VCC2, the right end of the capacitor C1 and the left end of the capacitor C2 are both connected to ground, the right end of the resistor R2 is connected to the pin 2 of the level shifter TXS0104 pwrq 2, the right end of the resistor R2 is connected to the pin 3 of the level shifter TXS0104 eqprq 2, the right end of the resistor R2 is connected to the pin eqps 0104 pwrq 2, and the right end of the resistor R2 is connected to the pin TXS0104 eqpr 2 and the pin 72 is connected to the pin txr 2, and the left end of the power supply pin 2 is connected to the pin TXS 2.

4. The RS232 serial port information acquisition circuit based on level conversion according to claim 1, wherein: the second level driver is composed of a level shifter TXS0104EQPWRQ1, a resistor R6, a capacitor C3 and a capacitor C4, wherein the left end of the capacitor C3 and the pin 14 of the level shifter TXS0104EQPWRQ1 are both connected with a power supply pin VCC1, the right end of the capacitor C4 and the pin 1 of the level shifter TXS0104EQPWRQ1 are both connected with a power supply pin VCC2, the right end of the capacitor C1 and the left end of the capacitor C2 are both grounded, the left end of the resistor R6 is connected with the pin 8 of the level shifter TXS0104EQPWRQ1, and the right end of the resistor R6 is connected with the power supply pin VCC 2.

5. The RS232 serial port information acquisition circuit based on level conversion according to claim 1, wherein: the third level driver is composed of a level shifter TXS0104EQPWRQ1, a resistor R9, a capacitor C5 and a capacitor C6, wherein the left end of the capacitor C5 and the pin 14 of the level shifter TXS0104EQPWRQ1 are both connected with a power supply pin VCC1, the right end of the capacitor C6 and the pin 1 of the level shifter TXS0104EQPWRQ1 are both connected with a power supply pin VCC2, the right end of the capacitor C5 and the left end of the capacitor C6 are both grounded, the left end of the resistor R9 is connected with the pin 8 of the level shifter TXS0104EQPWRQ1, and the right end of the resistor R9 is connected with the power supply pin VCC 2.

6. The RS232 serial port information acquisition circuit based on level conversion according to claim 1, wherein: the level shifter TXS0104EQPWRQ1 pin 2 in the second level driver is connected to the level shifter TXS0104EQPWRQ1 pin 2 in the third level driver through a resistor R7 and the level shifter TXS0104EQPWRQ1 pin 4 in the second level driver is connected to the level shifter TXS0104EQPWRQ1 pin 4 in the third level driver through a resistor R8.

7. The RS232 serial port information acquisition circuit based on level conversion according to claim 1, wherein: the first RS232 isolation transceiver consists of an RS232 isolation transceiver ADM3251EARWZ-REEL, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11 and a capacitor C12, the upper ends of the RS232 isolating transceiver ADM3251EARWZ-REEL pin 2, the RS232 isolating transceiver ADM3251EARWZ-REEL pin 3 and the capacitor C7 are connected with a power supply pin VCC1, the left end of the capacitor C8 is connected with the RS232 isolation transceiver ADM3251EARWZ-REEL pin 20, the right end of the capacitor C8 and the left end of the capacitor C9 are both connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 19, the left end of the capacitor C10 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 18, the right end of the capacitor C10 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 17, the left end of the capacitor C11 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 14, the right end of the capacitor C11 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 13, the left end of the capacitor C12 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 12.

8. The RS232 serial port information acquisition circuit based on level conversion according to claim 1, wherein: the first RS232 isolation transceiver consists of an RS232 isolation transceiver ADM3251EARWZ-REEL, a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C17 and a capacitor C18, the upper ends of the RS232 isolating transceiver ADM3251EARWZ-REEL pin 2, the RS232 isolating transceiver ADM3251EARWZ-REEL pin 3 and the capacitor C13 are connected with a power supply pin VCC1, the left end of the capacitor C14 is connected with the RS232 isolation transceiver ADM3251EARWZ-REEL pin 20, the right end of the capacitor C14 and the left end of the capacitor C15 are both connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 19, the left end of the capacitor C16 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 18, the right end of the capacitor C16 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 17, the left end of the capacitor C17 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 14, the right end of the capacitor C17 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 13, the left end of the capacitor C18 is connected with an RS232 isolation transceiver ADM3251EARWZ-REEL pin 12.