CN215496230U

CN215496230U - Paster piezo-resistor and circuit board

Info

Publication number: CN215496230U
Application number: CN202122037359.4U
Authority: CN
Inventors: 蔡锦波; 冉先发
Original assignee: Shenzhen Penang Electronics Co ltd
Current assignee: Shenzhen Penang Electronics Co ltd
Priority date: 2021-08-27
Filing date: 2021-08-27
Publication date: 2022-01-11
Anticipated expiration: 2031-08-27

Abstract

The utility model discloses a patch piezoresistor and a circuit board. A patch varistor comprising: the substrate is of a convex structure and is provided with an isolation groove to divide the substrate into a plurality of quadrangular frustum pyramid-shaped first parts; the side surface of the first part forms an angle theta with the direction vertical to the surface substrate; the electrode comprises an upper electrode and a lower electrode, and the upper electrode is arranged on the top surface of the first part to form a first electrode surface; the bottom surface of the base body is provided with a lower electrode as a common electrode to connect the plurality of first parts together. The surge protection problem in narrow space is solved, and the effects of reducing the size of the surface mounted piezoresistor, reducing the manufacturing cost and improving the output are achieved.

Description

Paster piezo-resistor and circuit board

Technical Field

The embodiment of the utility model relates to a piezoresistor technology, in particular to a patch piezoresistor and a circuit board.

Background

The voltage dependent resistor is a resistor with nonlinear voltage-current characteristics, and is mainly used for voltage clamping when a circuit bears overvoltage, and absorbing redundant current to protect sensitive devices. The varistor has the characteristics of large current resistance, energy absorption resistance and the like, when a circuit where the varistor is located bears transient large voltage such as lightning stroke, static electricity and the like, the resistance value of the varistor can be rapidly reduced to several ohms within tens of nanoseconds, so that the large current generated by high voltage is conducted, and a circuit system or an element connected in parallel with the varistor is prevented from being subjected to overvoltage breakdown, thereby achieving the effect of protecting the element or the circuit.

The patch type voltage dependent resistor in the prior art basically adopts the upper electrode and the lower electrode which are welded for the second time as the patch electrodes of MOV to realize the patch function, the thickness of the patch type voltage dependent resistor can increase the thickness of two electrodes and solder, the processing technology is complex, the manufacturing cost is relatively high, and the patch type voltage dependent resistor in the prior art has large occupied area and thicker thickness and is difficult to use in narrow spaces such as surge protection in the lamp industry.

SUMMERY OF THE UTILITY MODEL

The utility model provides a chip piezoresistor and a circuit board, which are used for realizing the effects of reducing the volume of the chip piezoresistor, reducing the manufacturing cost and improving the output.

In order to achieve the technical effects, the following technical scheme is adopted.

In a first aspect, the utility model provides a patch varistor, which comprises a substrate and electrodes, wherein the substrate is of a convex structure, and is provided with an isolation groove to divide the substrate into a plurality of quadrangular frustum pyramid-shaped first parts;

the side surface of the first part forms an angle theta with the direction vertical to the surface substrate;

the electrodes comprise an upper electrode and a lower electrode, and the upper electrode is arranged on the top surface of the first part to form a first electrode surface;

and a lower electrode is arranged on the bottom surface of the base body and used as a common electrode to connect the first parts together.

Optionally, the number of the first portions is at least two.

Optionally, the electrode is a sintered or sputtering metal electrode.

Optionally, the substrate is tablet-formed by a die.

Optionally, the substrate is cut by a laser or scribing process to generate the isolation grooves and the plurality of first portions, so as to form the convex structure.

Optionally, the substrate is processed by insulation packaging, and a top surface of the first portion is reserved for mounting.

In a second aspect, the utility model further provides a circuit board, which includes the patch varistor of any one of the first aspects, and the patch varistor is connected to the circuit board through the common electrode and at least two first electrode surfaces.

According to the utility model, the substrate of the chip varistor is divided into the convex structure comprising the first part and the second part through the isolation groove, the side surfaces of the first part and the second part and the side surface of the adjacent substrate form an angle theta, the upper electrodes are arranged on the top surfaces of the first part and the second part to form the first electrode surface and the second electrode surface, and the bottom surface of the substrate opposite to the isolation groove is provided with the lower electrode as the common electrode to connect the first part and the second part together, so that the surge protection problem in a narrow space is solved, the volume of the chip varistor is reduced, the manufacturing cost is reduced, and the output is improved.

Drawings

Fig. 1 is a schematic structural diagram of a patch varistor according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of another patch varistor provided in the embodiment of the present invention;

fig. 3 is a schematic structural diagram of another patch varistor provided in the embodiment of the present invention;

fig. 4 is a schematic structural diagram of another patch varistor according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the utility model and are not limiting of the utility model. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Examples

Fig. 1 is a schematic structural diagram of a patch varistor provided in an embodiment of the present invention, fig. 2 is a schematic structural diagram of another patch varistor provided in an embodiment of the present invention, and fig. 3 is a schematic structural diagram of another patch varistor provided in an embodiment of the present invention.

As shown in fig. 1, 2 and 3, a patch varistor includes: a base 30 and an electrode, wherein the base 30 has a convex structure, and the base 30 is provided with a plurality of rectangular truncated pyramid-shaped first parts 10 divided by isolation grooves 20;

the side 102 of the first portion 10 is at an angle θ to the adjacent side 303 of the substrate 30;

the electrodes comprise an upper electrode and a lower electrode, and the upper electrode is arranged on the top surface of the first part 10 to form a first electrode surface 101;

the bottom surface 302 of the base 30 is provided with a lower electrode as a common electrode 301 to connect the plurality of first portions 10 in common.

Optionally, the number of the first portions is at least two.

Wherein, the electrode adopts a sintered or sputtering formed metal electrode.

In this embodiment, an MOV structure is adopted to realize a single-sided patch function, and a convex varistor structure is adopted, as shown in fig. 1, two first portions 10 are taken as an example for explanation, the two first portions 10 are equivalent to two varistors, and two first electrode surfaces 101 form a parallel structure and form a series structure with a common electrode. The electrode in this embodiment is preferably a silver electrode. As shown in fig. 1, the side surfaces 102 of the two first portions 10 are at an angle θ with respect to the side surface 303 of the adjacent substrate 30, so that the insulation distance of the first electrode surface 101 is increased, and the dielectric breakdown voltage thereof is improved. Meanwhile, the surface discharge distance, i.e., the distance from I1 to I2 shown in fig. 3, is increased. In the prior art, a metal electrode plate is arranged at the bottom of a base body, and a leading-out end of the metal electrode plate is welded with a circuit board. In this embodiment, the bottom surface 302 of the base 30 opposite to the isolation groove 20 is provided with a lower electrode as a common electrode 301 to connect the two first portions 10 together, and the common electrode 301 is directly connected to the circuit board, so as to reduce the temperature impact influence of the welding electrode sheet on the circuit board elements.

In an alternative embodiment, the number of the first portions 10 is greater than 2, as shown in fig. 4, the number of the first portions 10 is 3, the three first portions 10 are sequentially arranged on the substrate, the three first portions 10 correspond to three piezoresistors, and the three first electrode surfaces 101 form a parallel structure and form a series structure with the common electrode.

In the prior art, the upper electrode and the lower electrode which are secondarily welded on the substrate are used as MOV patch electrodes, the thickness of the MOV patch electrodes is increased by the thickness of two electrodes and the thickness of solder, and in the embodiment, the silver electrode which is formed by sintering is used as the MOV patch electrode, so that the thickness of the patch piezoresistor is reduced, and as shown in figure 1, the thickness of the patch piezoresistor is T.

At least one isolation groove 20 is provided, when the number of the first portions 10 is larger than two, a plurality of isolation grooves are provided, the isolation grooves 20 are in a quadrangular frustum pyramid shape matched with the two adjacent first portions 10, as shown in fig. 1, the width of the isolation groove 20 at the bottom surface of the two first portions 10 is not limited, the isolation distance of the isolation groove 20 is further increased, and the insulation and voltage resistance is improved.

Optionally, the substrate 30 is cut by a laser or scribing process to generate the isolation grooves 20 and the plurality of first portions 10, so as to form the convex structure.

The manufacturing process of the embodiment adopts powder materials to be formed by die pressing, binder removal and sintering, silver coating and silver electrode sintering, and insulating encapsulation, compared with the prior art, the welding electrode slice is reduced, and the processing cost is reduced; the cutting process utilizes MOV silver sheets to cut through a laser or scribing process, and then insulating packaging is carried out. The manufacturing process is simple, the processing cost is reduced, and the production efficiency is improved.

Optionally, the substrate 30 is processed by insulation packaging, and the top surface of the first portion 10 is reserved for mounting.

The first electrode surfaces 101 of the plurality of first portions 10 are connected to the mounting surface of the varistor with other components.

The technical scheme of this embodiment, divide into the protruding type structure that contains a plurality of first parts through isolation groove with paster piezo-resistor's base member, the side of first part becomes theta degree with the side of adjacent base member, the top surface at the first part sets up the electrode and forms first electrode face, the bottom surface of the relative base member in isolation groove sets up down the electrode and connects a plurality of first parts jointly as common electrode, solve narrow and small space surge protection problem, realize reducing paster piezo-resistor's volume, reduce the effect of cost of manufacture and improvement output.

On the basis of the above embodiment, another embodiment further includes a circuit board including the patch varistor of any of the above embodiments, and the patch varistor is connected to the circuit board through the common electrode and at least two electrode surfaces.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the utility model. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A patch varistor, comprising: the substrate is of a convex structure and is provided with an isolation groove to divide the substrate into a plurality of quadrangular frustum pyramid-shaped first parts;

2. A patch varistor according to claim 1, wherein said first portions are at least two in number.

3. A patch varistor according to claim 1, wherein said electrodes are sintered or sputter formed metal electrodes.

4. A patch varistor according to claim 1, wherein said substrate is sheet-formed by means of a die.

5. A patch varistor according to claim 1, wherein said substrate is cut by laser or scribing process to form said isolation trenches and said first portions to form said convex structure.

6. A patch varistor according to claim 1, wherein said substrate is subjected to an insulation encapsulation process, leaving a top surface of said first portion for mounting.

7. A circuit board comprising a patch varistor as claimed in any one of claims 1 to 6, wherein said patch varistor is connected to the circuit board via the common electrode and at least two first electrode surfaces.