CN215494998U - Starting detection system and computer mainboard - Google Patents
Starting detection system and computer mainboard Download PDFInfo
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- CN215494998U CN215494998U CN202122051749.7U CN202122051749U CN215494998U CN 215494998 U CN215494998 U CN 215494998U CN 202122051749 U CN202122051749 U CN 202122051749U CN 215494998 U CN215494998 U CN 215494998U
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Abstract
The application discloses start detecting system and computer motherboard, start detecting system includes central processing unit, read only memory, information monitoring module and signal switching module. The signal switching module comprises a switch branch which is respectively connected with the central processing unit, the read-only memory and the signal monitoring module, and the switch branch is used for controlling the read-only memory to be connected to the signal monitoring module or controlling the read-only memory to be connected to the central processing unit according to a switching signal. The signal monitoring module is used for acquiring the firmware information of the read-only memory, detecting the firmware information and outputting a switching signal to the signal switching module according to the result of detecting the firmware information. Through the mode, the stability of the computer can be improved.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a start detection system and a computer motherboard.
Background
With the development of science and technology, computer devices such as notebook computers and all-in-one computers have been widely popularized and widely applied in various fields, and users can use the computer devices to store, transmit and process data.
At present, in an existing computer motherboard (for example, a loongson motherboard), a read-only memory is connected to a central processing unit through a bus, and after the computer is started, the program in the read-only memory is processed by the central processing unit for the first time.
However, in this way, when an abnormality occurs in the rom, that is, information in the rom is not secure, the cpu may be abnormal, for example, the cpu may not read related configuration information from the rom, that is, a safety hazard still exists, and stability of the computer is affected.
SUMMERY OF THE UTILITY MODEL
The embodiment of the application aims at providing a start detection system and a computer mainboard, and the application can improve the stability of a computer.
To achieve the above object, in a first aspect, the present application provides a start detection system, including:
the device comprises a central processing unit, a read-only memory, an information monitoring module and a signal switching module;
the signal switching module comprises a switch branch, the switch branch is respectively connected with the central processing unit, the read-only memory and the signal monitoring module, and the switch branch is used for controlling the read-only memory to be connected to the signal monitoring module or controlling the read-only memory to be connected to the central processing unit according to a switching signal;
the signal monitoring module is used for acquiring the firmware information of the read-only memory, detecting the firmware information and outputting the switching signal to the signal switching module according to the result of detecting the firmware information.
In an alternative mode, the switch branch comprises at least one single-pole double-throw switch, and the single-pole double-throw switch comprises a movable end and a fixed end;
the fixed end is connected with the read-only memory, the first end of the movable end is connected with the central processing unit, and the second end of the movable end is connected with the signal monitoring module.
In an optional manner, the signal switching module further includes a control unit;
the control unit is connected with the switch branch and used for outputting a control signal to control the on or off of the switch branch.
In an optional manner, the signal switching module further includes a signal switching interface;
the first pin of the signal switching interface is connected with a first voltage, the second pin of the signal switching interface is connected with the gating pin of the control unit, and the third pin of the signal switching interface is grounded.
In an optional manner, the signal switching module further includes a connection unit;
the connection unit is used for connecting a first pin of the signal switching interface and a second pin of the signal switching interface, or is used for connecting a second pin of the signal switching interface and a third pin of the signal switching interface.
In an optional mode, the information monitoring module includes a bus interface and an information security detection chip;
the information safety detection chip is arranged on the bus interface and used for acquiring the firmware information of the read-only memory through the bus interface, detecting the firmware information and outputting the switching signal to the signal switching module through the bus interface.
In an optional mode, the bus interface comprises a detection signal channel and a differential signal channel;
the detection signal channel is used for connecting the information safety detection chip;
the differential signal channel is used for transmitting differential signals.
In a second aspect, the present application provides a computer motherboard comprising the start-up detection system as described above.
The beneficial effects of the embodiment of the application are that: the application provides a start detection system, which comprises a central processing unit, a read-only memory, an information monitoring module and a signal switching module. Wherein, the signal switching module comprises a switch branch which is respectively connected with the central processing unit, the read-only memory and the signal monitoring module, when the computer is started, firstly, the switching signal controls the read-only memory to be connected to the signal monitoring module, so that the signal monitoring module can obtain the firmware information of the read-only memory, and then, if the signal monitoring module detects that the firmware information of the read-only memory has potential safety hazard, the read-only memory can be controlled to keep connected to the signal monitoring module through the switching signal, and the read-only memory is kept disconnected from the central processing unit, otherwise, if the signal monitoring module detects that the firmware information of the read-only memory is normal, the safety hidden danger does not exist, the read-only memory is controlled to be connected to the central processing unit through the switching signal, the abnormal risk of the central processing unit can be reduced, and the stability of the computer is improved.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
Fig. 1 is a schematic structural diagram of a Loongson main board in the prior art;
fig. 2 is a schematic structural diagram of a start detection system according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a switching branch according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a signal switching structure and a connection unit according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a start detection system according to another embodiment of the present application;
fig. 6 is a schematic structural diagram of a PCIE X8 connector according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a Loongson motherboard in the prior art. As shown in fig. 1, the Loongson motherboard includes a rom1 and a central controller 2. A BIOS (Basic Input Output System) program is provided in a Read Only Memory (ROM) 1. The BIOS program stores the most important basic input and output programs of the computer, the self-test program after power-on and the system self-starting program. A Central Processing Unit (CPU) is a final execution Unit for information Processing and program operation, and serves as an operation and control core of a computer system.
The rom1 is connected to the central controller 2 through a bus L, which may be an SPI bus, and the SPI (serial peripheral interface) bus technology is a synchronous serial interface. When the boot is started, the BIOS program in the ROM1 will take the CPU2 to identify and load important hardware and integrated components on the motherboard, such as a hard disk, a video card, a sound card, and various interfaces, then read the boot files of the operating system in the memory according to a preset sequence, and find the boot partition to load the operating system, such as DOS, Windows, Linux, etc., through the set boot mode.
Therefore, if the BIOS program has a safety hazard, for example, the code of the BIOS program is manually rewritten, or the version of the BIOS program is not correct, or the system-related configuration information is not comprehensive enough, or the BIOS program cannot be read, the subsequent operation of the CPU2 is adversely affected, for example, the CPU2 reads wrong information. That is, there is a safety hazard that may cause the CPU2 to be abnormal, thereby affecting the stability of the computer.
Based on this, this application provides a computer motherboard, this computer motherboard includes the start detection system in any embodiment of this application. The starting detection system can detect whether the read-only memory is normal or not when the computer is started. Therefore, the read-only memory can be connected with the central processing unit only when the read-only memory is normal, the risk of abnormity of the central processing unit can be reduced, and the stability of the computer can be improved.
As shown in fig. 2, the start-up detection system also includes a signal switching module 3 and an information monitoring module 4 on the basis of also including the rom1 and the cpu 2. The signal switching module 3 includes a switch branch 31, and the switch branch 31 is connected to the rom1, the cpu2, and the signal monitoring module 4 respectively.
Specifically, the switch branch 31 is used for controlling the rom1 to be connected to the signal monitoring module 4 according to the switching signal, or controlling the rom1 to be connected to the cpu 2. When the switch branch 31 controls the rom1 to be connected to the signal monitoring module 4, the signal monitoring module 4 can obtain firmware information of the rom through the switch branch 31 and detect the firmware signal, so as to output a switching signal to the signal switching module 3 according to a result of detecting the firmware information. The switching signal is used to control the switch branch 31 to keep the rom1 connected to the signal monitoring module 4, or to switch the rom1 to be connected to the cpu 2.
In practical applications, when the computer is started, the switch branch 31 can be controlled manually or automatically to connect the rom1 with the signal monitoring module 4. Then, the signal monitoring module 4 can read the firmware information in the rom1, i.e. read the relevant content of the BIOS program.
If the firmware information has a potential safety hazard, the read only memory 1 does not pass the detection, at this time, the switch branch 31 remains unchanged, and the read only memory 1 is still connected with the signal monitoring module 4. Under the condition, the computer can be determined to be abnormal or failed, so that the user can be restarted after further troubleshooting and solving the related potential safety hazard. If the firmware information is normal (i.e. no potential safety hazard exists), the read-only memory 1 passes the detection, at this time, the signal monitoring module 4 outputs a switching signal to the switch branch 31, so that the read-only memory 1 is switched to be connected with the central processing unit 2, and the computer enters a normal working state. In this embodiment, the computer can work only when the BIOS program in the rom1 is normal, and the risk of the computer being abnormal can be reduced, thereby facilitating the improvement of the stability of the computer.
In one embodiment, the switch branch 31 comprises at least one single-pole double-throw switch, which comprises a moving end and a fixed end. The fixed end is connected with the read-only memory 1, the first end of the movable end is connected with the central processing unit 2, and the second end is connected with the signal monitoring module 4.
The example in which the switch branch 31 includes 4 single-pole double-throw switches will be described. As shown in fig. 3, the switch branch 31 includes a first spdt switch S1, a second spdt switch S2, a third spdt switch S3 and a fourth spdt switch S4.
The fixed end COM1 of the first single-pole double-throw switch S1, the fixed end COM2 of the second single-pole double-throw switch S2, the fixed end COM3 of the third single-pole double-throw switch S3 and the fixed end COM4 of the fourth single-pole double-throw switch S4 are all used for being connected with the rom 1. The first end NC1 of the moving end of the first single-pole double-throw switch S1, the first end NC2 of the moving end of the second single-pole double-throw switch S2, the first end NC3 of the moving end of the third single-pole double-throw switch S3 and the first end NC4 of the moving end of the fourth single-pole double-throw switch S4 are all used for being connected with the signal monitoring module 4. The second end NO1 of the moving end of the first single-pole double-throw switch S1, the second end NO2 of the moving end of the second single-pole double-throw switch S2, the second end NO3 of the moving end of the third single-pole double-throw switch S3 and the second end NO4 of the moving end of the fourth single-pole double-throw switch S4 are all used for being connected with the cpu 2.
In this embodiment, at the time of starting the computer, since the fixed terminal of each single-pole double-throw switch is connected to the first terminal of the moving terminal, for example, the fixed terminal COM1 of the first single-pole double-throw switch S1 is connected to the first terminal NC1 of the moving terminal. At this time, the rom1 is connected to the signal monitoring module 4. The signal monitoring module 4 is used for acquiring the firmware information of the read-only memory. If the firmware information has potential safety hazard, each single-pole double-throw switch keeps the current state unchanged, namely the read-only memory 1 is still connected with the signal monitoring module 4. If the firmware information is normal, the signal monitoring module 4 outputs a switching signal to each single-pole double-throw switch, so that the moving end of each single-pole double-throw switch is switched from the current end to the second end. For example, the fixed terminal COM1 of the first single-pole double-throw switch S1 is switched from being connected with the first terminal NC1 of the moving terminal to being connected with the second terminal NO1 of the moving terminal; the fixed end COM2 of the second single-pole double-throw switch S2 is switched from being connected with the first end NC2 of the moving end to being connected with the second end NO2 of the moving end; the fixed end COM3 of the third single-pole double-throw switch S3 is switched from being connected with the first end NC3 of the moving end to being connected with the second end NO3 of the moving end; the fixed terminal COM4 of the fourth single pole double throw switch S4 is switched from being connected to the first terminal NC4 of the moving terminal to being connected to the second terminal NO4 of the moving terminal. Thereby, it is realized that the read only memory 1 is switched to be connected with the central processing unit 2. It should be noted that, in this embodiment, it is exemplified that the switch branch 31 includes 4 single-pole double-throw switches, and at this time, the same end of the 4 single-pole double-throw switches is connected to 4 pins. For example, the fixed terminal COM1 of the first spdt switch S1, the fixed terminal COM2 of the second spdt switch S2, the fixed terminal COM3 of the third spdt switch S3, and the fixed terminal COM4 of the fourth spdt switch S4 are used to connect to 4 pins of the rom 1. In other embodiments, the number of the set single-pole double-throw switches is different according to the number of the connection pins required by the same end of each single-pole double-throw switch, that is, the number of the single-pole double-throw switches can be set according to the actual application situation, which is not limited in the embodiments of the present application. In an embodiment, please continue to refer to fig. 3, the signal switching module 3 further includes a control unit 32. The control unit 32 is connected to each of the single-pole double-throw switches in the switch branch 31, and the control unit 32 is configured to output a control signal to control the switch branch 31 to be turned on or off, that is, the control signal is configured to control each of the single-pole double-throw switches to switch between the first end and the second end of the moving end. For example, the first single-pole double-throw switch S1 is controlled to switch from the first end NC1 connected to the moving end to the second end NO1, that is, the connection between the fixed end COM1 and the first end NC1 of the moving end corresponding to the first single-pole double-throw switch S1 is disconnected, and meanwhile, the connection between the fixed end COM1 and the second end NO1 is conducted.
It is understood that in this embodiment, the switching signal of each single-pole double-throw switch in the switch branch 31 is output by the control unit 32, while in other embodiments, the switching of each single-pole double-throw switch in the switch branch 31 may also be controlled by hardware, which is not limited by the embodiment of the present application.
In an embodiment, please refer to fig. 3, the signal switching module 3 further includes an enable pin EN and an enable pin SET. The enable pin EN is used for controlling whether the signal switching module 3 is in a working state, that is, when the enable pin EN is inputted with a signal in accordance with a set level, the signal switching module 3 enters the working state and can execute the functions that can be realized by the signal switching module 3; on the contrary, if the enable pin EN does not input a signal or the input signal does not conform to the set level, the signal switching module 3 stops working. The gating pin SET is used for controlling each single-pole double-throw switch in the switch branch 31 to switch between the first end and the second end of the moving end.
In one embodiment, as shown in fig. 4, the signal switching module 3 further includes a signal switching interface 33. The first pin J1 of the signal switching interface 33 is connected to the interface V1 through a first resistor R1, the interface V1 is used for being connected to a first voltage, the second pin J2 of the signal switching interface 33 is connected to the gate pin SET of the control unit 32 through the interface SET1, and the third pin J3 of the signal switching interface 33 is connected to the GND through a second resistor R2.
When the first pin J1 of the signal switching interface 33 is shorted with the second pin J2, the interface SET1 is pulled high, i.e., the level of the gate pin SET input to the control unit 32 is high. When the second pin J2 of the signal switching interface 33 is shorted with the third pin J3, the interface SET1 is pulled low, i.e., the level of the gate pin SET input to the control unit 32 is low.
In an embodiment, please continue to refer to fig. 4, the signal switching module 3 further includes a connection unit 34. The connection unit 34 is used for connecting the first pin J1 of the signal switching interface 33 and the second pin J2 of the signal switching interface 33, or is used for connecting the second pin J2 of the signal switching interface 33 and the third pin J3 of the signal switching interface 33. Preferably, the connection unit 34 may be provided as a hop cap.
As shown in fig. 4, the connection unit 34 may be configured to short the first pin J1 of the signal switching interface 33 and the second pin J2 of the signal switching interface 33, and at this time, the first voltage is transmitted to the interface SET1 through the interface V1, the first resistor R1, the first pin J1, the connection unit 34, and the second pin J1, so that the interface SET1 is pulled high. The connection unit 34 can also be used to short the second pin J2 of the signal switching interface 33 to the third pin J3 of the signal switching interface 33, at this time, the interface SET1 is shorted to ground, and the interface SET1 is pulled low.
In one embodiment, as shown in fig. 5, the information monitoring module 4 includes a bus interface 41 and an information security detection chip 42. The information security detection chip 42 is disposed on the bus interface 41, and usually, a slot is disposed on the bus interface 41, and the information security detection chip 42 is inserted into the slot of the bus interface 41.
Specifically, the information security detecting chip 42 is configured to obtain firmware information of the rom1 through the bus interface 41, detect the firmware information, and output a switching signal to the signal switching module 3 through the bus interface 41.
In an embodiment, the bus interface 41 may be a PCIE interface, and the information security detection chip 42 may be an SOC card. Among them, PCIE is a short hand for PCI-Express, and PCI-Express (peripheral component interconnect Express) is a high-speed serial computer expansion bus standard. PCIE belongs to high-speed serial point-to-point double-channel high-bandwidth transmission, connected equipment distributes independent channel bandwidth and does not share bus bandwidth, and mainly supports functions of active power management, error reporting, end-to-end reliable transmission, hot plug, quality of service (QOS) and the like. The SOC is an abbreviation of Security Operations Center, belongs to a Security operation Center in the field of information Security, and can acquire firmware information of the read-only memory and detect whether the firmware information is secure, and output a corresponding signal according to a detection result.
In one embodiment, bus interface 41 includes a sense signal path and a differential signal path. The detection signal channel may be used to connect the information security detection chip 42, and the differential signal channel is used to transmit differential signals.
In one embodiment, the bus interface 41 is a PCIE X8 connector. Referring to fig. 6, fig. 6 is a diagram illustrating an exemplary PCIE X8 connector according to an embodiment of the present application.
As shown in fig. 6, the PCIE X8 connector U1 includes a detection signal path and a differential signal path. Any 4 paths of differential signal channels of the PCIE X8 connector U1 may be selected to connect to the PCIE X4 standard card to transmit differential signals. For example, the available 4 differential signal paths are: the first path is as follows: the pin B14 and the pin B15 are used as pins for sending signals, and the pin A16 and the pin A17 are used as pins for receiving signals; and a second path: the pin B19 and the pin B20 are used as pins for sending signals, and the pin A21 and the pin A22 are used as pins for receiving signals; and a third path: the pin B23 and the pin B24 are used as pins for sending signals, and the pin A25 and the pin A26 are used as pins for receiving signals; and a fourth path: the pin B33 and the pin B34 are used as the signal-sending pins, and the pins A35 and A36 are used as the signal-receiving pins.
Furthermore, after the above pins are used as pins for connecting with the PCIE X4 standard card, the remaining pins may be correspondingly defined according to the pin definition of the SOC card. Therefore, the PCIE X8 connector U1 can be connected to both a PCIE X4 standard card and an SOC card, that is, the PCIE X8 connector provided in this embodiment can be compatible with the PCIE X4 standard card and the SOC card at the same time, i.e., the BIOS program can be detected by the SOC card, and the use of the PCIE X4 standard card is not affected, which is favorable for improving the stability and the practicability of the product.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; within the context of the present application, where technical features in the above embodiments or in different embodiments can also be combined, the steps can be implemented in any order and there are many other variations of the different aspects of the present application as described above, which are not provided in detail for the sake of brevity; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (8)
1. A start-up detection system, comprising:
the device comprises a central processing unit, a read-only memory, an information monitoring module and a signal switching module;
the signal switching module comprises a switch branch, the switch branch is respectively connected with the central processing unit, the read-only memory and the signal monitoring module, and the switch branch is used for controlling the read-only memory to be connected to the signal monitoring module or controlling the read-only memory to be connected to the central processing unit according to a switching signal;
the signal monitoring module is used for acquiring the firmware information of the read-only memory, detecting the firmware information and outputting the switching signal to the signal switching module according to the result of detecting the firmware information.
2. The activation detection system of claim 1,
the switch branch comprises at least one single-pole double-throw switch, and the single-pole double-throw switch comprises a movable end and a fixed end;
the fixed end is connected with the read-only memory, the first end of the movable end is connected with the central processing unit, and the second end of the movable end is connected with the signal monitoring module.
3. The activation detection system according to claim 1 or 2,
the signal switching module also comprises a control unit;
the control unit is connected with the switch branch and used for outputting a control signal to control the on or off of the switch branch.
4. The activation detection system of claim 3,
the signal switching module also comprises a signal switching interface;
the first pin of the signal switching interface is connected with a first voltage, the second pin of the signal switching interface is connected with the gating pin of the control unit, and the third pin of the signal switching interface is grounded.
5. The activation detection system of claim 4,
the signal switching module further comprises a connecting unit;
the connection unit is used for connecting a first pin of the signal switching interface and a second pin of the signal switching interface, or is used for connecting a second pin of the signal switching interface and a third pin of the signal switching interface.
6. The activation detection system of claim 1,
the information monitoring module comprises a bus interface and an information safety detection chip;
the information safety detection chip is arranged on the bus interface and used for acquiring the firmware information through the bus interface, detecting the firmware information and outputting the switching signal to the signal switching module through the bus interface.
7. The activation detection system of claim 6,
the bus interface comprises a detection signal channel and a differential signal channel;
the detection signal channel is used for connecting the information safety detection chip;
the differential signal channel is used for transmitting differential signals.
8. A computer motherboard comprising a startup detection system as claimed in any one of claims 1 to 7.
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| CN202122051749.7U CN215494998U (en) | 2021-08-27 | 2021-08-27 | Starting detection system and computer mainboard |
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| CN202122051749.7U CN215494998U (en) | 2021-08-27 | 2021-08-27 | Starting detection system and computer mainboard |
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Effective date of registration: 20231031 Address after: 518000, 4th Floor, No. 31, Xiacun Community, Gongming Street, Guangming District, Shenzhen City, Guangdong Province Patentee after: Shenzhen Baoxinchuang Information Technology Co.,Ltd. Address before: 518000 2nd floor, no.6, huidebao Industrial Park, No.11, second industrial zone, Baihua community, Guangming Street, Guangming District, Shenzhen City, Guangdong Province Patentee before: Shenzhen baoxinchuang Technology Co.,Ltd. |
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