CN215493862U - Anti-dismantling detection circuit - Google Patents
Anti-dismantling detection circuit Download PDFInfo
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- CN215493862U CN215493862U CN202120339104.0U CN202120339104U CN215493862U CN 215493862 U CN215493862 U CN 215493862U CN 202120339104 U CN202120339104 U CN 202120339104U CN 215493862 U CN215493862 U CN 215493862U
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Abstract
The utility model discloses a disassembly prevention detection circuit, which comprises an abnormality detection circuit, an abnormality holding circuit and a microprocessor which are connected in sequence; the abnormality detection circuit and the abnormality holding circuit are powered by a power supply VCC, and the microprocessor is powered by a power supply VDD; the abnormality detection circuit is used for detecting whether the electronic product is detached or not; when the abnormality detection circuit detects that the electronic product is detached, an abnormality signal can be generated to the holding circuit; and the exception holding circuit enters a holding state after receiving the exception signal, and then keeps outputting an exception holding signal to the microprocessor. The utility model can be used for detecting whether the electronic product is disassembled or not, and effectively improves the safety of the electronic product.
Description
Technical Field
The utility model relates to the technical field of electronic information, in particular to an anti-disassembly detection circuit.
Background
With the development of electronic information technology, electronic products are widely applied in various application fields, electronic product design and manufacturers are more and more, and many competitors can obtain the internal structure and data information of the electronic products by disassembling the electronic products, so as to plagiarize the electronic products; therefore, in order to ensure that an innovative product has a competitive advantage in market competition, it is necessary to design a tamper-proof detection circuit capable of detecting whether an electronic product is detached.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a disassembly prevention detection circuit which can detect whether an electronic product is disassembled or not and has high reliability.
In order to achieve the above purpose, the solution of the utility model is:
a tamper detection circuit comprises an abnormality detection circuit, an abnormality holding circuit and a microprocessor which are connected in sequence; the abnormality detection circuit and the abnormality holding circuit are powered by a power supply VCC, the microprocessor is powered by a power supply VDD, and the abnormality detection circuit, the abnormality holding circuit and the microprocessor are grounded together; the abnormality detection circuit is used for detecting whether the electronic product is detached or not; when the abnormality detection circuit detects that the electronic product is detached, an abnormality signal can be generated to the holding circuit; if the abnormality detection circuit does not detect that the electronic product is detached, a normal signal is generated to the abnormality holding circuit; and the exception holding circuit enters a holding state after receiving the exception signal, and then keeps outputting an exception holding signal to the microprocessor.
The normal signal is a low level signal, and the abnormal signal is a high level signal; the abnormity holding circuit comprises a resistor R1, a resistor R2, a MOS transistor M1, an inverter U1, an inverter U2 and an AND gate U3; the input end of the inverter U1 is the input end of the abnormity holding circuit, and the input end of the abnormity holding circuit is connected with the output end of the abnormity detection circuit; the output end of the inverter U1 is connected with the first input end of the AND gate U3, the second input end of the AND gate U3 is connected with the first end of the resistor R1 and the drain electrode of the MOS tube M1, the second end of the resistor R1 is connected with the power VCC, the source electrode of the MOS tube M1 is grounded, and the gate electrode of the MOS tube M1 is connected with the output end of the inverter U2 through the resistor R2; the output end of the AND gate U3 is connected with the input end of the inverter U2 and serves as the output end of the abnormity holding circuit, and the output end of the abnormity holding circuit is connected with one input end of the microprocessor.
The output of the exception holding circuit is connected to one input of the microprocessor through a resistor R3.
The anti-disassembly detection circuit further comprises a releasing circuit used for controlling the abnormal holding circuit to release the holding state, the input end of the releasing circuit is connected with one output end of the microprocessor, and the output end of the releasing circuit is connected with the grid electrode of the MOS tube M1.
The release circuit comprises a resistor R4 and a MOS tube M2; the gate of the MOS transistor M2 is connected to the first terminal of the resistor R4 and serves as the input terminal of the release circuit, the drain of the MOS transistor M2 serves as the output terminal of the release circuit, and the source of the MOS transistor M2 is connected to the second terminal of the resistor R4 and is grounded.
The input of the deactivation circuit is connected to an output of the microprocessor through a resistor R5.
The abnormality detection circuit comprises a light touch switch SW1 and a resistor R6, wherein the first end of the light touch switch SW1 is the output end of the abnormality detection circuit, the output end of the abnormality detection circuit is connected with the input end of the abnormality holding circuit, the first end of the light touch switch SW1 is connected with a power supply VCC through the resistor R6, and the second end of the light touch switch SW1 is grounded.
The abnormality detection circuit further comprises a resistor R7, a first end of the resistor R7 is connected with a common end of the tact switch SW1 and the resistor R6, and a second end of the resistor R7 is connected with one input end of the microprocessor.
After adopting the scheme, the utility model has the following characteristics:
1. the microprocessor can judge whether the electronic product is disassembled or not according to the condition that whether the abnormal holding signal is received or not, so that the electronic product is detected whether to be disassembled or not;
2. the abnormal holding circuit of the utility model enters a holding state after receiving the abnormal signal, and then the abnormal holding circuit keeps outputting an abnormal holding signal to the microprocessor, so that even if the microprocessor is electrified again, the abnormal holding circuit still keeps outputting the abnormal holding signal to the microprocessor, thereby ensuring good reliability of the utility model.
Drawings
Fig. 1 is a schematic circuit diagram of the present invention.
Detailed Description
In order to further explain the technical solution of the present invention, the present invention is explained in detail by the following specific examples.
As shown in fig. 1, the present invention discloses a tamper detection circuit, which includes an abnormality detection circuit, an abnormality holding circuit and a microprocessor connected in sequence, wherein the abnormality detection circuit and the abnormality holding circuit are powered by a power source VCC, the microprocessor is powered by a power source VDD, and the abnormality detection circuit, the abnormality holding circuit and the microprocessor are grounded in common, and the power source VCC can be provided by a battery; the abnormality detection circuit is used for detecting whether the electronic product is detached or not, and can generate an abnormal signal to the holding circuit when the abnormality detection circuit detects that the electronic product is detached, and generate a normal signal to the abnormality holding circuit if the abnormality detection circuit does not detect that the electronic product is detached; and the abnormality holding circuit enters a holding state after receiving the abnormality signal, and then the abnormality holding circuit keeps outputting an abnormality holding signal to the microprocessor.
As shown in fig. 1, the abnormality detection circuit includes a tact switch SW1 and a resistor R6, a first end of the tact switch SW1 is an output end of the abnormality detection circuit, an output end of the abnormality detection circuit is connected to an input end of the abnormality holding circuit, a first end of the tact switch SW1 is connected to a power VCC through the resistor R6, and a second end of the tact switch SW1 is grounded. When the electronic product is not detached, the tact switch SW1 is in a pressed state to turn on the tact switch SW1, so that the abnormality detection circuit outputs a normal signal which is a low level signal to the abnormality holding circuit; when the electronic product is detached, the tact switch SW1 is released from the pressed state to turn off the tact switch SW1, so that the abnormality detection circuit outputs an abnormality signal of a high level signal to the abnormality holding circuit.
As shown in fig. 1, the anomaly maintaining circuit includes a resistor R1, a resistor R2, a MOS transistor M1, an inverter U1, an inverter U2, and an and gate U3; the input end of the inverter U1 is the input end of the abnormity holding circuit, and the input end of the abnormity holding circuit is connected with the output end of the abnormity detection circuit; the output end of the inverter U1 is connected with the first input end of the AND gate U3, the second input end of the AND gate U3 is connected with the first end of the resistor R1 and the drain electrode of the MOS tube M1, the second end of the resistor R1 is connected with the power VCC, the source electrode of the MOS tube M1 is grounded, and the gate electrode of the MOS tube M1 is connected with the output end of the inverter U2 through the resistor R2; the output end of the AND gate U3 is connected with the input end of the inverter U2 and serves as the output end of the abnormity holding circuit, and the output end of the abnormity holding circuit is connected with one input end of the microprocessor. As shown in fig. 1, the output terminal of the anomaly keeping circuit can be connected to an input terminal of the microprocessor through a resistor R3, and the resistor R3 can play a role of current limiting protection to protect the microprocessor.
The working principle of the abnormity holding circuit of the utility model is as follows:
when the electronic product is not disassembled, the abnormality detection circuit outputs a normal signal which is a low level signal to the abnormality holding circuit, the inverter U1 further outputs a high level signal to the first input end of the AND gate U3, meanwhile, the second input end of the AND gate U3 is connected with a power VCC through a resistor R1 so that the level of the second input end of the AND gate U3 is high level, the levels of the first input end and the second input end of the AND gate U3 are both high level so that the AND gate U3 outputs a high level signal to the microprocessor and the inverter U2, and the microprocessor receives the high level signal to judge that the electronic product is not disassembled; the inverter U2 outputs a low level to the gate of the MOS transistor M1, and at this time, the MOS transistor M1 is turned off, so that the level of the second input terminal of the and gate U3 is still high; finally, the levels of the first input end and the second input end of the and gate U3 are both high levels, so that the abnormality holding circuit outputs a high level signal to the microprocessor, and the microprocessor receives the high level signal output by the abnormality holding circuit and enters a normal working mode;
when the electronic product is disassembled, the abnormality detection circuit outputs an abnormal signal which is a high level signal to the abnormality holding circuit, the inverter U1 further outputs a low level signal to the first input end of the AND gate U3, at the moment, the AND gate U3 outputs an abnormal holding signal which is a low level signal to the microprocessor and the inverter U2, the microprocessor receives the abnormal holding signal to judge that the electronic product is disassembled, and then the microprocessor enters an abnormal processing working mode; after receiving the abnormal holding signal, the inverter U2 outputs a high level signal to the gate of the MOS transistor M1, and at this time, the MOS transistor M1 is turned on to make the level of the second input terminal of the and gate U3 low, so that the abnormal holding circuit enters a holding state, and thereafter, the and gate U3 keeps outputting the abnormal holding signal of the low level signal to the microprocessor and the inverter U2 no matter how the signal output to the abnormal holding circuit by the abnormality detection circuit changes, so that the microprocessor and the inverter U2 continuously receive the abnormal holding signal; thereafter, if the microprocessor is powered on again, the and gate U3 still keeps outputting the exception holding signal as the low level signal to the microprocessor, so that the microprocessor still enters the exception handling mode, thereby improving the reliability of the present invention. When the microprocessor enters an abnormal processing working mode, the microprocessor can control the back end circuit connected with the microprocessor not to work so as to prevent data leakage, and in addition, the microprocessor can send signals to the server at the back end, so that the server at the back end can know that the electronic product is detached.
As shown in fig. 1, the present invention may further include a release circuit for controlling the abnormal holding circuit to release the holding state, an input terminal of the release circuit is connected to an output terminal of the microprocessor, and an output terminal of the release circuit is connected to the gate of the MOS transistor M1. When the electronic product is installed before leaving the factory and is maintained subsequently, an installer installs the electronic product to enable the abnormality detection circuit to output a normal signal which is a low-level signal to the abnormality holding circuit, then the installer can send a releasing instruction for controlling the abnormality holding circuit to release the holding state to the microprocessor, the microprocessor receives the releasing instruction and then controls the abnormality holding circuit to release the holding state through the releasing circuit, at the moment, the abnormality holding circuit can output a high-level signal to the microprocessor, and the microprocessor exits the abnormality processing working mode and closes the releasing circuit. As shown in fig. 1, specifically, the release circuit includes a resistor R4 and a MOS transistor M2; the gate of the MOS transistor M2 is connected with the first end of the resistor R4 and serves as the input end of the release circuit, the drain of the MOS transistor M2 serves as the output end of the release circuit, and the source of the MOS transistor M2 is connected with the second end of the resistor R4 and is grounded; when the abnormity holding circuit is in a holding state, people issue a release instruction to the microprocessor, the microprocessor outputs a high level signal to the release circuit after receiving the release instruction to control the conduction of the MOS tube M2, the MOS tube M2 is conducted to pull down the grid level of the MOS tube M1, further the MOS tube M1 is cut off to enable the level of the second input end of the AND gate U3 to be high level, the abnormity holding circuit releases the holding state, and the level of the output end of the abnormity holding circuit is controlled by the level of the output end of the abnormity detection circuit. The input end of the release circuit can be connected with one output end of the microprocessor through a resistor R5, and the resistor R5 can play a role in current limiting protection to protect the microprocessor and the release circuit.
As shown in fig. 1, the abnormality detection circuit further includes a resistor R7, a first end of the resistor R7 is connected to a common end of the tact switch SW1 and the resistor R6, and a second end of the resistor R7 is connected to an input end of the microprocessor, so that the microprocessor can detect a level of an output end of the abnormality detection circuit through the resistor R7, and the microprocessor can control the release circuit according to a release instruction issued by a user to the microprocessor when the level of the output end of the abnormality detection circuit is low, so that the microprocessor exits the abnormality processing mode and closes the release circuit.
The above embodiments and drawings are not intended to limit the form and style of the present invention, and any suitable changes or modifications thereof by those skilled in the art should be considered as not departing from the scope of the present invention.
Claims (6)
1. A tamper detection circuit, comprising: the device comprises an abnormality detection circuit, an abnormality holding circuit and a microprocessor which are connected in sequence; the abnormality detection circuit and the abnormality holding circuit are powered by a power supply VCC, the microprocessor is powered by a power supply VDD, and the abnormality detection circuit, the abnormality holding circuit and the microprocessor are grounded together;
the abnormality detection circuit is used for detecting whether the electronic product is detached or not; when the abnormality detection circuit detects that the electronic product is detached, an abnormality signal can be generated to the holding circuit; if the abnormality detection circuit does not detect that the electronic product is detached, a normal signal is generated to the abnormality holding circuit;
the abnormality holding circuit enters a holding state after receiving the abnormality signal, and then the abnormality holding circuit keeps outputting an abnormality holding signal to the microprocessor;
the normal signal is a low level signal, and the abnormal signal is a high level signal; the abnormity holding circuit comprises a resistor R1, a resistor R2, a MOS transistor M1, an inverter U1, an inverter U2 and an AND gate U3; the input end of the inverter U1 is the input end of the abnormity holding circuit, and the input end of the abnormity holding circuit is connected with the output end of the abnormity detection circuit; the output end of the inverter U1 is connected with the first input end of the AND gate U3, the second input end of the AND gate U3 is connected with the first end of the resistor R1 and the drain electrode of the MOS tube M1, the second end of the resistor R1 is connected with the power VCC, the source electrode of the MOS tube M1 is grounded, and the gate electrode of the MOS tube M1 is connected with the output end of the inverter U2 through the resistor R2; the output end of the AND gate U3 is connected with the input end of the inverter U2 and serves as the output end of the abnormity holding circuit, and the output end of the abnormity holding circuit is connected with one input end of the microprocessor;
the abnormality detection circuit comprises a light touch switch SW1 and a resistor R6, wherein the first end of the light touch switch SW1 is the output end of the abnormality detection circuit, the output end of the abnormality detection circuit is connected with the input end of the abnormality holding circuit, the first end of the light touch switch SW1 is connected with a power supply VCC through the resistor R6, and the second end of the light touch switch SW1 is grounded.
2. A tamper detection circuit according to claim 1, wherein: the output of the exception holding circuit is connected to one input of the microprocessor through a resistor R3.
3. A tamper detection circuit according to claim 1, wherein: the abnormal holding circuit further comprises a releasing circuit used for controlling the abnormal holding circuit to release the holding state, the input end of the releasing circuit is connected with one output end of the microprocessor, and the output end of the releasing circuit is connected with the grid electrode of the MOS tube M1.
4. A tamper detection circuit according to claim 3, wherein: the release circuit comprises a resistor R4 and a MOS tube M2; the gate of the MOS transistor M2 is connected to the first terminal of the resistor R4 and serves as the input terminal of the release circuit, the drain of the MOS transistor M2 serves as the output terminal of the release circuit, and the source of the MOS transistor M2 is connected to the second terminal of the resistor R4 and is grounded.
5. A tamper detection circuit according to claim 3 or 4, wherein: the input of the deactivation circuit is connected to an output of the microprocessor through a resistor R5.
6. A tamper detection circuit according to claim 1, wherein: the abnormality detection circuit further comprises a resistor R7, a first end of the resistor R7 is connected with a common end of the tact switch SW1 and the resistor R6, and a second end of the resistor R7 is connected with one input end of the microprocessor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120339104.0U CN215493862U (en) | 2021-02-05 | 2021-02-05 | Anti-dismantling detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120339104.0U CN215493862U (en) | 2021-02-05 | 2021-02-05 | Anti-dismantling detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215493862U true CN215493862U (en) | 2022-01-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120339104.0U Active CN215493862U (en) | 2021-02-05 | 2021-02-05 | Anti-dismantling detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN215493862U (en) |
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2021
- 2021-02-05 CN CN202120339104.0U patent/CN215493862U/en active Active
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