CN215449506U - Testing device for power supply chip - Google Patents
Testing device for power supply chip Download PDFInfo
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- CN215449506U CN215449506U CN202121183872.8U CN202121183872U CN215449506U CN 215449506 U CN215449506 U CN 215449506U CN 202121183872 U CN202121183872 U CN 202121183872U CN 215449506 U CN215449506 U CN 215449506U
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Abstract
The utility model discloses a testing device for a power supply chip. The testing device of the power supply chip comprises: the power supply simulation module, the load simulation module and the control module; the power supply chip is connected between the power supply simulation module and the load simulation module; the control module controls the power supply simulation module to access different quantities of direct current power supplies so as to output pulse voltage; and/or the control module controls the load simulation module to be connected with different numbers of resistors so as to enable the load simulation module to flow pulse current. The utility model can simulate and evaluate the functional parameters of the power supply chip and realize the efficient and convenient test of the power supply chip.
Description
Technical Field
The embodiment of the utility model relates to the technical field of display, in particular to a testing device for a power supply chip.
Background
With the continuous development of display technology, people have higher and higher requirements on display panels. In the display module, the parameter conditions of the power signals such as ELVDD and ELVSS directly affect the display effect of the module. The Power signal lines of the conventional display panel, such as an OLED display panel, are powered by an external Power chip (Power IC), and the functional parameters of the Power IC directly affect the ripples of the Power signal output by the Power chip, so it is necessary to confirm the functional parameters of the Power IC in advance. However, the transient function of the Power IC in the market at present is basically integrated instruments and equipment, so that the Power IC is heavy and inconvenient to carry for testing, and the problem of use limitation exists.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a testing device of a power supply chip, which is used for simulating and evaluating functional parameters of the power supply chip and realizing efficient and convenient testing of the power supply chip.
In order to achieve the technical purpose, the embodiment of the utility model provides the following technical scheme:
a test apparatus of a power supply chip, comprising:
the power supply chip is connected between the power supply simulation module and the load simulation module;
the control module controls the power supply simulation module to access different quantities of direct current power supplies so as to output pulse voltage; and/or the control module controls the load simulation module to be connected with different numbers of resistors so as to enable the load simulation module to flow pulse current.
Optionally, the power supply simulation module includes:
n-stage direct-current power supplies connected in series, wherein n is more than or equal to 2; the direct current power supply comprises a first pole and a second pole, and the first pole of the 1 st level direct current power supply is connected with reference voltage;
and the first superposition unit comprises a voltage output end and n voltage input ends, the n voltage input ends are electrically connected with the second poles of the n-level direct-current power supplies in a one-to-one correspondence manner, and the voltage output end is electrically connected with the power chip.
Optionally, the first superimposing unit includes:
the first poles of the n-1 first diodes are respectively and correspondingly electrically connected with the second poles of the first n-1 stages of direct current power supplies in a one-to-one manner;
the grid electrode of the first transistor is electrically connected with the control module, the first n-2 first transistors are connected between the second poles of two adjacent first diodes in series, the first pole of the n-1 first transistor is electrically connected with the second pole of the nth-stage direct-current power supply, and the second pole of the n-1 first transistor is electrically connected with the second pole of the n-1 first diode.
Preferably, the first superimposing unit further includes an nth first diode, and a first pole of the nth first diode is electrically connected to a second pole of the nth dc power supply; a second pole of the nth first diode is electrically connected to the first pole of the (n-1) th first transistor.
Preferably, the first superimposing unit further includes n-1 first resistors connected in series between the control module and the gate of the first transistor.
Preferably, n is 2, and the power supply simulation module comprises a first direct current power supply and a second direct current power supply; the first superposition unit comprises a first diode and a first transistor;
a first pole of the first direct current power supply is connected to the reference voltage, and a second pole of the first direct current power supply is respectively connected with a first pole of the first diode and a first pole of the second direct current power supply; the first pole of the first transistor is electrically connected with the second pole of the second direct current power supply, the second pole of the first transistor is electrically connected with the second pole of the first diode, and the grid electrode of the first transistor is electrically connected with the control module.
Optionally, the power supply simulation module further includes: the direct-current power supply and the second superposition unit are connected with the 2 nd-stage direct-current power supply in parallel;
the DC power supply connected in parallel with the DC power supply of the 2 nd stage comprises: k stages of third direct current power supplies are connected in series, wherein k is more than or equal to 1; the third direct current power supply comprises a first pole and a second pole, and the first pole of the third direct current power supply of the 1 st stage is electrically connected with the second pole of the direct current power supply of the 1 st stage;
the second superposition unit comprises a voltage output end and k +1 voltage input ends, the 1 st voltage input end of the second superposition unit is electrically connected with the first pole of the first-level third direct-current power supply, the 2 nd to k +1 th voltage input ends of the second superposition unit are electrically connected with the second poles of the k-level third direct-current power supply in a one-to-one correspondence manner, and the voltage output end of the second superposition unit is electrically connected with the power chip.
Preferably, the second superimposing unit includes:
the first poles of the k second diodes are respectively and correspondingly electrically connected with the first poles of the kth-level third direct-current power supply one by one;
the grid electrodes of the k second transistors are electrically connected with the control module, the first k-1 second transistors are connected between the second poles of two adjacent second diodes in series, the first pole of the kth second transistor is electrically connected with the second pole of the kth-stage third direct-current power supply, and the second pole of the kth second transistor is electrically connected with the second pole of the kth second diode.
Preferably, the second superimposing unit further includes k second resistors, and the second resistors are connected in series between the control module and the gate of the second transistor.
Preferably, the 1 st second diode is shared with the 1 st first diode.
Optionally, the power supply simulation module includes:
j level DC power supply, j is more than or equal to 2; the direct current power supply comprises a first pole and a second pole, and the first pole of the 1 st level direct current power supply is connected with reference voltage;
the third superposition unit comprises a unidirectional subunit and j-1 switch subunits; the j-1 switch subunits are connected in series between the j-level direct current power supplies; the unidirectional subunit comprises a voltage output end and j voltage input ends, and the ith voltage input end of the unidirectional subunit is connected between the second pole of the ith level of the direct-current power supply and the first pole of the (i + 1) th level of the direct-current power supply; wherein i is more than or equal to 1 and less than or equal to j-1; the jth voltage input end of the unidirectional subunit is electrically connected with the second pole of the jth level direct-current power supply, or the jth voltage input end of the unidirectional subunit is electrically connected with the jth-1 switch subunit; and the voltage output end of the unidirectional subunit is used as the output end of the power supply simulation module and is electrically connected with the power supply chip.
Optionally, the switch subunit comprises a third transistor; the grid electrode of the third transistor is electrically connected with the control module; the mth third transistor is connected in series between the second pole of the mth level direct current power supply and the first level of the (m + 1) th level direct current power supply; or, the mth third transistor is connected in series between the second pole of the (m + 1) th stage direct-current power supply and the first pole of the (m + 2) th stage direct-current power supply; wherein m is more than or equal to 1 and less than or equal to j-2; the j-1 th third transistor is connected in series between the second pole of the j-1 th stage direct current power supply and the first pole of the j-1 th stage direct current power supply; or a first pole of a j-1 th third transistor is electrically connected with a second pole of the j-th level direct current power supply, and a second pole of the j-1 th third transistor is electrically connected with a j-th voltage input end of the unidirectional sub-unit;
the unidirectional subunit includes: and the first pole of the ith third diode is connected between the second pole of the ith level of direct current power supply and the first pole of the (i + 1) th level of direct current power supply, and the second poles of the j-1 third diodes are in short circuit and are used as the voltage output end of the unidirectional subunit.
Preferably, the switch subunit further includes a third resistor, and the third resistor is connected in series between the control module and the gate of the third transistor.
Optionally, the power supply simulation module further includes:
and the voltage stabilizing unit comprises a first end and a second end, the first end of the voltage stabilizing unit is connected to the reference voltage, and the second end of the voltage stabilizing unit is electrically connected with the output end of the power supply simulation module. Therefore, the power supply voltage output by the power supply simulation module can be maintained, so that the power supply voltage is closer to the pulse voltage, and the test accuracy is improved.
Preferably, the voltage stabilization unit includes: and the first end of the capacitor is connected to the reference voltage, and the second end of the capacitor is electrically connected with the output end of the power supply simulation module.
Optionally, the load simulation module includes:
q first impedance units connected in parallel, wherein q is more than or equal to 2; the first impedance units comprise input ends and connecting ends, and the input ends of the q first impedance units are in short circuit and serve as the input ends of the load simulation module;
the parallel unit comprises q-1 connecting ends and q-1 reference ends; the q-1 connecting ends of the parallel units are electrically connected with the connecting ends of the 2 nd to q th first impedance units in a one-to-one correspondence manner; and the connection end of the first impedance unit and the q-1 reference ends of the parallel unit are connected with reference voltage.
Optionally, the parallel unit includes:
the grid electrode of the fourth transistor is electrically connected with the control module, the first poles of the q-1 fourth transistors are electrically connected with the connection ends of the 2 nd to q fourth impedance units in a one-to-one correspondence mode, and the second poles of the q-1 fourth transistors are connected with the reference voltage in an access mode.
Preferably, the parallel unit further includes: a fourth resistor connected in series between the control module and the gate of the fourth transistor.
Preferably, the parallel unit further includes: a q-th fourth transistor; the grid electrode of the q-th fourth transistor is electrically connected with the control module, the first pole of the q-th fourth transistor is electrically connected with the connecting end of the 1 st first impedance unit, and the second pole of the q-th fourth transistor is connected with the reference voltage.
Optionally, the load simulation module includes:
s second impedance units connected in series, wherein s is more than or equal to 2; the second impedance unit comprises an input end and a connecting end, the input end of the 1 st second impedance unit is used as the input end of the load simulation module, and the connecting end of the s-th second impedance unit is connected with a reference voltage;
and the s-1 series units are connected with the 2 nd to s th second impedance units in parallel in a one-to-one correspondence manner.
Preferably, the series unit includes: a fifth transistor, a gate of which is electrically connected with the control module; the first poles of the s-1 fifth transistors are electrically connected with the input ends of the 2 nd to s th second impedance units in a one-to-one correspondence mode, and the second poles of the s-1 fifth transistors are electrically connected with the connection ends of the 2 nd to s th second impedance units in a one-to-one correspondence mode.
Preferably, the series unit further comprises: a fifth resistor connected in series between the control module and the gate of the fifth transistor.
The power supply simulation module is arranged in the testing device of the power supply chip provided by the embodiment of the utility model, the number of direct current power supplies for supplying power to the power supply chip can be changed under the control of the control module, and the power supply voltages with different amplitudes are output in a pulse voltage mode, so that different power supply voltages are simulated, and the output voltages of the power supply chip in different power supply states are measured. The rising edge and the falling edge of the pulse voltage can simulate the transient state of the power supply voltage of the power supply chip, and the transient ripple of the output voltage of the power supply chip is measured. Moreover, the test device is provided with a load simulation module which can change the number of the resistors connected into the test device under the control of the control module; the load current in a pulse form is obtained by changing the load, so that the load change condition when the brightness or gray scale and the like are changed when the tested power supply chip is connected into the display module can be simulated, and the output voltage of the power supply chip under different load states can be measured. The testing device provides variable power supply voltage and/or variable load in a simulation mode by accessing different numbers of power supplies and/or resistors, so that the device is simple in structure, easy to implement, convenient to debug and convenient to carry. Therefore, the embodiment of the utility model can simulate and evaluate the functional parameters of the power supply chip and realize efficient and convenient test of the power supply chip.
Drawings
Fig. 1 is a schematic structural diagram of a testing apparatus for a power chip according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a power supply simulation module according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another power supply simulation module according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another power supply simulation module according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another testing apparatus for a power chip according to an embodiment of the present invention;
fig. 6 is a schematic control timing diagram of a power supply simulation module according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another power supply simulation module according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of another power supply simulation module according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of another power supply simulation module according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of another power supply simulation module according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of a load simulation module according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of another load simulation module according to an embodiment of the present invention;
fig. 13 is a schematic structural diagram of another load simulation module according to an embodiment of the present invention;
fig. 14 is a schematic structural diagram of a testing apparatus for a power chip according to another embodiment of the present invention;
fig. 15 is a schematic control timing diagram of a load simulation module according to an embodiment of the present invention;
fig. 16 is a schematic structural diagram of another load simulation module according to an embodiment of the present invention;
fig. 17 is a schematic structural diagram of another load simulation module according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the utility model and are not limiting of the utility model. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
The embodiment of the utility model provides a testing device of a power supply chip, which can be a power supply chip in a display device. Fig. 1 is a schematic structural diagram of a testing apparatus for a power chip according to an embodiment of the present invention. Referring to fig. 1, the testing apparatus of the power chip includes: a power supply simulation module 10, a load simulation module 20 and a control module 40. The power supply chip 30 is connected between the power supply simulation module 10 and the load simulation module 20; the control module 40 controls the power supply simulation module 10 to access different numbers of direct current power supplies so as to output pulse voltage; and/or the control module 40 controls the load simulation module 20 to switch in different numbers of resistors so that the load simulation module 20 flows the pulse current.
The power supply simulation module 10 may include a plurality of dc power supplies and a superimposing unit, and the control module 40 may determine the number of the dc power supplies for output by controlling the superimposing unit. The plurality of direct current power supplies can be power supplies with fixed output voltage or adjustable power supplies; the output amplitude of different direct current power supplies can be different, and the output amplitude can be specifically set according to actual requirements. The load simulation module 20 may include a plurality of resistors and a series unit (or a parallel unit), the control module 40 may control the number of resistors constituting the effective load by controlling the series unit (or the parallel unit), each resistor may be connected in parallel, in series, or in combination of series and parallel, and the resistance value of each resistor may be selected according to actual requirements. The control module 40 may be arranged as shown in fig. 1, and the testing apparatus includes an integrated control module 40 for controlling both the supply voltage output by the supply simulation module 10 and the load generated by the load simulation module 20. Alternatively, the control module 40 may include two control units operating independently for controlling the states of the power supply simulation module 10 and the load simulation module 20, respectively.
Illustratively, the test mode of the test device is as follows:
1) the number of the dc power supplies for outputting the power supply voltage in the power supply simulation module 10 is changed, so that the power supply simulation module 10 outputs the pulse voltage, and the rising edge or the falling edge thereof can be used for simulating a transient state in which the power supply of the power supply chip 30 jumps or jitters during actual application. That is, a linear Transient response (Line Transient) test for the power supply chip 30 may be implemented by changing the output of the power supply simulation module 10. The transient ripple of the output voltage of the power supply chip 30 can be obtained by obtaining the output voltage, so as to evaluate the ripple variation of the output voltage of the power supply chip 30. The output voltage of the power chip 30 may be detected by a voltage detection device, and the voltage detection device may be connected between the output terminal of the power chip 30 and a reference voltage terminal (e.g., a ground terminal). Illustratively, the voltage detection device may employ a multimeter, an oscilloscope, or a dedicated voltage detection device, or the like.
2) Changing the number of the access resistors in the load simulation module 20 can make the load current flowing through the load simulation module to be in a state of pulse current. For example, when the resistors in the load simulation module 20 are all in parallel, the more resistors are connected in parallel, the smaller the equivalent resistance value is, i.e., the smaller the load is, the larger the load current is. Therefore, by reasonably setting the connection mode of the resistors, the change of the resistors of the access device can simulate the change condition of the load carried by the power chip 30, so that the power chip 30 outputs the pulse current. The output current of the power supply chip can be detected by a current detection device, and the current detection device can be connected in series with the load simulation module 20. For example, the current detection device may be a multimeter, an oscilloscope, or a dedicated current detection device. The current detection device may also be a current transformer, and detects the current at the output end of the power supply chip 30 in an electromagnetic induction manner. That is, a Load Transient response (Load Transient) test for the power chip 30 may be implemented by changing the number of access resistors in the Load simulation module 20. The transient ripple of the output voltage of the power supply chip 30 can be obtained by obtaining the output voltage, so as to evaluate the ripple variation of the output voltage of the power supply chip 30.
It should be noted that, in a test apparatus, only the power supply simulation module 10 provided by the present invention may be included, only the load simulation module 20 provided by the present invention may be included, or both of them may be included, and the present invention is not limited to this.
The power supply simulation module 10 is arranged in the testing device of the power supply chip provided by the embodiment of the utility model, the number of direct current power supplies for supplying power to the power supply chip 30 can be changed under the control of the control module 40, and the power supply voltages with different amplitudes are output in the form of pulse voltage, so that different power supply voltages are simulated, and the output voltage of the power supply chip 30 in different power supply states is measured. The rising edge and the falling edge of the pulse voltage can both simulate the transient state of the power supply voltage of the power supply chip 30, so as to measure the transient ripple of the output voltage of the power supply chip 30. The testing device is provided with a load simulation module 20, and the number of resistors connected into the testing device can be changed under the control of a control module 40; the pulse-form load current is obtained by changing the load, so that the load change condition when the brightness or gray scale and the like are changed when the tested power supply chip 30 is connected into the display module can be simulated, and the output voltage of the power supply chip 30 under different load states can be measured. The testing device provides variable power supply voltage and/or variable load in a simulation mode by accessing different numbers of power supplies and/or resistors, so that the device is simple in structure, easy to implement, convenient to debug and convenient to carry. Therefore, the embodiment of the utility model can simulate and evaluate the functional parameters of the power supply chip 30 when the power supply voltage changes and/or the load changes, and realize the efficient and convenient test of the power supply chip 30.
In addition to the above embodiments, the power supply simulation module may have a plurality of configurations, and some of them will be described below, but the present invention is not limited thereto.
Fig. 2 is a schematic structural diagram of a power supply simulation module according to an embodiment of the present invention. Referring to fig. 2, in one embodiment, the power supply simulation module 10 optionally includes: the first superposition unit 110 and the series-connected n-stage direct-current power supply DC, n is more than or equal to 2. The direct current power supply DC comprises a first pole and a second pole, and the first pole of the 1 st level direct current power supply DC is connected to a reference voltage. Illustratively, the first pole of the dc power source is a negative pole and the second pole is a positive pole. The first superimposing unit 110 includes a voltage output end 111 and n voltage input ends, where the n voltage input ends are electrically connected to the second poles of the n-level DC power supplies DC in a one-to-one correspondence; the voltage output terminal 111 is electrically connected to the power supply chip and supplies a supply voltage Vout to the power supply chip.
In fig. 2, the 1 st to nth stages of the direct current power DC are exemplarily sequentially arranged in the order from bottom to top. The reference voltage may be set to a ground voltage.
With continued reference to fig. 2, on the basis of the foregoing embodiments, optionally, the first superimposing unit 110 includes n-1 control terminals, which are electrically connected to the control module 40, so as to implement control on whether the 2 nd to n th DC power supplies DC are superimposed on the first DC power supply DC.
Alternatively, the first superimposing unit 110 includes a converting subunit and 1 control terminal, and the control terminals are electrically connected to the control module 40 and the converting subunit, respectively. The control signal output by the control module 40 is converted by the control subunit and then transmitted to the switches corresponding to the DC power supplies DC of each stage. The structure has no limit to the number of output ports of the control module 40 and the number of stages of the series-connected direct current power supplies DC.
Fig. 3 is a schematic structural diagram of another power supply simulation module according to an embodiment of the present invention. Referring to fig. 3, in one embodiment, the first superimposing unit 110 optionally includes: n-1 first transistors M1 and at least n-1 first diodes D1. First poles of the n-1 first diodes D1 are electrically connected with second poles of the 1 st-stage direct current power supplies DC in a one-to-one correspondence mode respectively; the second pole of the 1 st first diode D1 serves as the voltage output terminal of the first superimposing unit 110. The gate of the first transistor M1 is electrically connected to the control module 40, the first n-2 first transistors M1 are connected in series between the second poles of two adjacent first diodes D1, the first pole of the n-1 first transistor M1 is electrically connected to the second pole of the nth DC power source DC, and the second pole of the n-1 first transistor M1 is electrically connected to the second pole of the n-1 first diode D1.
In this embodiment, the first superimposing unit 110 is configured to include the first diode D1, so that unidirectional output of the output voltage of each stage of the DC power supply DC can be ensured. Illustratively, the first pole of the DC power source DC is a negative pole and the second pole is a positive pole, and accordingly, the first pole of the first diode D1 is an anode and the second pole is a cathode. The first transistor M1 is arranged to be used as a switch for controlling whether the 2 nd to n-th-stage direct-current power supplies DC participate in output, so that the circuit structure is simple; the control module 40 can control the on/off of the first transistor M1 through a Pulse Width Modulation (PWM) control method, so as to control the power supply simulation module 10 to output a Pulse voltage, and the control logic is easy to implement. The rising edge or the falling edge of the pulse voltage can be used for simulating the condition that the supply voltage changes suddenly.
With continued reference to fig. 3, in each of the above embodiments, optionally, the power supply simulation module 10 further includes: and a voltage stabilization unit 140. The voltage stabilizing unit 140 includes a first end and a second end, the first end is connected to a reference voltage (ground), and the second end is electrically connected to an output end of the power supply simulation module 140. By means of the arrangement, the voltage of the output of the power supply simulation module 10 can be maintained, so that the power supply voltage Vout can approach the pulse voltage more, and the test accuracy is improved.
Fig. 4 is a schematic structural diagram of another power supply simulation module according to an embodiment of the present invention. Referring to fig. 4, in an embodiment, the first superimposing unit 110 further includes an nth first diode D1, i.e., the uppermost first diode D1 in fig. 4, optionally to ensure unidirectionality of the DC output voltage of the nth DC power source. A first pole of the nth first diode D1 is electrically connected to a second pole of the nth stage direct current power source DC; the second pole is electrically connected to the first pole of the (n-1) th first transistor M1.
With continued reference to fig. 4, based on the above embodiments, optionally, the first superimposing unit 110 further includes n-1 first resistors R1, and the first resistor R1 is connected in series between the control module 40 and the gate of the first transistor M1. The first resistor R1, as a gate resistor of the first transistor M1, has the functions of eliminating gate oscillation, adjusting the rising and falling edges of the first transistor M1, adjusting the switching speed of the first transistor M1, and the like, and can make the device more controllable and reliable.
With continued reference to fig. 4, on the basis of the above embodiments, the voltage stabilizing unit 140 optionally includes: the first end of the capacitor C1 and the first end of the capacitor C1 are connected with a reference voltage, and the second end of the capacitor C2 is electrically connected with the output end of the power supply simulation module 10. The capacitor C1 is used as the voltage stabilizing unit 140, so that the structure of the voltage stabilizing unit 140 is simple and easy to realize. And the capacitor C1 also has a certain filtering function, so that the power supply voltage Vout output by the power supply simulation module 10 is closer to the pulse voltage, the simulation effect of the linear transient state is better, and the accuracy of the testing device is improved.
Fig. 5 is a schematic structural diagram of another testing apparatus for a power chip according to an embodiment of the present invention;
fig. 6 is a schematic control timing diagram of a power supply simulation module according to an embodiment of the present invention. Next, referring to fig. 5 and 6, a specific operation of the power supply simulation module 10 will be described by taking an example in which the power supply simulation module 10 includes two stages of dc power supplies (n is 2).
Referring to fig. 5, the power supply simulation module 10 includes a first direct current power supply DC1 and a second direct current power supply DC 2; the first superposition unit 110 includes a first diode D1, a first transistor M1, and a first resistor R1; the control module 40 includes a power supply control unit 410. A first pole of the first direct current power supply DC1 is connected to a reference voltage, and a second pole of the first direct current power supply DC1 is electrically connected with a first pole of the first diode D1 and a first pole of the second direct current power supply DC2 respectively; a first pole of the first transistor M1 is electrically connected to a second pole of the second DC power DC2, a second pole of the first transistor M1 is electrically connected to a second pole of the first diode D1, and a gate of the first transistor M1 is electrically connected to the power supply control unit 410 through a first resistor R1.
For example, referring to fig. 5 and fig. 6, taking two stages of dc power supplies as both the power supplies with fixed output voltage and the first transistor M1 as an N-type MOS transistor (conducting when the gate inputs a high level), the principle of the linear transient response test of the test apparatus includes: the power supply control unit 410 may control the output control signal S1 by PWM.
Specifically, when the control signal S1 is at a low level, the first transistor M1 is turned off, the transmission path of the second DC power supply DC2 is cut off, and the voltage of the first DC power supply DC1 is output through the first diode D1.
When the control signal S1 is at a high level, the first transistor M1 is turned on, the transmission path of the second DC power supply DC2 is turned on, and the output voltage of the second DC power supply DC2 is superimposed on the output voltage of the first DC power supply DC 1; the supply voltage output by the supply simulation module 10 is the sum of the voltages of the first DC power supply DC1 and the second DC power supply DC 2. Meanwhile, the voltage of the first pole of the first diode D1 is lower than that of the second pole thereof, and the first diode D1 is turned off, preventing the voltage from being transmitted reversely.
In summary, through PWM control, a pulse voltage can be output at the output end of the power supply analog module 10; among the pulse voltages, the low level is DC1, and the high level is DC1+ DC 2. The pulse waveform serves as an input voltage of the power supply chip 30. During the test, the transient ripple of the output voltage of the power chip 30 may be measured at the output terminal of the power chip 30 or the input terminal of the load simulation module 20. Illustratively, the voltage of the first direct current power supply DC1 is greater than the voltage of the second direct current power supply DC 2; the pressure difference between the two can be selected according to actual requirements, and is set to be 0.5V for example. The voltage of the first direct-current power supply DC1 is relatively large, and can be simulated as a normal operating voltage provided by the power supply chip 30; for example, 3.7V for the output voltage of the battery in the display device. The voltage of the second direct current power supply DC2 is small, and can be superposed on the first direct current power supply DC1 to simulate the transient amount of the power supply voltage; for example, set to 0.5V.
In the embodiment of the present invention, the power supply simulation module 10 only includes the first DC power supply DC1 and the second DC power supply DC2, and thus the requirement of the power supply simulation module 10 for outputting the pulse voltage can be met under the condition of the simplest circuit structure and the simplest control method.
Fig. 7 is a schematic structural diagram of another power supply simulation module according to an embodiment of the present invention, and in fig. 7, for easy distinction and representation, the 1 st-stage DC power supply is referred to as a first DC power supply DC1, and the remaining 2 nd to n nd-stage DC power supplies are referred to as a second DC power supply DC2, among n-stage DC power supplies connected in series and having the same structure as in the foregoing embodiments. Referring to fig. 7, on the basis of the above embodiments, optionally, the power supply simulation module 10 further includes: a dc power supply connected in parallel with the 2 nd stage dc power supply, and a second superimposing unit 120. The direct current power supply connected with the 2 nd-stage direct current power supply DC2 in parallel comprises: the k-level third direct-current power supply DC3 is connected in series, wherein k is more than or equal to 1; in fig. 7, the third direct current power supply DC3 of the 1 st to k-th stages is sequentially arranged in the top-down direction. The third DC power supply DC3 includes a first pole and a second pole, and the first pole of the stage 1 third DC power supply DC3 is electrically connected to the second pole of the stage 1 DC power supply (first DC power supply DC 1). The second superimposing unit 120 includes voltage output terminals and k +1 voltage input terminals, the 1 st voltage input terminal of the second superimposing unit 120 is electrically connected to the first pole of the first-stage third DC power supply DC3, the 2 nd to k +1 th voltage input terminals of the second superimposing unit 120 are electrically connected to the second poles of the 1 st to k th-stage third DC power supplies DC3 in a one-to-one correspondence, and the voltage output terminal of the second superimposing unit 120 is electrically connected to the power chip.
Similar to the connection relationship between the second DC power supply DC2 and the first superimposing unit 110, the third DC power supply DC3 and the second superimposing unit 120 can also function to change the output of the power supply analog module 10, and the two parts are connected in parallel and can be regarded as two independent structures. Under the control of the control module 40, the two may each implement a step-wise superposition on the first direct current power supply DC 1. Therefore, the voltages of the second DC power supply DC2 and the third DC power supply DC3 can be set to be different, and the control module 40 can select which set of series structure is used to be superimposed on the first DC power supply DC1 according to the requirement, so as to enrich the number of output voltage values.
With continued reference to fig. 7, on the basis of the above embodiments, optionally, the second superimposing unit 120 includes: the k second transistors M2 and at least k second diodes D2, first poles of the k second diodes D2 are respectively and electrically connected with first poles of the kth-stage third direct-current power supply DC3 in a one-to-one correspondence manner; the gates of the second transistors M2 are electrically connected to the control module 40, the first k-1 second transistors M2 are connected in series between the second poles of two adjacent second diodes D2, the first pole of the kth second transistor D2 is electrically connected to the second pole of the kth stage third DC power source DC3, and the second pole of the kth second transistor M2 is electrically connected to the second pole of the kth second diode D2. Further, the second superimposing unit 120 further includes k second resistors R2, and the second resistors R2 are connected in series between the control module 40 and the gate of the second transistor M2. The structure of the second stacking unit 120 is similar to the structure of the first stacking unit 110, and for the specific operation principle and the beneficial effects, reference is made to the description of the first stacking unit 110, which is not repeated herein. In which a 1 st first diode D1 and a 1 st second diode D2 are electrically connected to a first direct current power source DC1, and the two diodes are connected in parallel. Therefore, one of the diodes may be omitted so that the number of diodes electrically connected to the first direct current power supply DC1 is one to simplify the circuit structure.
Fig. 8 is a schematic structural diagram of another power supply simulation module according to an embodiment of the present invention. Referring to fig. 8, a specific structure and a control principle of the power supply analog module will be described with n being 2 and k being 1 as examples. The power supply analog-to-digital module 10 includes a first DC power supply DC1, a second DC power supply DC2, a third DC power supply DC3, a first transistor M1, a second transistor M2, a first diode D1 (a second diode D2), a first resistor R1, and a second resistor R2. The second direct-current power supply DC2 is connected in parallel with the third direct-current power supply DC3 and then connected in series with the first direct-current power supply DC 1. When the directions of the second DC power DC2 and the third DC power DC3 are the same, the 1 st-stage first diode D1 and the 1 st-stage second diode D2 may be shared to simplify the structure of the power supply simulation module 10.
Illustratively, the control principle of the power supply simulation module 10 includes:
when the first transistor M1 and the second transistor M2 are controlled to be turned off, the transmission paths of the second direct current power supply DC2 and the third direct current power supply DC3 are cut off, and the power supply simulation module 10 outputs the voltage of the first direct current power supply DC 1. When the first transistor M1 is controlled to be closed and the second transistor M2 is controlled to be turned off, the transmission path of the second direct current power supply DC2 is turned on, the transmission path of the third direct current power supply DC3 is cut off, and the power supply simulation module 10 outputs the sum of the voltages of the first direct current power supply DC1 and the second direct current power supply DC 2. When the first transistor M1 is controlled to be turned off and the second transistor M2 is controlled to be turned on, the transmission path of the second DC power supply DC2 is cut off, the transmission path of the third DC power supply DC3 is turned on, and the power supply simulation module 10 outputs the sum of the voltages of the first DC power supply DC1 and the third DC power supply DC 3. Wherein the second direct current power supply DC2 and the third direct current power supply DC3 may set different voltage values.
Fig. 9 is a schematic structural diagram of another power supply simulation module according to an embodiment of the present invention. Referring to fig. 9, in one embodiment, the power supply simulation module 10 optionally includes: and j is more than or equal to 2 when the third superposition unit and the j-level direct-current power supply DC are used. In fig. 9, the 1 st to j-th stages of the direct current power DC are sequentially arranged in a bottom-up direction. The direct current power supply DC comprises a first pole and a second pole, and the first pole of the 1 st level direct current power supply DC is connected to a reference voltage (grounded); the third stacking unit comprises a unidirectional subunit 132 and j-1 switching subunits 131; j-1 switch subunits 131 are connected in series between j stages of direct current power supplies DC; the unidirectional subunit 132 comprises a voltage output end and j voltage input ends, wherein the ith voltage input end of the unidirectional subunit 132 is connected between the second pole of the ith level direct current power supply DC and the first pole of the (i + 1) th level direct current power supply DC; wherein i is more than or equal to 1 and less than or equal to j-1; the jth voltage input end of the unidirectional subunit 132 is electrically connected with the second pole of the jth level direct current power supply DC, or the jth voltage input end of the unidirectional subunit 132 is electrically connected with the j-1 th switch subunit 131; the voltage output end of the unidirectional subunit 132 serves as the output end of the power supply analog module 10, and is electrically connected with the power supply chip.
Except the 1 st level DC power supply, each of the other DC power supplies has a switch subunit 131 connected in series with it; the switch subunit 131 may be disposed above the DC power supply DC, or may be disposed below the DC power supply DC, which is not limited herein.
Optionally, the switch subunit 131 further includes a control terminal electrically connected to the control module 40. The control module 40 can control the number of stages of the DC power DC superimposed on the 1 st stage DC power DC by controlling the on/off of the switch subunit 131.
Fig. 10 is a schematic structural diagram of another power supply simulation module according to an embodiment of the present invention. Referring to fig. 10, in one embodiment, optionally, the switch subunit 131 includes a third transistor M3; the gate of the third transistor M3 is electrically connected to the control module 40; the mth third transistor M3 is connected in series between the second pole of the mth stage direct current power supply DC and the first stage of the (M + 1) th stage direct current power supply DC; alternatively, the mth third transistor M3 is connected in series between the second pole of the (M + 1) th stage direct current power supply DC and the first pole of the (M + 2) th stage direct current power supply DC; wherein m is more than or equal to 1 and less than or equal to j-2; the j-1 th third transistor M3 is connected in series between the second pole of the j-1 th stage direct current power supply DC and the first pole of the j-1 th stage direct current power supply DC; alternatively, the first pole of the j-1 th third transistor M3 is electrically connected to the second pole of the j-th stage DC power DC, and the second pole of the j-1 th third transistor M3 is electrically connected to the j-th voltage input terminal of the unidirectional sub-unit 132. The switch subunit 131 is configured to include only one third transistor M3, so that the switch subunit 131 has a simple structure, is easy to implement, and is easy to control.
Optionally, the switch subunit 131 further includes a third resistor R3, and the third resistor R3 is connected in series between the control module 40 and the gate of the third transistor M3, and is used as the gate resistor of the third transistor M3.
The unidirectional sub-unit 132 includes j-1 third diodes D3, a first pole of the ith third diode D3 is connected between a second pole of the ith stage DC power supply DC and a first pole of the (i + 1) th stage DC power supply DC, and a second pole of the j-1 third diode D3 is shorted and serves as a voltage output terminal of the unidirectional sub-unit 132. The arrangement is such that the unidirectional sub-unit 132 has a simple structure and is easy to implement. Optionally, the unidirectional sub-unit 132 may further include a jth third diode D3 connected to the second pole of the jth stage DC power DC to avoid the parallel connection of different DC power DC, so as to ensure unidirectional output.
As can be seen from fig. 10, the difference from the foregoing embodiments is that the switch subunit is arranged at a different position, and the principle of implementing the dc power supply superposition is the same as that of the foregoing embodiments, and is not described again here.
The above embodiments exemplarily explain structures that the power supply simulation module may have. The following description is given of a possible structure of the load simulation module, but the present invention is not limited thereto.
Fig. 11 is a schematic structural diagram of a load simulation module according to an embodiment of the present invention. Referring to fig. 11, in one embodiment, the load simulation module 20 optionally includes: a parallel unit 220 and q first impedance units 210 connected in parallel, q ≧ 2. In fig. 11, the 1 st to the q-th first impedance units 210 are sequentially arranged in the left-to-right direction. The first impedance units 210 comprise input ends and connection ends, the input ends of the q first impedance units 210 are short-circuited and serve as the input ends of the load simulation module 20; the parallel unit 220 includes q-1 connection terminals and q-1 reference terminals; q-1 connection terminals of the parallel unit 220 are electrically connected to connection terminals of the 2 nd to q th first impedance units 210 in a one-to-one correspondence; the connection terminal of the first impedance unit 210 and q-1 reference terminals of the parallel unit 220 are both connected to a reference voltage (ground).
The parallel unit 220 may include control branches connected to the 2 nd to q th first impedance units 210 in a one-to-one correspondence manner, and control ends of the control branches are connected to the control module. By changing the number of the control branches that are turned on, the number of the first impedance units 210 that are actually connected in parallel in the load simulation module 20 can be changed, so as to change the equivalent impedance value.
Fig. 12 is a schematic structural diagram of another load simulation module according to an embodiment of the present invention. Referring to fig. 12, in one embodiment, the first impedance unit 210 is optionally formed by a first load resistor R11. The parallel unit 220 includes: the q-1 fourth transistor M4, the gate of the fourth transistor M4 is electrically connected to the control module 40, the first pole of the q-1 fourth transistor M4 is electrically connected to the connection terminals of the 2 nd to q fourth impedance units 210 in a one-to-one correspondence, and the second pole of the q-1 fourth transistor M4 is connected to the reference voltage. By means of the arrangement, except for the first impedance unit 210, the other first impedance units 210 are connected in series with one fourth transistor M4, and the number of the first load resistors R11 connected in parallel can be controlled by controlling the on/off of the fourth transistor M4, so that the load simulation module 20 is simple in structure and easy to implement.
With reference to fig. 12, on the basis of the foregoing embodiments, optionally, the load simulation module 20 further includes a filtering unit 250, which is connected in parallel to two ends of the first impedance unit 210, and implements a filtering function on the output voltage Vin of the power chip.
Fig. 13 is a schematic structural diagram of another load simulation module according to an embodiment of the present invention. Referring to fig. 13, on the basis of the above embodiments, optionally, the parallel unit further includes: a qth fourth transistor M4; the gate of the qth fourth transistor M4 is electrically connected to the control module 40, the first pole of the qth fourth transistor M4 is electrically connected to the connection terminal of the 1 st first impedance unit 210, and the second pole of the qth fourth transistor M4 is connected to the reference voltage. The arrangement is such that each first impedance unit 210 is connected in series with one fourth transistor M4, thereby realizing that the analog load can be changed from the minimum equivalent load (all the first load resistors R11 are connected in parallel) to the open circuit, and expanding the adjustment range of the analog load.
With continued reference to fig. 13, on the basis of the above embodiments, optionally, the parallel unit 220 further includes: the fourth resistor R4 is connected in series between the control module 40 and the gate of the fourth transistor M4 as the gate resistor of the fourth transistor M4. Optionally, the filtering unit 250 includes a second capacitor C2, and the second capacitor C2 has a voltage stabilizing function in addition to filtering.
Fig. 14 is a schematic structural diagram of a testing apparatus for a power chip according to another embodiment of the present invention; fig. 15 is a schematic control timing diagram of a load simulation module according to an embodiment of the present invention. Next, referring to fig. 14 and fig. 15, a specific operation of the load simulation module 20 will be described by taking an example in which the load simulation module 20 includes two first impedance units 210(q is 2).
The load simulation module 20 includes: two first load resistors R11, a fourth transistor M4, a fourth resistor R4 and a second capacitor C2. The control module 40 may include a load control unit 420, and the gate of the fourth transistor M4 is electrically connected to the load control unit 420 through a fourth resistor R4. For example, taking the fourth transistor M4 as an N-type MOS transistor (which is turned on when a high level is input to the gate), the load transient response test principle of the test apparatus includes: the load control unit 420 may control the output control signal S2 through PWM.
Specifically, when the control signal S2 is at a low level, the fourth transistor M4 is turned off, and an effective load is formed by only the first load resistor R11, and the load current Iload flowing through the load control unit at this time is denoted as I1. When the control signal S2 is at a high level, the fourth transistor M4 is turned on, the first load resistor R11 and the second first load resistor R11 are connected in parallel to form an effective load, and the load current Iload flowing through the load control unit is denoted as I2. Since the equivalent resistance value is smaller than that of any one of the first load resistors R11 when the load resistors are connected in parallel, I2 is larger than I1. Therefore, through PWM control, the load current Iload can be output in a pulse form; therefore, the load condition of the power chip 30 of the test display panel when the display brightness or gray scale changes after the module is mounted can be simulated, for example, the load condition is switched from a black picture to a white picture or other load change conditions, so that the power supply stability of the power chip 30 can be evaluated. Illustratively, the first load resistor R11 is used as a base load, and a resistor with a larger resistance value can be selected; the second first load resistor R11 is used as a regulated load, and a resistor with a smaller resistance value can be selected.
In the embodiment of the present invention, the load simulation module 20 only includes two first load resistors R11 and one fourth transistor M4, and can meet the requirement that the power supply chip 30 outputs the pulse current due to the load change of the load simulation module 20 under the condition of the simplest circuit structure and the simplest control manner.
The above embodiments exemplify the structure in which the load simulation module 20 is composed of the first impedance units 210 connected in parallel, but the present invention is not limited thereto. The following describes the load simulation module 20 in another configuration. Fig. 16 is a schematic structural diagram of another load simulation module according to an embodiment of the present invention. Referring to fig. 16, in one embodiment, the load simulation module 20 optionally includes: s second impedance units 230 and s-1 series units 240 connected in series, s ≧ 2. In fig. 16, the 1 st to s-th second impedance units 230 are arranged in order from the top down. The second impedance unit 230 includes an input terminal and a connection terminal, the input terminal of the 1 st second impedance unit 230 is used as the input terminal of the load simulation module 20, and the connection terminal of the s-th second impedance unit 230 is connected to the reference voltage; the s-1 series units 240 are connected in parallel with the 2 nd to s th second impedance units 230 in a one-to-one correspondence.
In the load simulation module 20, when the series unit 240 is turned on, the second impedance unit 230 connected in parallel thereto is shorted, not counting the effective load. Therefore, by adjusting the number of the series units 240 that are turned on, the number of the second impedance units 230 that are included in the payload can be controlled.
Fig. 17 is a schematic structural diagram of another load simulation module according to an embodiment of the present invention. Referring to fig. 17, on the basis of the above embodiments, optionally, the second impedance unit 230 includes a second load resistor R12. The serial unit 240 includes: a fifth transistor M5, a gate of the fifth transistor M5 being electrically connected to the control module 40; first poles of the s-1 fifth transistors M5 are electrically connected to the input terminals of the 2 nd to s-th second impedance units 230 in a one-to-one correspondence, and second poles of the s-1 fifth transistors M5 are electrically connected to the connection terminals of the 2 nd to s-th second impedance units 230 in a one-to-one correspondence. The series unit 240 is composed of only one fifth transistor M5, so that the series unit 240 has a simple structure, is easy to implement, and is easy to control.
Optionally, the series unit 240 further includes: the fifth resistor R5 is connected in series between the control module 40 and the gate of the fifth transistor M5 as the gate resistor of the fifth transistor M5.
It should be noted that, in the above embodiments, the case where the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are N-type transistors is exemplified, but the present invention is not limited thereto. In another embodiment, the transistor may be a P-type transistor.
In the above embodiments, the first pole of the dc power supply is a negative pole, and the second pole is a positive pole, which are not intended to limit the present invention. In other embodiments, the first pole of the dc power supply may be a positive pole, and the second pole may be a negative pole; at this time, the direction of each corresponding diode needs to be set correspondingly. Other DC power supplies can also be arranged to be reversely connected with the 1 st level DC power supply so as to simulate the negative fluctuation of the power supply voltage.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the utility model. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (21)
1. A testing device for a power supply chip is characterized by comprising:
the power supply chip is connected between the power supply simulation module and the load simulation module;
the control module controls the power supply simulation module to access different quantities of direct current power supplies so as to output pulse voltage; and/or the control module controls the load simulation module to be connected with different numbers of resistors so as to enable the load simulation module to flow pulse current.
2. The power supply chip testing device according to claim 1, wherein the power supply simulation module comprises:
n-stage direct-current power supplies connected in series, wherein n is more than or equal to 2; the direct current power supply comprises a first pole and a second pole, and the first pole of the 1 st level direct current power supply is connected with reference voltage;
and the first superposition unit comprises a voltage output end and n voltage input ends, the n voltage input ends are electrically connected with the second poles of the n-level direct-current power supplies in a one-to-one correspondence manner, and the voltage output end is electrically connected with the power chip.
3. The power supply chip testing apparatus as claimed in claim 2, wherein the first superimposing unit includes:
the first poles of the n-1 first diodes are respectively and correspondingly electrically connected with the second poles of the first n-1 stages of direct current power supplies in a one-to-one manner;
the grid electrode of the first transistor is electrically connected with the control module, the first n-2 first transistors are connected between the second poles of two adjacent first diodes in series, the first pole of the n-1 first transistor is electrically connected with the second pole of the nth-stage direct-current power supply, and the second pole of the n-1 first transistor is electrically connected with the second pole of the n-1 first diode.
4. The power supply chip testing device as claimed in claim 3, wherein the first superimposing unit further includes an nth first diode, a first pole of which is electrically connected to the second pole of the nth stage DC power supply; a second pole of the nth first diode is electrically connected to the first pole of the (n-1) th first transistor.
5. The power supply chip testing device according to claim 3, wherein the first superimposing unit further includes n-1 first resistors, and the first resistors are connected in series between the control module and the gate of the first transistor.
6. The device for testing the power supply chip according to claim 3, wherein n is 2, and the power supply simulation module comprises a first direct current power supply and a second direct current power supply; the first superposition unit comprises a first diode and a first transistor;
a first pole of the first direct current power supply is connected to the reference voltage, and a second pole of the first direct current power supply is respectively connected with a first pole of the first diode and a first pole of the second direct current power supply; the first pole of the first transistor is electrically connected with the second pole of the second direct current power supply, the second pole of the first transistor is electrically connected with the second pole of the first diode, and the grid electrode of the first transistor is electrically connected with the control module.
7. The power supply chip testing apparatus as claimed in claim 2, wherein the power supply simulation module further comprises: the direct-current power supply and the second superposition unit are connected with the 2 nd-stage direct-current power supply in parallel;
the DC power supply connected in parallel with the DC power supply of the 2 nd stage comprises: k stages of third direct current power supplies are connected in series, wherein k is more than or equal to 1; the third direct current power supply comprises a first pole and a second pole, and the first pole of the third direct current power supply of the 1 st stage is electrically connected with the second pole of the direct current power supply of the 1 st stage;
the second superposition unit comprises a voltage output end and k +1 voltage input ends, the 1 st voltage input end of the second superposition unit is electrically connected with the first pole of the first-level third direct-current power supply, the 2 nd to k +1 th voltage input ends of the second superposition unit are electrically connected with the second poles of the k-level third direct-current power supply in a one-to-one correspondence manner, and the voltage output end of the second superposition unit is electrically connected with the power chip.
8. The power supply chip testing apparatus as claimed in claim 7, wherein the second superimposing unit includes:
the first poles of the k second diodes are respectively and correspondingly electrically connected with the first poles of the kth-level third direct-current power supply one by one;
the grid electrodes of the k second transistors are electrically connected with the control module, the first k-1 second transistors are connected between the second poles of two adjacent second diodes in series, the first pole of the kth second transistor is electrically connected with the second pole of the kth-stage third direct-current power supply, and the second pole of the kth second transistor is electrically connected with the second pole of the kth second diode.
9. The power supply chip testing device according to claim 8, wherein the second superimposing unit further includes k second resistors, and the second resistors are connected in series between the control module and the gate of the second transistor.
10. The power supply chip testing device according to claim 1, wherein the power supply simulation module comprises:
j level DC power supply, j is more than or equal to 2; the direct current power supply comprises a first pole and a second pole, and the first pole of the 1 st level direct current power supply is connected with reference voltage;
the third superposition unit comprises a unidirectional subunit and j-1 switch subunits; the j-1 switch subunits are connected in series between the j-level direct current power supplies; the unidirectional subunit comprises a voltage output end and j voltage input ends, and the ith voltage input end of the unidirectional subunit is connected between the second pole of the ith level of the direct-current power supply and the first pole of the (i + 1) th level of the direct-current power supply; wherein i is more than or equal to 1 and less than or equal to j-1; the jth voltage input end of the unidirectional subunit is electrically connected with the second pole of the jth level direct-current power supply, or the jth voltage input end of the unidirectional subunit is electrically connected with the jth-1 switch subunit; and the voltage output end of the unidirectional subunit is used as the output end of the power supply simulation module and is electrically connected with the power supply chip.
11. The power supply chip test device according to claim 10, wherein the switch subunit includes a third transistor; the grid electrode of the third transistor is electrically connected with the control module; the mth third transistor is connected in series between the second pole of the mth level direct current power supply and the first level of the (m + 1) th level direct current power supply; or, the mth third transistor is connected in series between the second pole of the (m + 1) th stage direct-current power supply and the first pole of the (m + 2) th stage direct-current power supply; wherein m is more than or equal to 1 and less than or equal to j-2; the j-1 th third transistor is connected in series between the second pole of the j-1 th stage direct current power supply and the first pole of the j-1 th stage direct current power supply; or a first pole of a j-1 th third transistor is electrically connected with a second pole of the j-th level direct current power supply, and a second pole of the j-1 th third transistor is electrically connected with a j-th voltage input end of the unidirectional sub-unit;
the unidirectional subunit includes: and the first pole of the ith third diode is connected between the second pole of the ith level of direct current power supply and the first pole of the (i + 1) th level of direct current power supply, and the second poles of the j-1 third diodes are in short circuit and are used as the voltage output end of the unidirectional subunit.
12. The power chip testing device as claimed in claim 11, wherein the switch subunit further comprises a third resistor, and the third resistor is connected in series between the control module and the gate of the third transistor.
13. The power supply chip testing device according to claim 2 or 10, wherein the power supply simulation module further comprises:
and the voltage stabilizing unit comprises a first end and a second end, the first end of the voltage stabilizing unit is connected to the reference voltage, and the second end of the voltage stabilizing unit is electrically connected with the output end of the power supply simulation module.
14. The power supply chip testing apparatus as claimed in claim 13, wherein the voltage stabilizing unit comprises: and the first end of the capacitor is connected to the reference voltage, and the second end of the capacitor is electrically connected with the output end of the power supply simulation module.
15. The power supply chip testing apparatus according to claim 1, wherein the load simulation module comprises:
q first impedance units connected in parallel, wherein q is more than or equal to 2; the first impedance units comprise input ends and connecting ends, and the input ends of the q first impedance units are in short circuit and serve as the input ends of the load simulation module;
the parallel unit comprises q-1 connecting ends and q-1 reference ends; the q-1 connecting ends of the parallel units are electrically connected with the connecting ends of the 2 nd to q th first impedance units in a one-to-one correspondence manner; and the connection end of the first impedance unit and the q-1 reference ends of the parallel unit are connected with reference voltage.
16. The power supply chip test apparatus as claimed in claim 15, wherein the parallel unit comprises:
the grid electrode of the fourth transistor is electrically connected with the control module, the first poles of the q-1 fourth transistors are electrically connected with the connection ends of the 2 nd to q fourth impedance units in a one-to-one correspondence mode, and the second poles of the q-1 fourth transistors are connected with the reference voltage in an access mode.
17. The power supply chip testing apparatus as claimed in claim 16, wherein the parallel unit further comprises: a fourth resistor connected in series between the control module and the gate of the fourth transistor.
18. The power supply chip testing apparatus as claimed in claim 16, wherein the parallel unit further comprises: a q-th fourth transistor; the grid electrode of the q-th fourth transistor is electrically connected with the control module, the first pole of the q-th fourth transistor is electrically connected with the connecting end of the 1 st first impedance unit, and the second pole of the q-th fourth transistor is connected with the reference voltage.
19. The power supply chip testing apparatus according to claim 1, wherein the load simulation module comprises:
s second impedance units connected in series, wherein s is more than or equal to 2; the second impedance unit comprises an input end and a connecting end, the input end of the 1 st second impedance unit is used as the input end of the load simulation module, and the connecting end of the s-th second impedance unit is connected with a reference voltage;
and the s-1 series units are connected with the 2 nd to s th second impedance units in parallel in a one-to-one correspondence manner.
20. The power supply chip testing apparatus as claimed in claim 19, wherein the series unit comprises: a fifth transistor, a gate of which is electrically connected with the control module; the first poles of the s-1 fifth transistors are electrically connected with the input ends of the 2 nd to s th second impedance units in a one-to-one correspondence mode, and the second poles of the s-1 fifth transistors are electrically connected with the connection ends of the 2 nd to s th second impedance units in a one-to-one correspondence mode.
21. The power supply chip testing apparatus as claimed in claim 20, wherein the series unit further comprises: a fifth resistor connected in series between the control module and the gate of the fifth transistor.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115656770A (en) * | 2022-10-19 | 2023-01-31 | 杭州国磊半导体设备有限公司 | Method and device for testing power driving chip, computer equipment and storage medium |
| CN116840734A (en) * | 2023-07-07 | 2023-10-03 | 西安航空学院 | Digital pulse parameter detection system and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115656770A (en) * | 2022-10-19 | 2023-01-31 | 杭州国磊半导体设备有限公司 | Method and device for testing power driving chip, computer equipment and storage medium |
| CN115656770B (en) * | 2022-10-19 | 2023-09-01 | 杭州国磊半导体设备有限公司 | Power supply driving chip testing method and device, computer equipment and storage medium |
| CN116840734A (en) * | 2023-07-07 | 2023-10-03 | 西安航空学院 | Digital pulse parameter detection system and method |
| CN116840734B (en) * | 2023-07-07 | 2024-04-05 | 西安航空学院 | Digital pulse parameter detection system and method |
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