CN215416640U - High-speed signal transmission system with interconnection framework - Google Patents
High-speed signal transmission system with interconnection framework Download PDFInfo
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- CN215416640U CN215416640U CN202121199698.6U CN202121199698U CN215416640U CN 215416640 U CN215416640 U CN 215416640U CN 202121199698 U CN202121199698 U CN 202121199698U CN 215416640 U CN215416640 U CN 215416640U
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- 230000008054 signal transmission Effects 0.000 title claims abstract description 18
- 230000005540 biological transmission Effects 0.000 claims description 15
- 239000003990 capacitor Substances 0.000 claims description 11
- 230000008878 coupling Effects 0.000 claims description 11
- 238000010168 coupling process Methods 0.000 claims description 11
- 238000005859 coupling reaction Methods 0.000 claims description 11
- 238000013461 design Methods 0.000 abstract description 6
- 238000011161 development Methods 0.000 abstract description 3
- 238000003780 insertion Methods 0.000 description 5
- 230000037431 insertion Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000012356 Product development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
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Abstract
The utility model provides a high-speed signal transmission system with an interconnection framework, which comprises a mainboard, a cable and terminal equipment, wherein the mainboard is provided with a cable connector; and two ends of the cable are respectively connected with the cable connector and the terminal equipment. The utility model changes the existing interconnection mode of the mainboard, the cable and the backboard to the terminal equipment into the mode of the mainboard and the cable to the terminal equipment, integrates the cable and the backboard, eliminates the influence of the cable end connector and the trace routing length of the PCB on a team, improves the signal transmission quality of signals at higher speed, greatly reduces the development and design cost of the system for interconnecting all board cards and components, and improves the competitiveness of products.
Description
Technical Field
The utility model relates to the technical field of server high-speed signal transmission, in particular to a high-speed signal transmission system with an interconnection architecture.
Background
In the design of the current high-speed Server main board, with the increase of the high-speed signal rate, for example, PCIE5.0 signal 32.0Gbps, SAS4.0 signal 24.0Gbps, and other types of buses are already introduced into product development and applied, the increase of the signal rate will affect the transmission quality of the complex long-distance Channel signal.
Meanwhile, due to the current product performance requirements, a cascading scheme is generally adopted to meet the long-distance transmission quality requirements of high-speed signals. As shown in fig. 1, a cascading manner of a motherboard + a Cable + a backplane is adopted, so that the terminating terminal device becomes a mainstream design scheme for current server product development.
However, with the introduction of PCIE5.0(32Gbps rate) signals, the signals require a small insertion loss value of the whole link, which may result in an increase in electrical indexes of PCB boards and Cable cables, thereby greatly increasing the design cost of system development.
SUMMERY OF THE UTILITY MODEL
The utility model provides a high-speed signal transmission system with an interconnection framework, which is used for solving the problem that the cost and the design cost of the existing interconnection mode are high.
In order to achieve the purpose, the utility model adopts the following technical scheme:
the utility model provides a high-speed signal transmission system with an interconnection framework, which comprises a mainboard, a cable and terminal equipment, wherein the mainboard is provided with a cable connector; and two ends of the cable are respectively connected with the cable connector and the terminal equipment.
Furthermore, a CPU and a coupling capacitor are arranged on the mainboard, the CPU is connected with one end of the coupling capacitor through a PCB transmission line TL1, and the other end of the coupling capacitor is connected with the cable connector through a PCB transmission line TL 2.
Further, the cable is connected with the terminal equipment through a plug-in card.
Further, the terminal device is a PCIE card.
Further, set up PCIE connector and SMT connector on the plug-in card, the SMT connector is connected to the cable, PCIE card connects the PCIE connector.
The effects provided in the contents of the present invention are only the effects of the embodiments, not all the effects of the present invention, and one of the above technical solutions has the following advantages or advantageous effects:
the utility model changes the existing interconnection mode of the mainboard, the cable and the backboard to the terminal equipment into the mode of the mainboard and the cable to the terminal equipment, integrates the cable and the backboard, eliminates the influence of the cable end connector and the trace routing length of the PCB on a team, improves the signal transmission quality of signals at higher speed, greatly reduces the development and design cost of the system for interconnecting all board cards and components, and improves the competitiveness of products.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a prior art high speed interconnect architecture;
FIG. 2 is a high speed interconnect architecture of the present invention;
the system comprises a main board 1, 11PCB transmission lines TL1, 12 coupling capacitors, 13PCB transmission lines TL2, 14Z-link connectors, 15CPU, 2 cables, 3 back boards, 30PCB transmission lines TL3, 31PCIE plug-in connectors, 32PCIE connectors, 33PCIE card, 34 plug-in cards and 35SMT connectors.
Detailed Description
In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the utility model. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the utility model.
As shown in fig. 1, the interconnection architecture includes a main board 1, a cable 2 and a backplane 3 that are interconnected, Z-link connectors 14 for connecting the cable 2 are respectively disposed on the main board 1 and the backplane 3, and the main board 1 is further provided with a PCB connection line TL 111, a coupling capacitor 12, a PCB connection line TL 213 and a CPU 15; the backplane 3 is provided with a PCB transmission line TL3, a PCIE plug connector 31, a PCIE connector 32, and a PCIE card33, where the PCIE plug connector 31 is used for plugging the PCIE connector 32.
Based on the interconnection architecture of fig. 1, for the high-speed transmission signal of PCIE5.0, in order to deal with the increase of signal rate, a board with better electrical performance is to be adopted on the motherboard and the backplane, wherein the motherboard adopts an EM528 Low board, and the backplane adopts an EM890K ultra Low board because 3.3inch long lines (TL3) are required, which has better electrical performance than the EM528 and naturally higher board price. Meanwhile, the interconnection architecture shown in fig. 1 is adopted to evaluate the insertion loss of the whole channel, and the insertion loss value is found to slightly exceed the SPEC index, so that the signal transmission quality of the interconnection architecture has certain risk.
Aiming at the problem that the signal transmission quality is influenced by the fact that the PCIE5.0 signal rate is increased and the insertion loss value of the existing interconnection transmission scheme is large, the embodiment of the scheme is explained as follows.
As shown in fig. 2, the high-speed signal transmission system with interconnection architecture of the present invention includes a motherboard 1, a cable 2 and a terminal device, where the terminal device of this embodiment is illustrated as a PCIE card33, and the motherboard is provided with a cable connector 14; both ends of the cable 2 are connected to the cable connector 14 and the terminal device, respectively.
The mainboard 1 is provided with a CPU15 and a coupling capacitor 12, the CPU15 is connected with one end of the coupling capacitor 12 through a PCB transmission line TL1, and the other end of the coupling capacitor 12 is connected with the cable connector 14 through a PCB transmission line TL 2. Wherein the cable connector is a Z-link connector.
The cable 2 is connected to the terminal device by a paddle card 34. PCIE connector 32 and SMT connector 35 are arranged on card 34, the cable is connected with SMT connector 35, and PCIE card33 is connected with PCIE connector 32.
The interconnection architecture of fig. 2 integrates the cable and the backplane together in a manner of motherboard + cable to terminal device, thereby eliminating the influence of the length of the PCB transmission line on the cable-end connector and the backplane, and improving the signal transmission quality of the signal at a higher rate. The link insertion loss values shown in fig. 2 satisfy the SPEC criterion. Meanwhile, PCIE5.0 high-speed signals can not be carried out on the back board any more, so that a common FR4 board can be adopted, and the development cost of the PCB board is reduced.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.
Claims (5)
1. A high-speed signal transmission system with an interconnection architecture is characterized by comprising a main board, a cable and terminal equipment, wherein the main board is provided with a cable connector; and two ends of the cable are respectively connected with the cable connector and the terminal equipment.
2. The high-speed signal transmission system of claim 1, wherein the main board is provided with a CPU and a coupling capacitor, the CPU is connected to one end of the coupling capacitor through a PCB transmission line TL1, and the other end of the coupling capacitor is connected to the cable connector through a PCB transmission line TL 2.
3. The high-speed signal transmission system according to claim 1, wherein the cable is connected to the terminal device by a card.
4. The high-speed signal transmission system according to claim 3, wherein the terminal device is a PCIE card.
5. The high-speed signal transmission system according to claim 4, wherein a PCIE connector and an SMT connector are disposed on the card, the cable is connected to the SMT connector, and the PCIE card is connected to the PCIE connector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121199698.6U CN215416640U (en) | 2021-05-31 | 2021-05-31 | High-speed signal transmission system with interconnection framework |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121199698.6U CN215416640U (en) | 2021-05-31 | 2021-05-31 | High-speed signal transmission system with interconnection framework |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215416640U true CN215416640U (en) | 2022-01-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202121199698.6U Active CN215416640U (en) | 2021-05-31 | 2021-05-31 | High-speed signal transmission system with interconnection framework |
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| Country | Link |
|---|---|
| CN (1) | CN215416640U (en) |
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2021
- 2021-05-31 CN CN202121199698.6U patent/CN215416640U/en active Active
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