CN215378539U - Chip configuration circuit of small-sized quick charger - Google Patents
Chip configuration circuit of small-sized quick charger Download PDFInfo
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- CN215378539U CN215378539U CN202121162063.9U CN202121162063U CN215378539U CN 215378539 U CN215378539 U CN 215378539U CN 202121162063 U CN202121162063 U CN 202121162063U CN 215378539 U CN215378539 U CN 215378539U
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Abstract
In order to overcome the defects of the prior art, the utility model provides a chip configuration circuit of a small-sized quick charger, a time sequence control circuit of the utility model controls a first chip acquisition end and a second chip acquisition end to work simultaneously or with a fixed time sequence difference, the first chip acquisition end and the second chip acquisition end transmit signals to an acquisition and storage circuit simultaneously or with a fixed time sequence difference, the first acquisition and storage circuit and the second acquisition and storage circuit both store the acquired signals, including the potential and the time sequence of the signals, and thus, the utility model can realize the simultaneous acquisition of the working frequency of a chip at the commercial power output side and the chip frequency at the charging control side.
Description
Technical Field
The utility model relates to a chip configuration circuit of a small-sized quick charger.
Background
The fast charger in the prior art generally comprises a commercial power output side and a charging output side, wherein a main chip of the commercial power output side is a voltage control chip, a main chip of the charging control side is a rectification control chip and an output interface control chip, in order to improve the efficiency of fast charging, it is generally required that the working frequency of the commercial power output side chip and the chip frequency of the charging control side are configured and improved at the same time, in the prior art, the simultaneous acquisition of the working frequency of the commercial power output side chip and the chip frequency of the charging control side cannot be realized, and no corresponding control technology support can be provided to study the simultaneous configuration and improvement of the working frequency of the commercial power output side chip and the chip frequency of the charging control side.
Disclosure of Invention
In order to overcome the defects of the prior art, the utility model provides a chip configuration circuit of a small-sized quick charger, wherein a time sequence control circuit of the chip configuration circuit of the small-sized quick charger controls a first chip acquisition end and a second chip acquisition end to work simultaneously or with a fixed time sequence difference, the first chip acquisition end and the second chip acquisition end transmit signals to an acquisition and storage circuit simultaneously or with a fixed time sequence difference, and the first acquisition and storage circuit and the second acquisition and storage circuit both store acquired signals comprising the potential and the time sequence of the signals.
The technical scheme adopted by the utility model for solving the technical problems is as follows: the utility model comprises a first chip acquisition end for acquiring signals of a commercial power output side chip and a second chip acquisition end for acquiring signals of a charging output side chip, wherein the first chip acquisition end and the second chip acquisition end are both electrically connected with a time sequence control circuit, the first chip acquisition end is also electrically connected with a first acquisition storage circuit, the second chip acquisition end is also electrically connected with a second acquisition storage circuit, the time sequence control circuit is used for controlling the first chip acquisition end and the second chip acquisition end to work simultaneously or with a fixed time sequence difference, and the first acquisition storage circuit and the second acquisition storage circuit are both used for storing acquired signals, including the potential and the time sequence of the signals.
The utility model discloses a power supply output side chip, including pulse width modulation and synchronous rectification integrated chip, first chip acquisition end is including the OUT pin of pulse width modulation and synchronous rectification integrated chip.
The utility model discloses a power output side chip is including the OUT pin of rectification control chip, the OUT pin of rectification control chip is connected to the second chip collection end, and the output side chip that charges is used in TYPE-A interface, and the output side chip that charges includes the rectification control chip, the second chip collection end is including the OUT pin of rectification control chip.
The utility model discloses a battery charging system, including TYPE-A interface, commercial power output side chip is used IN TYPE-A interface, and the output side chip that charges includes output interface control chip, second chip acquisition end is including output interface control chip's IN pin.
The first acquisition storage circuit and the second acquisition storage circuit respectively comprise a sampling circuit, an analog-to-digital conversion circuit and a storage circuit which are electrically connected.
The utility model has the advantages that the time sequence control circuit controls the first chip acquisition end and the second chip acquisition end to work simultaneously or with fixed time sequence difference, the first chip acquisition end and the second chip acquisition end transmit signals to the acquisition and storage circuit simultaneously or with fixed time sequence difference, and the first acquisition and storage circuit and the second acquisition and storage circuit store the acquired signals including the potential and the time sequence of the signals.
Drawings
The utility model is further illustrated with reference to the following figures and examples.
FIG. 1 is a block diagram of the circuit components of an embodiment of the present invention.
Detailed Description
In specific implementation, as shown in fig. 1, the utility model includes a first chip collecting terminal for collecting signals of a commercial power output side chip, and a second chip collecting terminal for collecting signals of a charging output side chip, wherein the first chip collecting terminal and the second chip collecting terminal are both electrically connected to a timing control circuit, the first chip collecting terminal is also electrically connected to a first collecting and storing circuit, the second chip collecting terminal is also electrically connected to a second collecting and storing circuit, the timing control circuit is configured to control the first chip collecting terminal and the second chip collecting terminal to operate at the same time or with a fixed timing difference, the first collecting and storing circuit and the second collecting and storing circuit are both configured to store collected signals, including the potential and timing of the signals, and in implementation, the timing control circuit controls the first chip collecting terminal and the second chip collecting terminal to operate at the same time or with a fixed timing difference, the utility model can realize the simultaneous acquisition of the working frequency of the chip at the commercial power output side and the chip frequency at the charging control side.
Preferably, the utility model comprises a first chip acquisition end for acquiring signals of a commercial power output side chip, and a second chip acquisition end for acquiring signals of a charging output side chip, wherein the first chip acquisition end and the second chip acquisition end are both electrically connected with a time sequence control circuit, the first chip acquisition end is also electrically connected with a first acquisition and storage circuit, the second chip acquisition end is also electrically connected with a second acquisition and storage circuit, the time sequence control circuit is used for controlling the first chip acquisition end and the second chip acquisition end to work simultaneously or with a fixed time sequence difference, the first acquisition and storage circuit and the second acquisition and storage circuit are both used for storing acquired signals, including the potential and the time sequence of the signals, the commercial power output side chip is applied in a TYPE-A interface, the commercial power output side chip comprises a pulse width modulation and synchronous rectification integrated chip, the first chip acquisition end comprises an OUT pin of the pulse width modulation and synchronous rectification integrated chip.
Preferably, the utility model comprises a first chip acquisition end for acquiring signals of a commercial power output side chip, and a second chip acquisition end for acquiring signals of a charging output side chip, wherein the first chip acquisition end and the second chip acquisition end are both electrically connected with a time sequence control circuit, the first chip acquisition end is also electrically connected with a first acquisition and storage circuit, the second chip acquisition end is also electrically connected with a second acquisition and storage circuit, the time sequence control circuit is used for controlling the first chip acquisition end and the second chip acquisition end to work simultaneously or with a fixed time sequence difference, the first acquisition and storage circuit and the second acquisition and storage circuit are both used for storing acquired signals, including the potential and the time sequence of the signals, the commercial power output side chip is applied in a TYPE-A interface, and the charging output side chip comprises a rectification control chip, the second chip acquisition end comprises an OUT pin of the rectification control chip.
Preferably, the utility model comprises a first chip acquisition end for acquiring signals of a commercial power output side chip and a second chip acquisition end for acquiring signals of a charging output side chip, wherein the first chip acquisition end and the second chip acquisition end are both electrically connected with a time sequence control circuit, the first chip acquisition end is also electrically connected with a first acquisition storage circuit, the second chip acquisition end is also electrically connected with a second acquisition storage circuit, the time sequence control circuit is used for controlling the first chip acquisition end and the second chip acquisition end to work simultaneously or IN a fixed time sequence difference mode, the commercial power output side chip is applied to a TYPE-A interface, the charging output side chip comprises an output interface control chip, and the second chip acquisition end comprises an IN pin of the output interface control chip.
Preferably, the utility model comprises a first chip acquisition end for acquiring signals of a commercial power output side chip, and a second chip acquisition end for acquiring signals of a charging output side chip, wherein the first chip acquisition end and the second chip acquisition end are both electrically connected with a timing control circuit, the first chip acquisition end is also electrically connected with a first acquisition storage circuit, the second chip acquisition end is also electrically connected with a second acquisition storage circuit, the timing control circuit is used for controlling the first chip acquisition end and the second chip acquisition end to work simultaneously or at a fixed timing difference, and the first acquisition storage circuit and the second acquisition storage circuit both comprise a sampling circuit, an analog-to-digital conversion circuit and a storage circuit which are electrically connected.
It will be appreciated by those skilled in the art that the utility model may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed above are illustrative and not exclusive in all respects. All changes which come within the scope of or equivalence to the utility model are intended to be embraced therein.
Claims (5)
1. A chip configuration circuit of a small-sized quick charger is characterized in that: including being used for carrying out signal acquisition's first chip collection end to commercial power output side chip, including being used for carrying out signal acquisition's second chip collection end to charging output side chip, first chip gather the end with second chip gather the end all to be connected with the chronogenesis control circuit electricity, first chip gather the end still to be connected with first collection storage circuit electricity, second chip gather the end still to be connected with second collection storage circuit electricity, chronogenesis control circuit be used for controlling first chip gather the end with second chip gather the end simultaneously or fixed chronogenesis difference work, first collection storage circuit with second gather storage circuit all be used for the signal of storage collection, including the electric potential and the chronogenesis of signal.
2. The chip configuration circuit of a small-sized fast charger according to claim 1, wherein: the utility model discloses a power supply output side chip, including pulse width modulation and synchronous rectification integrated chip, first chip acquisition end is including the OUT pin of pulse width modulation and synchronous rectification integrated chip.
3. The chip configuration circuit of a small-sized fast charger according to claim 1, wherein: the utility model discloses a power output side chip is including the OUT pin of rectification control chip, the OUT pin of rectification control chip is connected to the second chip collection end, and the output side chip that charges is used in TYPE-A interface, and the output side chip that charges includes the rectification control chip, the second chip collection end is including the OUT pin of rectification control chip.
4. The chip configuration circuit of a small-sized fast charger according to claim 1, wherein: the utility model discloses a battery charging system, including TYPE-A interface, commercial power output side chip is used IN TYPE-A interface, and the output side chip that charges includes output interface control chip, second chip acquisition end is including output interface control chip's IN pin.
5. The chip configuration circuit of a small-sized fast charger according to claim 1, wherein: the first acquisition storage circuit and the second acquisition storage circuit respectively comprise a sampling circuit, an analog-to-digital conversion circuit and a storage circuit which are electrically connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121162063.9U CN215378539U (en) | 2021-05-27 | 2021-05-27 | Chip configuration circuit of small-sized quick charger |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121162063.9U CN215378539U (en) | 2021-05-27 | 2021-05-27 | Chip configuration circuit of small-sized quick charger |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215378539U true CN215378539U (en) | 2021-12-31 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202121162063.9U Active CN215378539U (en) | 2021-05-27 | 2021-05-27 | Chip configuration circuit of small-sized quick charger |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN215378539U (en) |
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2021
- 2021-05-27 CN CN202121162063.9U patent/CN215378539U/en active Active
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