CN215376304U

CN215376304U - Board card

Info

Publication number: CN215376304U
Application number: CN202121612885.2U
Authority: CN
Inventors: 刘博�
Original assignee: Beijing Aoxing Technology Co ltd
Current assignee: Beijing Aoxing Technology Co ltd
Priority date: 2021-07-15
Filing date: 2021-07-15
Publication date: 2021-12-31
Anticipated expiration: 2031-07-15

Abstract

The utility model provides a board card, comprising: the debugging serial ports of the CPUs are respectively connected with the CPLD, and the CPLD is connected with the debugging host; in the first time, the debugging serial port of one CPU in the CPUs is in communication connection with the debugging host through the CPLD; and in the second time, the debugging serial port of another CPU in the CPUs is in communication connection with the debugging host through the CPLD. The debugging serial ports of the CPUs are switched through the CPLD, and the debugging serial ports of the CPUs can be output in a time-sharing multiplexing mode.

Description

Board card

Technical Field

The utility model relates to the field of computers, in particular to a board card.

Background

Generally, a board card with a Central Processing Unit (CPU) needs to lead out debugging serial ports, one CPU needs to lead out 1 debugging serial port, if a plurality of CPUs exist, a plurality of debugging serial ports need to be led out, and a common method is to leave out a plurality of serial ports on a PCB of the board card in a pin arrangement or socket manner and connect an external serial port line to a debugging host. Fig. 1 shows a schematic diagram of this method, in which a board a includes three CPUs: the CPU1, the CPU2 and the CPU3 are respectively provided with debugging serial ports 1-1, 2-1 and 3-1; and three pin headers: p1, P2, P3. The debugging serial port of each CPU is connected to a pin bank respectively, and each pin bank is connected with the corresponding serial ports g1, g2 and g3 of the debugging host B through cables respectively. When 1 board card has a plurality of debugging serial ports, can draw out on the PCB of board card to debug. If the device is provided with a shell, only 1 debugging serial port is usually reserved in consideration of space problems, and only one serial port of the CPU can be led out. If a user has a requirement to lead out serial ports of a plurality of CPUs, the prior art is difficult to meet the requirement. Moreover, usually, a plurality of debugging serial ports are provided on 1 board card or device, and usually only 1 interface is provided externally, so that a technology is required to be capable of multiplexing and outputting a plurality of serial ports in a time-sharing manner.

SUMMERY OF THE UTILITY MODEL

Aiming at the problems in the related art, the utility model aims to provide a board card which can output debugging serial ports of a plurality of CPUs in a time-sharing multiplexing manner.

According to an embodiment of the present invention, a board card includes: a plurality of CPUs; the respective debugging serial ports of the CPUs are respectively connected with the CPLD, and the CPLD is connected with the debugging host; in the first time, the debugging serial port of one CPU in the CPUs is in communication connection with the debugging host through the CPLD; and in the second time, the debugging serial port of another CPU in the CPUs is in communication connection with the debugging host through the CPLD.

According to the embodiment of the utility model, the CPLD comprises a plurality of switching modules correspondingly connected with a plurality of CPUs, the switching modules are respectively connected with a plurality of external buttons of the board card, and when one button of the external buttons is in a trigger state, the switching module is used for connecting the debugging serial port of the corresponding CPU with the debugging host in a communication manner.

According to the embodiment of the utility model, the CPLD comprises a plurality of transmission modules, each transmission module is correspondingly connected with the pin header on the board card, each transmission module is respectively connected between the CPU and the switching module, and when the transmission module corresponding to one CPU in the CPUs transmits the debugging serial port signal from the CPU to the switching module, the transmission modules corresponding to the rest CPUs in the CPUs transmit the debugging serial port signal from the CPU to the pin header connected with the transmission modules.

According to the embodiment of the utility model, after the board card is powered on, the transmission module corresponding to one of the CPUs transmits the debugging serial port signal from the CPU to the switching module, and the transmission modules corresponding to the rest CPUs in the CPUs transmit the debugging serial port signal of the CPU to the pin header connected with the transmission module.

According to an embodiment of the present invention, the board card further includes: and the external indicator lamp is used for indicating the current debugging serial port and is in communication connection with the CPLD.

According to the embodiment of the utility model, the board comprises a shell, the board comprises an interface used as a debugging serial port, and the CPLD is connected with the debugging host through the interface.

According to an embodiment of the utility model, the plurality of switching modules comprises switches.

The utility model can output the debugging serial ports of the CPUs on the board by time division multiplexing by arranging the CPLD on the board and switching the debugging serial ports of the CPUs through the CPLD.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 is a functional block diagram of a board card according to the prior art;

fig. 2 is a schematic block diagram of a board according to an embodiment of the present invention;

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present invention.

The utility model provides a board card, comprising: the CPU comprises a plurality of CPUs and a complex Programmable Logic device CPLD (Complex Programmable Logic device), wherein the respective debugging serial ports of the CPUs are respectively connected with the CPLD, and the CPLD is connected with a debugging host; in the first time, the debugging serial port of one CPU in the CPUs is in communication connection with the debugging host through the CPLD; and in the second time, the debugging serial port of another CPU in the CPUs is in communication connection with the debugging host through the CPLD. According to the technical scheme, the CPLD is arranged on the board card, the debugging serial ports of the CPUs are switched through the CPLD, and the debugging serial ports of the CPUs can be output in a time-sharing multiplexing mode.

Fig. 2 schematically shows a schematic block diagram of a board, in an exemplary embodiment, the board C has three CPUs: CPU1, CPU2, CPU3 have respective debugging serial ports: 1-1, 2-1, 3-1, where the number of CPUs is not limited. In the embodiment, the debugging serial ports 1-1, 2-1 and 3-1 are all connected with the CPLD, and the CPLD is connected with the debugging host D. In the first time, the debugging serial port 1-1 of the CPU1 is in communication connection with the debugging host D through the CPLD, at this time, the CPLD only outputs the debugging serial port signal of the CPU1 to the debugging host D to debug the CPU1, and in the second time, the debugging serial port 2 of the CPU2 is in communication connection with the debugging host D through the CPLD, at this time, the CPLD only outputs the debugging serial port signal of the CPU2 to the debugging host D to debug the CPU 2. Therefore, the utility model can realize the time-sharing multiplexing output of the debugging serial port 1, the debugging serial port 2 and the debugging serial port 3.

In an exemplary embodiment, as shown in fig. 2, the CPLD includes a plurality of switching modules S1, S2, S3 connected to the plurality of CPUs, the plurality of switching modules are respectively connected to the plurality of external buttons btn1, btn2, btn3 of the board, and when one of the buttons is in a triggered state, the switching module communicatively connects the debug serial port of the corresponding CPU to the debug host. For example, when the button btn2 is pressed, the switching module S2 communicatively connects the debug serial port 2-1 of the corresponding CPU2 with the debug host D.

In this embodiment, the external button may control the switching module connected to the button to output the debug serial port signal of the CPU corresponding to the switching module to the debug host. Therefore, the output debugging serial port signal can be conveniently switched through an external button of the board card.

In an exemplary embodiment, as shown in fig. 2, the CPLD includes a plurality of transmission modules M1, M2, M3, each of which is connected between a corresponding CPU and a switching module, respectively, and each of which is connected with a pin header P1, P2, P3, respectively. The transmission module can selectively output the debugging serial port signal of the CPU to the switching module or the pin header. In one embodiment, when an external button of the board card is in a triggered state, the transmission module on the external button control circuit transmits a corresponding debugging serial port signal of the CPU to the switching module, and the switching module outputs the debugging serial port signal to the debugging host. And the transmission modules on the other external button control circuits which are not triggered on the board card transmit the corresponding debugging serial port signals of the CPU to the pin header. For example, when the button btn2 is pressed, the transmission module M2 transmits the corresponding debug serial port signal 2-1 of the CPU2 to the switching module S2, and the switching module S2 outputs the debug serial port signal 2-1 to the debug host D. And the transmission modules M1 and M3 on the control lines of the other external buttons btn1 and btn3 which are not triggered on the board respectively transmit debugging serial port signals 1-1 and 3-1 of the corresponding CPU1 and CPU3 to the pins P1 and P3.

In this embodiment, two output lines are provided for the debugging serial port signal of the CPU through the transmission module, so that when the debugging serial port signal of one of the CPUs on the board is output through the CPLD, the debugging serial port signals of the remaining CPUs on the board can be output through the pin header, thereby enabling the debugging serial ports of the plurality of CPUs on the board to be led out.

In an exemplary embodiment, after the board is powered on, a certain transmission module inside the CPLD defaults to transmit the debugging serial port signal of a corresponding CPU to the switching module, and the transmission modules corresponding to the other CPUs on the board transmit the debugging serial port signal of the CPU to the pin header. For example, the transmission module M1 defaults to transmit the debug serial port signal of the CPU1 corresponding to the transmission module M to the switching module S1, and the transmission modules corresponding to the

CPUs

2 and 3 on the board transmit the debug serial port signal of the CPUs to the pins P2 and P3, respectively.

In an exemplary embodiment, the board further includes an external indicator light, such as the LED1, the LED2, and the LED3 shown in fig. 2, and the external indicator light is connected in communication with the CPLD for indicating which debugging serial port is currently output.

In an exemplary embodiment, the board includes a housing, the board further includes an interface used as a debugging serial port, the CPLD is connected with the debugging host through the interface, and the interface can be connected with the debugging host through a cable. In this embodiment, a plurality of debug serial ports may be multiplexed and output to one interface of the board.

In an exemplary embodiment, the switching module includes a switch.

As described in detail below with respect to the embodiment of fig. 2, as shown in fig. 2, the board C has three CPUs: CPU1, CPU2, CPU3, each CPU has a debugging serial port: 1-1, 2-1 and 3-1, and the debugging serial port is connected to the CPLD. Wherein, M1, M2, M3, S1, S2 and S3 are all functional modules in the CPLD, M1, M2 and M3 are transmission modules, and S1, S2 and S3 are switching modules; a1, a2 and a3 are input signals corresponding to debugging serial ports 1-1, 2-1 and 3-1 in the CPLD respectively, b1, b2, b3, c1, c2 and c3 are internal signals generated by the transmission module according to the debugging serial port input signals, and y is an output signal corresponding to the debugging serial port input signals generated by the CPLD. btn1, btn2, btn3 are external buttons of the board card for switching serial port output. The LED1, the LED2 and the LED3 are external indicator lights of the board card and are used for indicating which serial port is currently output. The pin headers P1, P2 and P3 are arranged on the board card and can be respectively communicated with debugging serial ports 1-1, 2-1 and 3-1 under specific conditions. Wherein, the debugging serial port 1-1 of the CPU1 is connected with a transmission module M1, shown as A1; the debugging serial port 2-1 of the CPU2 is connected with a transmission module M2, shown as A2; the debug serial 3-1 of the CPU3 is connected to a transport module M3, shown as A3. Each transmission module is correspondingly connected with the switching module, and each switching module is correspondingly connected with the external button. The working principle of the board card C is as follows:

after the board card is powered on, the CPLD internal transmission module M1 outputs a signal a1 to a signal c1 by default, and the S1 module outputs a signal c1 to a signal y, so that the serial port g of the current debugging host D is connected to the debugging serial port 1-1 of the CPU1, and the CPLD lights up the LED 1. The CPLD internal transmission module M2 outputs the signal a2 to the signal b2 by default, and thus to the pin header P2. The CPLD internal transmission module M3 outputs the signal a3 to the signal b3 by default, and thus to the pin header P3.

When the button btn2 is pressed, the CPLD internal transmission module M2 outputs the signal a2 to the signal c2 by default, and the switching module S2 outputs the signal c2 to the signal y, so that the serial port g of the current debugging host D is connected to the debugging serial port 2-1 of the CPU2, and the CPLD lights the LED 2. The CPLD internal transmission module M1 outputs the signal a1 to the signal b1 and thus to the pin header P1. The CPLD internal transmission module M3 outputs the signal a3 to the signal b3 and thus to the pin header P3.

When the button btn3 is pressed, the CPLD internal transmission module M3 outputs the signal a3 to the signal c3 by default, and the switching module S3 outputs the signal c3 to the signal y, so that the serial port g of the current debugging host D is connected to the debugging serial port 3-1 of the CPU3, and the CPLD lights the LED 3. The CPLD internal transmission module M1 outputs the signal a1 to the signal b1 and thus to the pin header P1. The CPLD internal transmission module M2 outputs the signal a2 to the signal b2 and thus to the pin header P2.

In the embodiment, the debugging serial ports of the

CPUs

1, 2 and 3 can be output in a time-sharing multiplexing mode by switching the debugging serial ports of the CPUs through the CPLD.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A board card, comprising:

a plurality of CPUs;

the respective debugging serial ports of the CPUs are respectively connected with the CPLD, and the CPLD is connected with a debugging host;

in the first time, the debugging serial port of one CPU in the CPUs is in communication connection with the debugging host through the CPLD; and in a second time, the debugging serial port of another CPU in the CPUs is in communication connection with the debugging host through the CPLD.

2. The board according to claim 1, wherein the CPLD includes a plurality of switching modules correspondingly connected to the plurality of CPUs, and the plurality of switching modules are respectively connected to a plurality of external buttons of the board, and when one of the plurality of external buttons is in a triggered state, the switching module communicatively connects the debugging serial port of the corresponding CPU to the debugging host.

3. The board card of claim 2, wherein the CPLD includes a plurality of transmission modules, each transmission module is correspondingly connected to a pin header on the board card, and each transmission module is respectively connected between a CPU and a switching module, and when a transmission module corresponding to one of the CPUs transmits the debug serial port signal from the CPU to the switching module, the transmission modules corresponding to the remaining CPUs of the CPUs transmit the debug serial port signal from the CPU to the pin header connected to the transmission module.

4. The board card of claim 3, wherein after the board card is powered on, the transmission module corresponding to one of the CPUs transmits the debug serial port signal from the CPU to the switching module, and the transmission modules corresponding to the remaining CPUs of the CPUs transmit the debug serial port signal of the CPU to the pin header connected to the transmission module.

5. The board card of claim 1, further comprising: and the external indicator lamp is used for indicating the current debugging serial port and is in communication connection with the CPLD.

6. The board of claim 1, wherein the board includes a housing, the board including an interface for a debug serial port, the CPLD being connected to the debug host through the interface.

7. The board of claim 2, wherein the plurality of switching modules comprise switches.