CN215343889U - Power control chip enables control circuit and vehicle-mounted charger auxiliary power supply - Google Patents
Power control chip enables control circuit and vehicle-mounted charger auxiliary power supply Download PDFInfo
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- CN215343889U CN215343889U CN202120832720.XU CN202120832720U CN215343889U CN 215343889 U CN215343889 U CN 215343889U CN 202120832720 U CN202120832720 U CN 202120832720U CN 215343889 U CN215343889 U CN 215343889U
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Abstract
The utility model discloses an enabling control circuit of a power control chip.A enabling signal generating module of the enabling control circuit is used for outputting an enabling signal to an enabling pin connected with the power control chip; the enabling signal is an enabling low level when the voltage of the power input pin is lower than a threshold voltage, and is an enabling high level when the voltage of the power input pin is greater than or equal to a set voltage; the enabling high level is larger than the threshold voltage and smaller than the working voltage of the power control chip. In the process that the power supply input pin of the power supply control chip enters the under-voltage area of the power supply control chip from the normal working voltage, the enable pin is set to be at a low level successfully before the power supply input pin enters the under-voltage area, so that the situation that the power supply control chip is locked is avoided. The utility model also discloses an auxiliary power supply of the vehicle-mounted charger. According to the utility model, when the charging power supply is plugged, the enabling pin of the power supply control chip can be reset from hardware without software detection.
Description
Technical Field
The utility model relates to a power circuit, in particular to a power control chip enabling control circuit and an auxiliary power supply of a vehicle-mounted charger.
Background
The auxiliary power supply of the vehicle-mounted charger is mainly used for providing energy for the driving circuit and also providing energy for other loads (such as a voltage sampling circuit, a current sampling circuit and the like), and the stability of the auxiliary power supply is important for the work of the whole vehicle-mounted charger. The auxiliary power supply is usually formed by a flyback (flyback converter) main topology and a PWM (pulse width modulation) control chip due to the requirement of multi-path output, the performance of the PWM control chip directly determines the robustness of the auxiliary power supply, and currently, commonly used PWM control chips (such as NCV887100D, NCV887101D, NCV887102D, and NCV887103D manufactured by the asemei semiconductor company) have a characteristic that when a power input pin VIN of the control chip is in an under-voltage region (usually 3V) defined by the chip, if an enable pin EN of the control chip is still in a high level state (usually 2-5V), the chip has a risk of under-voltage lock, and if the condition occurs, the enable pin EN needs to be pulled down and then put high to restart the auxiliary power supply. Therefore, when the charging power supply positive KL30 of the vehicle-mounted charger is plugged from the normal charging voltage 14V in millisecond level, the specific waveform of the charging power supply positive KL30 is as shown in fig. 1, the auxiliary power supply has a certain probability that no output voltage is generated due to the locking of the PWM control chip, and the MCU (microprocessor) of the vehicle-mounted charger stops working due to power failure. Fig. 2 is a power supply structure of a current PWM control chip enable circuit, and the solution to the technical problem is as follows: the output of the auxiliary power supply is detected through MCU software, and when no output of the auxiliary power supply is detected, the voltage of an enable pin EN of the PWM control chip IC is pulled low and then is set high by the MCU to solve the problem. The scheme has the disadvantages that the sampling detection can only depend on software, the sampling period of the software is usually long (for example, 10ms), when the positive KL30 of the charging power supply of the vehicle-mounted charger has a waveform as shown in FIG. 1, the situation that the detection is missed due to the fact that the sampling frequency of the software is too low exists, in order to make up for the defects, the software needs to make a more complex sampling strategy, and MCU resources are greatly consumed.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem that when a charging power supply is plugged, an enabling pin of a power supply control chip can be reset from hardware, so that the condition that the power supply control chip is locked under low voltage is thoroughly avoided.
In order to solve the above technical problem, the power control chip enable control circuit provided by the utility model comprises an enable signal generation module;
the enable signal generating module is used for outputting an enable signal to an enable pin EN connected with the power control chip IC;
the enabling signal is an enabling low level when the voltage of a power input pin VIN is lower than a threshold voltage, and is an enabling high level when the voltage of the power input pin VIN is greater than or equal to a set voltage;
the working voltage of the power control chip > enable high level > the threshold voltage > the undervoltage voltage of the power control chip > enable low level.
Preferably, the power control chip IC is a PWM control chip;
the PWM control chip is provided with a power supply input pin VIN, an enable pin EN and a PWM signal output end;
when the power input pin VIN of the PWM control chip is lower than the undervoltage defined by the chip, if the enable pin EN of the control chip is still in a high level state, the control chip has a risk of undervoltage lock, Vd < Vs < Vu, Vs is the undervoltage, Vd is the lower limit voltage of the enable pin EN in the high level state, and Vu is the upper limit voltage of the enable pin EN in the high level state.
Preferably, Vs is 3V, Vd is 2V, Vu is 5V;
when the PWM control chip is locked, the PWM signal output end maintains the same level.
Preferably, the power control chip enable control circuit further comprises a voltage division sampling circuit;
the enabling signal generating module comprises a three-terminal adjustable shunt reference source D2, a PNP triode T2, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a diode D1 and a second capacitor C2;
the voltage division sampling circuit is connected between a power input pin VIN of the power control chip IC and the ground, and is used for dividing the voltage of the power input pin VIN of the power control chip IC to obtain a comparison sampling voltage;
when the voltage of a reference end R of the three-end adjustable shunt reference source D2 is greater than the internal reference voltage VI thereof, the cathode C of the three-end adjustable shunt reference source is communicated with the anode A of the three-end adjustable shunt reference source; when the voltage of the reference end R is less than or equal to the internal reference voltage VI, the cathode C is disconnected with the anode A;
the reference end R of the three-end adjustable shunt reference source D2 is connected with a comparison sampling voltage output point, the anode A of the three-end adjustable shunt reference source is grounded, and the cathode C of the three-end adjustable shunt reference source is connected with the base electrode of the PNP triode T2 through a fifth resistor R5;
the emitter of the PNP triode T2 is connected with the system base voltage VDD, the collector of the PNP triode T2 is grounded through a seventh resistor R7, and the collector of the PNP triode T2 is connected with an enable pin EN of a power control chip IC;
the sixth resistor R6 is connected between the emitter and the base of the PNP transistor T2;
the positive end of the diode D1 is connected with an enable pin EN of the power control chip IC, and the negative end of the diode D1 is connected with the reference end R of the three-end adjustable shunt reference source D2 through a fourth resistor R4;
the second capacitor C2 is connected between the reference terminal R of the three-terminal adjustable shunt reference source D2 and ground.
Preferably, the voltage division sampling circuit comprises a second resistor R2 and a third resistor R3;
the second resistor R2 and the third resistor R3 are sequentially connected in series between the power input pin VIN of the power control chip IC and the ground, and the connection point of the second resistor R2 and the third resistor R3 is used as a comparison sampling voltage output point.
Preferably, the second resistor R2 is connected to the positive terminal of the charging power source and is connected to ground through the first capacitor C1.
Preferably, the power control chip enable control circuit further includes a first resistor R1;
the first resistor R1, the second resistor R2 and the third resistor R3 are sequentially connected in series between the positive ground and the ground of the charging power supply;
the first resistor R1 is smaller than the second resistor R2 and the third resistor R3 at 1/10.
Preferably, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6 and the seventh resistor R7 are all kilo-ohm resistors, and the first resistor R1 is less than 100 ohms.
Preferably, the power control chip enable control circuit further includes a switch transistor T1;
the switch tube T1 is connected between the charging power supply and the second resistor R2;
the control end of the switch tube T1 is connected with the microprocessor;
the microprocessor is used for controlling the on-off of the switch tube T1.
Preferably, the system base voltage VDD is 5V, and the internal reference voltage VI of the three-terminal adjustable shunt reference source D2 is 2.5V.
Preferably, the power control chip enable control circuit further comprises a power management circuit SBC;
the input end of the power management circuit SBC is connected with the positive KL30 of the charging power supply, and when the positive KL30 of the charging power supply is powered on, the power management circuit SBC outputs the system base voltage VDD.
The utility model also provides an auxiliary power supply of the vehicle-mounted charger, which comprises the power control chip enabling control circuit.
Preferably, the auxiliary power supply of the vehicle-mounted charger further comprises a flyback converter;
the power supply control chip IC is a PWM control chip;
and the PWM signal output by the PWM signal output end of the PWM control chip is used for controlling the on-off of a power switch device in the main circuit of the flyback converter.
According to the power supply control chip enabling control circuit, when the positive KL30 of the charging power supply is plugged, software detection is not needed, the enabling pin EN of the power supply control chip IC can be reset from hardware, the situation that the power supply control chip is locked under voltage is thoroughly avoided, the situation that detection is missed due to the fact that the sampling rate of software is too low is avoided, and meanwhile MCU resources are saved.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the present invention are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a waveform diagram of a conventional vehicle-mounted charger when a charging power supply is plugged in and unplugged from a normal charging voltage in millisecond level;
FIG. 2 is a power supply structure of a PWM control chip enabling circuit of an auxiliary power supply of a conventional vehicle-mounted charger;
FIG. 3 is a circuit diagram of an embodiment of an enable control circuit of a power control chip according to the present invention;
fig. 4 is a waveform diagram of the power control chip enable control circuit of the present invention when the millisecond-level plugging occurs from the normal charging voltage.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
As shown in fig. 3, the power control chip enable control circuit includes an enable signal generation module;
the enabling signal generating module is used for outputting an enabling signal to an enabling pin EN connected with the power control chip IC;
the enabling signal is an enabling low level when the voltage of a power input pin VIN is lower than a threshold voltage, and is an enabling high level when the voltage of the power input pin VIN is greater than or equal to a set voltage;
the working voltage of the power control chip > enable high level > the threshold voltage > the undervoltage voltage of the power control chip > enable low level.
Preferably, the power control chip IC is a PWM (pulse width modulation) control chip;
the PWM control chip is provided with a power supply input pin VIN, an enable pin EN and a PWM signal output end;
the PWM control chip is provided with a power supply input pin VIN, an enable pin EN and a PWM signal output end;
when the power input pin VIN of the PWM control chip is lower than the undervoltage defined by the chip, if the enable pin EN of the control chip is still in a high level state, the control chip has a risk of undervoltage lock, Vd < Vs < Vu, Vs is the undervoltage, Vd is the lower limit voltage of the enable pin EN in the high level state, and Vu is the upper limit voltage of the enable pin EN in the high level state.
Preferably, Vs is 3V, Vd is 2V, Vu is 5V;
when the PWM control chip is locked, the PWM signal output end maintains the same level.
The PWM control chip has a characteristic that when a power input pin VIN of the PWM control chip is in an under-voltage region (less than 3V) defined by the chip, if an enable pin EN of the control chip is still in a high level state (usually 2-5V), the PWM control chip has a risk of under-voltage lock.
The power control chip enable control circuit of the first embodiment, when the charging power supply positive KL30 is plugged or unplugged as shown in fig. 1, can reset the enable pin EN of the power control chip IC from hardware without software detection, thoroughly avoids the occurrence of the condition of under-voltage lock of the power control chip, avoids the condition of missed detection due to too low software sampling rate, and saves MCU resources.
Example two
Based on the first embodiment, the power control chip enabling control circuit further comprises a voltage division sampling circuit;
the enabling signal generating module comprises a three-terminal adjustable shunt reference source D2, a PNP triode T2, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a diode D1 and a second capacitor C2;
the voltage division sampling circuit is connected between a power input pin VIN of the power control chip IC and the ground, and is used for dividing the voltage of the power input pin VIN of the power control chip IC to obtain a comparison sampling voltage;
when the voltage of a reference end R of the three-end adjustable shunt reference source D2 is greater than the internal reference voltage VI thereof, the cathode C of the three-end adjustable shunt reference source is communicated with the anode A of the three-end adjustable shunt reference source; when the voltage of the reference end R is less than or equal to the internal reference voltage VI, the cathode C is disconnected with the anode A;
the reference end R of the three-end adjustable shunt reference source D2 is connected with a comparison sampling voltage output point, the anode A of the three-end adjustable shunt reference source is grounded, and the cathode C of the three-end adjustable shunt reference source is connected with the base electrode of the PNP triode T2 through a fifth resistor R5;
the emitter of the PNP triode T2 is connected with the system base voltage VDD, the collector of the PNP triode T2 is grounded through a seventh resistor R7, and the collector of the PNP triode T2 is connected with an enable pin EN of a power control chip IC;
the sixth resistor R6 is connected between the emitter and the base of the PNP transistor T2;
the positive end of the diode D1 is connected with an enable pin EN of the power control chip IC, and the negative end of the diode D1 is connected with the reference end R of the three-end adjustable shunt reference source D2 through a fourth resistor R4;
the second capacitor C2 is connected between the reference terminal R of the three-terminal adjustable shunt reference source D2 and ground.
Preferably, the voltage division sampling circuit comprises a second resistor R2 and a third resistor R3;
the second resistor R2 and the third resistor R3 are sequentially connected in series between the power input pin VIN of the power control chip IC and the ground, and the connection point of the second resistor R2 and the third resistor R3 is used as a comparison sampling voltage output point.
Preferably, the second resistor R2 is connected to the positive terminal of the charging power source and is connected to ground through the first capacitor C1.
Preferably, the power control chip enable control circuit further includes a first resistor R1;
the first resistor R1, the second resistor R2 and the third resistor R3 are sequentially connected in series between the positive ground and the ground of the charging power supply;
the first resistor R1 is smaller than the second resistor R2 and the third resistor R3 at 1/10.
Preferably, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6 and the seventh resistor R7 are all kilo-ohm resistors, and the first resistor R1 is less than 100 ohms.
Preferably, the power control chip enable control circuit further includes a switch transistor T1;
the switch tube T1 is connected between the charging power supply and the second resistor R2;
the control end of the switch tube T1 is connected with the microprocessor;
and the microprocessor MCU is used for controlling the on-off of the switch tube T1.
Preferably, the system base voltage VDD is 5V, and the internal reference voltage VI of the three-terminal adjustable shunt reference source D2 is 2.5V.
Preferably, the power control chip enable control circuit further comprises a power management circuit SBC;
the input end of the power management circuit SBC is connected with the positive KL30 of the charging power supply, and when the positive KL30 of the charging power supply is powered on, the power management circuit SBC outputs the system base voltage VDD.
Preferably, the three-terminal adjustable shunt reference source D2 is TL 431.
The enabling control circuit of the power control chip of the second embodiment has the following working principle:
a) the positive KL30 of charging source is charged for the first time, the power management circuit SBC outputs the system basic voltage VDD, the enable pin EN level initial voltage of the power control chip IC is zero at this moment, the partial pressure of the input voltage of the power input pin VIN of the power control chip at the reference end R of the three-end adjustable shunt reference source D2 is greater than the internal reference voltage VI of the three-end adjustable shunt reference source D2, the cathode C of the three-end adjustable shunt reference source D2 is communicated to the anode A of the ground, the PNP triode T2 is conducted, the enable pin EN level of the control chip is about VDD-0.7V, and the power control chip IC starts to work.
b) When the positive KL30 voltage of the charging source is plugged from the current voltage, as shown in fig. 4, in the process that the power input pin VIN of the power control chip IC enters the under-voltage region (VIN <3V) of the power control chip from the normal operating voltage, when the power input pin VIN of the power control chip IC is higher than the under-voltage region (for example, 5.4V), the superimposed voltage generated by the power input pin VIN of the power control chip IC and the enable pin EN is smaller than the internal reference voltage VI (for example, 2.5V) of the three-terminal adjustable shunt reference source D2, the cathode C of the three-terminal adjustable shunt reference source D2 is disconnected from the anode a, the PNP triode T2 is turned off, the enable terminal EN of the power control chip IC becomes a low level, and the power control chip IC is turned off. Since the enable pin EN of the power control chip IC is successfully set to the low level before the power input pin VIN of the power control chip IC enters the under-voltage area, the situation that the power control chip IC is locked is avoided, and the working condition described in the process a) is entered along with the recovery of the input voltage of the power input pin VIN of the power control chip IC.
Through verification, the circuit can respond to the input voltage dynamic change (steep drop and steep rise) of the power supply input pin VIN of the power supply control chip IC with the maximum speed of T being 250 us.
EXAMPLE III
The auxiliary power supply of the vehicle-mounted charger comprises the power control chip enabling control circuit of the embodiment I or II.
Preferably, the auxiliary power supply of the vehicle-mounted charger further comprises a flyback converter (flyback);
the power supply control chip IC is a PWM control chip;
and the PWM signal output by the PWM signal output end of the PWM control chip is used for controlling the on-off of a power switch device in a main circuit of the flyback converter (flyback).
If the PWM control chip is locked, the PWM signal output end of the PWM control chip keeps the same level unchanged, and a flyback converter (flyback) main circuit of the auxiliary power supply of the vehicle-mounted charger stops working.
The auxiliary power supply of the vehicle-mounted charger in the third embodiment thoroughly solves the problem that the auxiliary power supply does not output because the power control chip IC is locked under voltage when the charging power supply positive KL30 is plugged as shown in fig. 1 from a hardware circuit.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the utility model, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (13)
1. A power control chip enables the control circuit, characterized by, it includes enabling the signal generation module;
the enabling signal generating module is used for outputting an enabling signal to an enabling pin connected with the power control chip;
the enabling signal is an enabling low level when the voltage of the power input pin is lower than a threshold voltage, and is an enabling high level when the voltage of the power input pin is greater than or equal to a set voltage;
the working voltage of the power control chip > enable high level > the threshold voltage > the undervoltage voltage of the power control chip > enable low level.
2. The power control chip enable control circuit according to claim 1,
the power supply control chip is a PWM control chip;
the PWM control chip is provided with a power supply input pin, an enabling pin and a PWM signal output end;
when a power input pin of the PWM control chip is lower than an undervoltage defined by the chip, if an enable pin of the control chip is still in a high-level state, the control chip has the risk of undervoltage locking, Vd < Vs < Vu, Vs is the undervoltage, Vd is the lower-limit voltage of the enable pin in the high-level state, and Vu is the upper-limit voltage of the enable pin in the high-level state.
3. The power control chip enable control circuit according to claim 2,
Vs＝3V,Vd＝2V,Vu＝5V；
when the PWM control chip is locked, the PWM signal output end maintains the same level.
4. The power control chip enable control circuit according to claim 1,
the power control chip enabling control circuit also comprises a voltage division sampling circuit;
the enabling signal generating module comprises a three-end adjustable shunt reference source, a PNP triode, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a diode and a second capacitor;
the voltage division sampling circuit is connected between a power input pin of the power control chip and the ground and used for dividing the voltage of the power input pin of the power control chip to obtain a comparison sampling voltage;
when the voltage of the reference end of the three-end adjustable shunt reference source is greater than the internal reference voltage of the three-end adjustable shunt reference source, the cathode of the three-end adjustable shunt reference source is communicated with the anode of the three-end adjustable shunt reference source; when the voltage of the reference terminal is less than or equal to the voltage of the internal reference terminal, the cathode is disconnected with the anode;
the reference end of the three-end adjustable shunt reference source is connected with a comparative sampling voltage output point, the anode of the three-end adjustable shunt reference source is grounded, and the cathode of the three-end adjustable shunt reference source is connected with the base electrode of the PNP triode through a fifth resistor;
the emitter of the PNP triode is connected with the system base voltage, the collector of the PNP triode is grounded through a seventh resistor, and the collector of the PNP triode is connected with an enabling pin of the power control chip;
the sixth resistor is connected between the emitter and the base of the PNP triode;
the positive end of the diode is connected with an enabling pin of the power control chip, and the negative end of the diode is connected with the reference end of the three-end adjustable shunt reference source through a fourth resistor;
and the second capacitor is connected between the reference end of the three-end adjustable shunt reference source and the ground.
5. The power control chip enable control circuit according to claim 4,
the voltage division sampling circuit comprises a second resistor and a third resistor;
the second resistor and the third resistor are sequentially connected between a power input pin of the power control chip and the ground in series, and a connection point of the second resistor and the third resistor is used as a comparison sampling voltage output point.
6. The power control chip enable control circuit according to claim 5,
and the second resistor is used for connecting the positive end of the charging power supply and is grounded through the first capacitor.
7. The power control chip enable control circuit according to claim 5,
the power control chip enabling control circuit further comprises a first resistor;
the first resistor, the second resistor and the third resistor are sequentially connected in series between the positive ground and the ground of the charging power supply;
the first resistance is less than 1/10 of the second and third resistances.
8. The power control chip enable control circuit according to claim 7,
the second resistor, the third resistor, the fourth resistor, the fifth resistor, the sixth resistor and the seventh resistor are all kiloohm resistors, and the first resistor is smaller than 100 ohms.
9. The power control chip enable control circuit according to claim 5,
the power control chip enabling control circuit also comprises a switch tube;
the switch pipe is connected between the charging power supply and the second resistor;
the control end of the switch tube is connected with the microprocessor;
the microprocessor is used for controlling the on-off of the switch tube.
10. The power control chip enable control circuit according to claim 4,
the system base voltage is 5V, and the internal reference voltage of the three-terminal adjustable shunt reference source is 2.5V.
11. The power control chip enable control circuit according to claim 4,
the power control chip enabling control circuit also comprises a power management circuit;
the input end of the power management circuit is connected with the positive end of the charging power supply, and when the charging power supply is powered on, the power management circuit outputs system base voltage.
12. An auxiliary power supply of a vehicle-mounted charger comprising the power control chip enable control circuit of any one of claims 1 to 11.
13. The vehicle-mounted charger auxiliary power supply of claim 12, wherein the vehicle-mounted charger auxiliary power supply further comprises a flyback converter;
the power supply control chip is a PWM control chip;
and the PWM signal output by the PWM signal output end of the PWM control chip is used for controlling the on-off of a power switch device in the main circuit of the flyback converter.
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