CN215266297U - Low-thickness packaging structure of embedded chip of large-board-level fan-out substrate - Google Patents
Low-thickness packaging structure of embedded chip of large-board-level fan-out substrate Download PDFInfo
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- CN215266297U CN215266297U CN202121216085.9U CN202121216085U CN215266297U CN 215266297 U CN215266297 U CN 215266297U CN 202121216085 U CN202121216085 U CN 202121216085U CN 215266297 U CN215266297 U CN 215266297U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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Abstract
The utility model discloses a low-thickness packaging structure of a pre-embedded chip of a large-board-level fan-out substrate, which comprises a plastic packaging layer, wherein a first hole site and a second hole site are arranged along the thickness direction of the plastic packaging layer; the ASIC chip and the capacitor are packaged in the plastic packaging layer, and one sides of an I/O interface of the ASIC chip and one side of the capacitor are exposed out of the first surface of the plastic packaging layer; the first conductive column is filled in the first hole position, the second conductive column is filled in the second hole position, and the second conductive column is connected with the capacitor; the electric connection structure is positioned on the first surface of the plastic packaging layer and is connected with one end of the first conductive column, the I/O interface of the ASIC chip and the capacitor; a resistor encapsulated within the electrical connection structure; and a sensor chip connected to the electrical connection structure. The utility model discloses encapsulate into the base plate with the ASIC chip through fan-out technique, reduce packaging structure's thickness, prevent that the chip from revealing, bury electric capacity, resistance simultaneously in the base plate, further reduce packaging structure thickness, improve whole packaging structure's compactedness.
Description
Technical Field
The utility model relates to a packaging technology field, concretely relates to low thickness packaging structure of pre-buried chip of big board-level fan-out base plate.
Background
Micro-Electro-Mechanical Systems (MEMS for short) is a process technology that combines Micro-electronic technology and Mechanical engineering, and its operating range is in the micrometer range. Application Specific Integrated Circuits (ASICs) are considered to be a special purpose designed Integrated Circuit in the Integrated Circuit community.
The packaging structure of the sensor chip and the ASIC chip opens up a brand new technical field and industry, and the microsensor and the like manufactured based on the packaging structure have very wide application prospects in all fields which people can contact.
Among the prior art, the sensor chip among the general sensor module and the packaging structure of ASIC chip are directly relatively fixed or welded fastening on the PCB board through the glue film laminating with the two, so, sensor module in the use, the sealed condition of revealing of chip appears easily to this kind of packaging method will lead to the whole packaging structure thickness thickening of PCB, to some packaging structure thickness application scenes that require height, prior art obviously can't satisfy the demand.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a low thickness packaging structure of the pre-buried chip of big board-level fan-out base plate reduces packaging structure's thickness, prevents that the chip from taking place to reveal, improves whole packaging structure's compactedness.
To achieve the purpose, the utility model adopts the following technical proposal:
the utility model provides a low thickness packaging structure of pre-buried chip of big board-level fan-out base plate, includes:
the plastic packaging layer is provided with a first surface and a second surface which are arranged in a back direction along the thickness direction of the plastic packaging layer, and the plastic packaging layer is provided with a first hole site and a second hole site at intervals along the thickness direction of the plastic packaging layer;
the ASIC chip and the capacitor are packaged in the plastic package layer at intervals, an I/O interface positioned on one side of the ASIC chip and one side of the capacitor are exposed out of the first surface of the plastic package layer, and the second hole is positioned below the capacitor so that the other side of the capacitor is exposed out of the second surface of the plastic package layer;
the first conductive column is filled in the first hole position, the second conductive column is filled in the second hole position, and one end of the second conductive column is electrically connected with the capacitor;
the electrical connection structure is positioned on the first surface of the plastic package layer and is electrically connected with one end of the first conductive column, the I/O interface of the ASIC chip and the capacitor;
the resistor is packaged in the electric connection structure and is respectively and electrically connected with the ASIC chip, the capacitor and the first conductive column through the electric connection structure;
and the sensor chip is electrically connected with the electric connection structure.
As an optimal scheme of a low-thickness packaging structure of a pre-buried chip of a large board-level fan-out substrate, the electric connection structure comprises:
the first dielectric layer is positioned on the first surface of the plastic packaging layer, the first dielectric layer is provided with a third hole site for exposing the I/O interface of the ASIC chip, the capacitor and the first conductive column, and the resistor is positioned on the first dielectric layer;
a first redistribution layer located on the first dielectric layer and connected to the I/O interface of the ASIC chip, the capacitor, and the first conductive pillar through a third conductive pillar in the third hole, the first redistribution layer being electrically connected to the resistor;
a second dielectric layer located on the first redistribution layer and the first dielectric layer exposed from the first redistribution layer, the second dielectric layer being provided with a fourth hole for exposing the first redistribution layer;
and the second redistribution layer is positioned on the second dielectric layer and is connected with the first redistribution layer through a fourth conductive column in a fourth hole position.
As an optimal scheme of a low-thickness packaging structure of a pre-buried chip of a large-board-level fan-out substrate, the ASIC chip is connected with one end of a resistor through a third conductive column and a first redistribution layer respectively, the other end of the resistor is connected with one side of a capacitor through the first redistribution layer and the third conductive column, the other side of the capacitor is connected with a second conductive column, and the sensor chip is connected with the ASIC chip through the second redistribution layer, a fourth conductive column, the first redistribution layer and the third conductive column.
As an optimal scheme of a low-thickness packaging structure of a pre-embedded chip of a large-board-level fan-out substrate, the plastic packaging layer, the first dielectric layer and the second dielectric layer are provided with sound holes along the thickness direction, and the sensor chip is located on the sound holes.
The plastic package structure further comprises a third triple wiring layer, wherein the third triple wiring layer is located on the second surface of the plastic package layer and is connected with the first conductive column and the second conductive column respectively.
The sensor chip and the second redistribution layer are both located in the metal frame.
As an optimal scheme of a low-thickness packaging structure of a pre-buried chip of a large board-level fan-out substrate, the sensor chip comprises a bare chip, an I/O interface positioned in the bare chip and a connecting column which is convexly arranged outside the bare chip and electrically connected with the I/O interface, and one end, far away from the bare chip, of the connecting column is electrically connected with the second re-wiring layer.
As an optimal scheme of a low-thickness packaging structure of a pre-embedded chip of a large-board-level fan-out substrate, the first hole position, the second hole position, the third hole position and the fourth hole position are formed by communicating conical holes with adjacent upper and lower small hole ends.
As a preferable scheme of the low-thickness packaging structure of the embedded chip of the large-board-level fan-out substrate, the I/O interface of the sensor chip is arranged downwards and is connected with the second redistribution layer through welding.
As a preferred scheme of the low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate, the sensor chip is adhered to the second dielectric layer, and an I/O interface of the sensor chip is arranged upward and connected with the second redistribution layer through a wire.
The utility model has the advantages that: the utility model discloses encapsulate ASIC chip into the base plate through fan-out technique, the base plate can replace organic PCB board, realizes bearing sensor chip, electricity and connects and transmits the function of sound; pass through the mode that the glue film laminating was fixed at the PCB board with ASIC chip and IPD chip for prior art, the utility model discloses directly with ASIC chip package in the base plate, packaging structure thickness is littleer to can not take place the condition that the chip revealed, simultaneously, the utility model discloses constitute filter circuit in burying the base plate with electric capacity, resistance, for the IPD chip, the packaging structure thickness that buries the appearance and bury the resistance can further reduce to it is more nimble to bury the mounted position that the appearance buries the resistance, can effectively improve whole packaging structure's compactedness.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic cross-sectional view illustrating a plastic package layer covering an ASIC chip and a capacitor according to a first embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of the plastic package layer and the first dielectric layer after being perforated according to the first embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of the first redistribution layer according to the first embodiment of the present invention after being manufactured.
Fig. 4 is a schematic cross-sectional view of a second dielectric layer after being formed according to a first embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of the second redistribution layer according to the first embodiment of the present invention after being manufactured.
Fig. 6 is a schematic cross-sectional view of a low-thickness package structure of a pre-embedded chip of a large board-level fan-out substrate according to a first embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view of a low-thickness package structure of a pre-embedded chip of a large board-level fan-out substrate according to an embodiment of the present invention.
In fig. 1 to 7:
1. a plastic packaging layer; 11. a first side; 12. a second face;
2. an ASIC chip; 3. a capacitor;
4. an electrical connection structure; 41. a first dielectric layer; 42. a first rewiring layer; 43. a second dielectric layer; 44. a second rewiring layer;
5. a resistance; 6. a sensor chip; 7. a third triple wiring layer; 8. a metal frame;
101. a first hole site; 102. a second hole site; 103. a third hole site; 104. a fourth hole site; 105. a sound hole;
201. a first conductive post; 202. a second conductive post; 203. a third conductive pillar; 204. and a fourth conductive pillar.
Detailed Description
The technical solution of the present invention is further explained by the following embodiments with reference to the accompanying drawings.
Wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; for a better understanding of the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not indicated or implied that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are used only for illustrative purposes and are not to be construed as limiting the present patent, and the specific meaning of the terms will be understood by those skilled in the art according to the specific circumstances.
In the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" or the like, if appearing to indicate a connection relationship between the components, is to be understood broadly, for example, as being either a fixed connection, a detachable connection, or an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The first embodiment is as follows:
as shown in fig. 1 to 6, the present invention provides a low thickness package structure of a pre-embedded chip of a large board-level fan-out substrate, comprising:
the plastic packaging layer 1 is provided with a first surface 11 and a second surface 12 which are arranged in a back direction along the thickness direction of the plastic packaging layer 1, and the plastic packaging layer 1 is provided with a first hole site 101 and a second hole site 102 at intervals along the thickness direction;
the ASIC chip 2 and the capacitor 3 are packaged in the plastic package layer 1 at intervals, one side of the I/O interface and one side of the capacitor 3 which are positioned on one side of the ASIC chip 2 are exposed out of the first surface 11 of the plastic package layer 1, and the second hole 102 is positioned below the capacitor 3 so that the other side of the capacitor 3 is exposed out of the second surface 12 of the plastic package layer 1;
a first conductive pillar 201 filled in the first hole 101 and a second conductive pillar 202 filled in the second hole 102, wherein one end of the second conductive pillar 202 is electrically connected to the capacitor 3;
the electric connection structure 4 is positioned on the first surface 11 of the plastic package layer 1 and is electrically connected with one end of the first conductive pillar 201, the I/O interface of the ASIC chip 2 and the capacitor 3;
the resistor 5 is packaged in the electrical connection structure 4, and the resistor 5 is electrically connected with the ASIC chip 2, the capacitor 3 and the first conductive pillar 201 through the electrical connection structure 4;
the sensor chip 6, the sensor chip 6 and the electrical connection structure 4 are electrically connected.
The utility model encapsulates the ASIC chip 2 into a substrate by the fan-out technology, and the substrate can replace an organic PCB board to realize the functions of bearing the sensor chip 6, electrically connecting and transmitting sound; pass through the mode that the glue film laminating was fixed at the PCB board with ASIC chip 2 and IPD chip for prior art, the utility model discloses directly with ASIC chip 2 encapsulation in the base plate, packaging structure thickness is littleer to can not take place the condition that the chip revealed, simultaneously, the utility model discloses bury electric capacity 3, resistance 5 and constitute filter circuit in the base plate, for the IPD chip, bury the packaging structure thickness that the appearance buried the resistance and can further reduce to bury the mounted position that the appearance buried the resistance more nimble, can effectively improve whole packaging structure's compactedness.
Wherein, the electric connection structure 4 includes:
the first dielectric layer 41 is located on the first surface 11 of the plastic package layer 1, the first dielectric layer 41 is provided with a third hole 103 for exposing the I/O interface of the ASIC chip 2, the capacitor 3 and the first conductive pillar 201, and the resistor 5 is located on the first dielectric layer 41;
the first redistribution layer 42 is located on the first dielectric layer 41 and connected to the I/O interface of the ASIC chip 2, the capacitor 3 and the first conductive pillar 201 through the third conductive pillar 203 in the third hole 103, and the first redistribution layer 42 is electrically connected to the resistor 5;
a second dielectric layer 43 disposed on the first redistribution layer 42 and the first dielectric layer 41 exposed from the first redistribution layer 42, the second dielectric layer 43 being provided with a fourth via 104 for exposing the first redistribution layer 42;
and a second redistribution layer 44 on the second dielectric layer 43 and connected to the first redistribution layer 42 by fourth conductive pillars 204 in fourth hole sites 104.
Optionally, the first dielectric layer 41 and the second dielectric layer 43 are both made of ABF (Ajinomoto structured-up Film), PI, EMC, photoresist or PP (Polypropylene), and are attached to the first surface 11 of the plastic package layer 1 to perform an insulating function.
Optionally, the material of the first conductive pillar 201, the second conductive pillar 202, the third conductive pillar 203, and the fourth conductive pillar 204 in this embodiment is Cu, Ag, or Au.
In this embodiment, a laser drilling method may be adopted to drill the first dielectric layer 41, form the third hole site 103 exposing the I/O interface, the capacitor 3 and the first conductive pillar 201 of the ASIC chip 2, sputter a seed layer (not shown in the figure) on the surface of the third hole site 103 and the surface of the first dielectric layer 41, then copper plating, form the third conductive pillar 203 in the third hole site 103 and form the first redistribution layer 42 on the surface of the first dielectric layer 41; the fabrication of the second redistribution layer 44 is similar to the fabrication of the first redistribution layer 42, and is not described herein again.
The first redistribution layer 42 and the second redistribution layer 44 in this embodiment have the functions that an I/O interface of the ASIC chip 2 can be connected to one ends of the first conductive pillar 201 and the resistor 5 through the third conductive pillar 203 and the first redistribution layer 42, the other end of the resistor 5 can be connected to one side of the capacitor 3 through the first redistribution layer 42 and the third conductive pillar 203, the other side of the capacitor 3 is connected to the second conductive pillar 202, and the sensor chip 6 can be connected to the ASIC chip 2 through the second redistribution layer 44, the fourth conductive pillar 204, the first redistribution layer 42, and the third conductive pillar 203.
Specifically, the plastic package layer 1, the first dielectric layer 41 and the second dielectric layer 43 are provided with a sound hole 105 along the thickness direction thereof, and the sensor chip 6 is located on the sound hole 105.
The low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate further includes a third redistribution layer 7, and the third redistribution layer 7 is located on the second surface 12 of the plastic package layer 1 and is connected to the first conductive column 201 and the second conductive column 202 respectively.
The low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate further comprises a metal frame 8, wherein the metal frame 8 is located on the second dielectric layer 43, and the sensor chip 6 and the second redistribution layer 44 are both located in the metal frame 8.
Specifically, the first hole site 101, the second hole site 102, the third hole site 103 and the fourth hole site 104 are formed by communicating tapered holes with adjacent upper and lower small hole ends.
Alternatively, the first rewiring layer 42, the second rewiring layer 44, and the third rewiring layer 7 of the present embodiment may be a multilayer structure of one layer, two layers, or more than two layers, as necessary.
Specifically, the sensor chip 6 includes a bare chip, an I/O interface located in the bare chip, and a connection post protruding out of the bare chip and electrically connected to the I/O interface, and one end of the connection post away from the bare chip is electrically connected to the second redistribution layer 44.
Alternatively, the sensor chip 6 in this embodiment may employ a MEMS chip or a radio frequency chip.
More specifically, as shown in fig. 6, the I/O interface of the sensor chip 6 in the present embodiment is disposed downward, and the connection column of the sensor chip 6 is connected to the second redistribution layer 44 by soldering, which is more stable and reliable.
Example two:
the low-thickness package structure of the embedded chip of the large board-level fan-out substrate in this embodiment is basically the same as that in the first embodiment, except for the connection mode between the sensor chip 6 and the second redistribution layer 44.
As shown in fig. 7, the sensor chip 6 in this embodiment is directly adhered to the second dielectric layer 43, and the I/O interface of the sensor chip 6 is disposed upward and connected to the second redistribution layer 44 through a wire.
It should be understood that the above-described embodiments are merely illustrative of the preferred embodiments of the present invention and the technical principles thereof. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, these modifications are within the scope of the present invention as long as they do not depart from the spirit of the present invention. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description.
Claims (10)
1. The utility model provides a low thickness packaging structure of pre-buried chip of big board-level fan-out base plate which characterized in that includes:
the plastic packaging layer is provided with a first surface and a second surface which are arranged in a back direction along the thickness direction of the plastic packaging layer, and the plastic packaging layer is provided with a first hole site and a second hole site at intervals along the thickness direction of the plastic packaging layer;
the ASIC chip and the capacitor are packaged in the plastic package layer at intervals, an I/O interface positioned on one side of the ASIC chip and one side of the capacitor are exposed out of the first surface of the plastic package layer, and the second hole is positioned below the capacitor so that the other side of the capacitor is exposed out of the second surface of the plastic package layer;
the first conductive column is filled in the first hole position, the second conductive column is filled in the second hole position, and one end of the second conductive column is electrically connected with the capacitor;
the electrical connection structure is positioned on the first surface of the plastic package layer and is electrically connected with one end of the first conductive column, the I/O interface of the ASIC chip and the capacitor;
the resistor is packaged in the electric connection structure and is respectively and electrically connected with the ASIC chip, the capacitor and the first conductive column through the electric connection structure;
and the sensor chip is electrically connected with the electric connection structure.
2. The low-thickness packaging structure of embedded chips of large board-level fan-out substrate according to claim 1, wherein the electrical connection structure comprises:
the first dielectric layer is positioned on the first surface of the plastic packaging layer, the first dielectric layer is provided with a third hole site for exposing the I/O interface of the ASIC chip, the capacitor and the first conductive column, and the resistor is positioned on the first dielectric layer;
a first redistribution layer located on the first dielectric layer and connected to the I/O interface of the ASIC chip, the capacitor, and the first conductive pillar through a third conductive pillar in the third hole, the first redistribution layer being electrically connected to the resistor;
a second dielectric layer located on the first redistribution layer and the first dielectric layer exposed from the first redistribution layer, the second dielectric layer being provided with a fourth hole for exposing the first redistribution layer;
and the second redistribution layer is positioned on the second dielectric layer and is connected with the first redistribution layer through a fourth conductive column in a fourth hole position.
3. The low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate as claimed in claim 2, wherein the ASIC chip is connected to one ends of the first conductive pillars and the resistors through the third conductive pillars and the first redistribution layer, the other ends of the resistors are connected to one side of the capacitor through the first redistribution layer and the third conductive pillars, the other side of the capacitor is connected to the second conductive pillars, and the sensor chip is connected to the ASIC chip through the second redistribution layer, the fourth conductive pillars, the first redistribution layer, and the third conductive pillars.
4. The low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate as claimed in claim 3, wherein the plastic package layer, the first dielectric layer and the second dielectric layer are provided with sound holes along the thickness direction thereof, and the sensor chip is located on the sound holes.
5. The low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate as claimed in claim 4, further comprising a third redistribution layer, wherein the third redistribution layer is located on the second surface of the plastic encapsulation layer and is connected to the first conductive pillars and the second conductive pillars respectively.
6. The large board level fan-out substrate pre-buried chip low-thickness packaging structure according to claim 5, further comprising a metal frame, wherein the metal frame is located on the second dielectric layer, and the sensor chip and the second redistribution layer are both located in the metal frame.
7. The structure of claim 6, wherein the sensor chip comprises a bare chip, an I/O interface located in the bare chip, and a connection pillar protruding out of the bare chip and electrically connected to the I/O interface, and one end of the connection pillar away from the bare chip is electrically connected to the second redistribution layer.
8. The structure for packaging the embedded chips of the large board-level fan-out substrate according to any one of claims 2 to 7, wherein the first hole site, the second hole site, the third hole site and the fourth hole site are formed by communicating conical holes with adjacent upper and lower small hole ends.
9. The large board-level fan-out substrate embedded chip low-thickness packaging structure as claimed in any one of claims 2 to 7, wherein an I/O interface of the sensor chip is arranged downward and connected with the second redistribution layer through welding.
10. The large board-level fan-out substrate embedded chip low-thickness packaging structure of any one of claims 2 to 7, wherein the sensor chip is attached to the second dielectric layer, and an I/O interface of the sensor chip is disposed upward and connected to the second redistribution layer through a wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121216085.9U CN215266297U (en) | 2021-06-01 | 2021-06-01 | Low-thickness packaging structure of embedded chip of large-board-level fan-out substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121216085.9U CN215266297U (en) | 2021-06-01 | 2021-06-01 | Low-thickness packaging structure of embedded chip of large-board-level fan-out substrate |
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| Publication Number | Publication Date |
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| CN215266297U true CN215266297U (en) | 2021-12-21 |
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| CN202121216085.9U Active CN215266297U (en) | 2021-06-01 | 2021-06-01 | Low-thickness packaging structure of embedded chip of large-board-level fan-out substrate |
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- 2021-06-01 CN CN202121216085.9U patent/CN215266297U/en active Active
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