CN215264786U - Memory detection device - Google Patents

Abstract

A memory detection device comprises a test substrate, a plurality of memory modules to be detected, a central processing unit, a basic input/output system firmware, a sequence presence detection chip and a Hyper server. Therefore, the stored parameters in the SPD chip are changed through the Hyper server connected externally, various test actions can be provided, such as voltage offset setting, data storage persistence and the like, the BIOS firmware can read the parameters in the SPD chip after the startup, and at least one of the BIOS settings is partially or completely corrected, so that a large number of test substrates can be rapidly controlled, the time for setting one by one is saved, better test convenience is improved, and test efficiency is increased.

Description

Memory detection device

Technical Field

The utility model relates to a memory detection device, especially, relate to a Hyper server through the external connection changes the parameter that the sequence exists the inside storage of detection (SPD) chip, can provide and carry out multiple test action, Basic Input/Output System (Basic Input/Output System, BIOS) firmware can remove to read the inside parameter of SPD chip after the start, thereby carry out the device that partial correction or whole were rectified to at least one of a plurality of BIOS settlement, especially indicate the large batch test substrate of control that can be quick, save and need carry out the time of settlement one by one, thereby improve better test convenience, and increase the device of the efficiency of test.

Background

A computer may include a host system and one or more memory subsystems attached to the host system. The host system may have a Central Processing Unit (CPU) that communicates with a memory subsystem to store and/or retrieve data and instructions. The Memory subsystem may be a Memory Module, such as a Dual In-line Memory Module (DIMM), which refers to a series of modules including Dynamic Random Access Memory (DRAM). The DIMM is usually in the form of a printed circuit board with several to several tens of DRAM chips soldered to a fabricated circuit, and is used in personal computers, workstations, and servers.

The BIOS of the current host system is executed by a Flash memory (Flash memory) on a circuit board, which records basic input/output settings of a computer, and the circuit board further includes an SPD for controlling the DRAM. The configuration file of the BIOS program includes information about parameter settings of each hardware corresponding to a plurality of parameters, and whether the hardware is started. Conventionally, when a computer is manufactured, configuration files of these BIOS programs are mostly pre-recorded in a memory, then an operator enters a BIOS menu when starting up, sets parameters manually according to hardware configuration of a currently connected host system, finally stores the configuration files, and reloads a new BIOS configuration file after restarting.

However, the manual setting of the BIOS configuration file is a troublesome and inefficient task for computer development engineers, manufacturing and testing personnel, and the design, manufacturing and testing efficiency is not good because various hardware configured in the host system must be checked one by one. In addition, it is also difficult for the user of the general computer to set the parameters of the BIOS menu, and if the settings are not proper, the abnormal condition of the host system may occur and the host system cannot be booted smoothly. Moreover, since the configuration file loaded by the BIOS program during booting is stored in the host system in the prior art, the problem of configuration file damage or improper tampering is also easily caused, which affects the subsequent booting operation of the host system. Therefore, it is generally not suitable for the actual use of the user.

SUMMERY OF THE UTILITY MODEL

The utility model discloses a main aim at, overcome the above-mentioned problem that prior art met, and provide memory detection device, the Hyper server through outside connection changes the parameter of the inside storage of SPD chip, can provide and carry out multiple test action, the BIOS firmware can get rid of reading the inside parameter of SPD chip after the start, thereby at least one of a plurality of BIOS settlement carries out the part and rectifies or whole correction, in order to reach the large batch test base plate of control that can be quick, save the time that needs to set for one by one, thereby improve better test convenience, and increase efficiency of software testing.

In order to achieve the above purpose, the utility model adopts the technical scheme that: a memory detection device, comprising: a test substrate; a plurality of memory modules (DUT) to be tested, which are arranged on the test substrate; a central processing unit arranged on the test substrate and electrically connected to the plurality of memory modules to be tested; a BIOS firmware disposed on the test substrate and electrically connected to the CPU, and configured to provide the test substrate with screening for a plurality of memory modules to be tested; an SPD chip, which is arranged on the test substrate and is electrically connected to the BIOS firmware and the plurality of memory modules to be tested, and a plurality of parameters are stored in the SPD chip, including the main set value, the expansion set value and the BIOS command set of the memory modules, and the BIOS firmware can read the parameters from the SPD chip; and a Hyper server, which is connected to the SPD chip of the test substrate from the outside and is used for writing at least one of the BIOS command set and the set value of a plurality of BIOS settings to be changed into the SPD chip, so that when the BIOS command set is read from the SPD chip after the structured BIOS firmware is started, at least one of the BIOS settings is directly changed based on the BIOS command set and becomes effective when the computer is started next time.

In the above embodiment of the present invention, the memory module to be tested is a dual in-line memory module, and is configured to set at least one memory chip.

In the above embodiments of the present invention, the memory chip is a Dynamic Random Access Memory (DRAM).

Drawings

FIG. 1 is a block diagram of the present invention.

Reference numbers refer to:

memory detection device 100

Test substrate 1

Memory module 2 to be tested

Central processing unit 3

BIOS firmware 4

SPD chip 5

The Hyper server 6.

Detailed Description

FIG. 1 is a block diagram illustrating the present invention. As shown in the figure: the utility model relates to a memory detection device 100, it includes that a test substrate 1, several await measuring memory module (device unit test, DUT) 2, a Central Processing Unit (CPU) 3, a Basic Input/Output System (BIOS) firmware 4, a sequence exist and detect (serial present detect, SPD) chip 5, and a Hyper server 6 constitutes.

The above-mentioned memory module to be tested (DUT) 2 is disposed on the test substrate 1; each Memory Module 2 to be tested may be a Dual In-line Memory Module (DIMM) configured to set at least one Memory chip, and the Memory chip may be a Dynamic Random Access Memory (DRAM).

The cpu 3 is disposed on the test substrate 1 and electrically connected to the plurality of memory modules 2.

The BIOS firmware 4 is disposed on the test substrate 1 and electrically connected to the CPU 3. The BIOS firmware 4 is configured to provide the test substrate 1 to screen a plurality of memory modules 2 to be tested mounted thereon.

The SPD chip 5 is disposed on the test substrate 1 and electrically connected to the BIOS firmware 4 and the plurality of memory modules 2. The SPD chip 5 stores a plurality of parameters, including the main setting value, the extended setting value, and the BIOS command set of the memory module, so that the BIOS firmware 4 can read the parameters from the SPD chip 5.

The Hyper server 6 is connected to the SPD chip 5 of the test substrate 1 from the outside, and is used to write the BIOS command set and setting values of at least one of a plurality of BIOS settings to be changed into the SPD chip 5, so that when the structured BIOS firmware 4 reads the BIOS command set from the SPD chip 5 after being started, at least one of the plurality of BIOS settings is directly changed based on the BIOS command set, and becomes effective at the next startup. Thus, the completely new memory detection device 100 is constructed by the above-mentioned structure.

The main objective of the present invention is to make the BIOS firmware 4 structured to form the BIOS firmware 4 that can be controlled by the external Hyper server 6, and this structured Flash memory (Flash memory) can be directly changed. In the present embodiment, the method adopted to make the BIOS firmware 4 structurable is to change the SPD chip 5 through the Hyper server 6 connected externally.

When in use, the utility model discloses a space that does not use in SPD chip 5, on the Hyper server 6 of outside with it, later when BIOS firmware 4 starts and reads this SPD chip 5, this SPD chip 5 can link to this Hyper server 6, write into this SPD chip 5 with BIOS command set and setting value mode by this Hyper server 6 the data that will change, provide this BIOS firmware 4 and directly change at least one of several BIOS and set for based on this BIOS command set. In other words, the present invention moves some settings of the BIOS to the SPD chip 5, and after definition, the settings of the BIOS to be changed will directly affect at least one setting of the plurality of BIOS inside the BIOS firmware 4 through the SPD chip 5. Therefore, the parameters stored in the SPD chip are changed through the Hyper server connected externally, various testing actions can be provided, such as voltage offset setting, data storage persistence and the like, the BIOS firmware can read the parameters in the SPD chip after the startup, and at least one setting of the plurality of BIOS is partially or completely corrected, so that a large number of test substrates can be rapidly controlled, the time for setting one by one is saved, better testing convenience is improved, and testing efficiency is improved.

To sum up, the utility model discloses a memory detection device, can effectively improve all kinds of shortcomings of prior art, Hyper server through the outside connection changes the parameter of the inside storage of SPD chip, can provide and carry out multiple test action, the BIOS firmware can remove to read the inside parameter of SPD chip after the start, thereby at least one settlement of a plurality of BIOS carries out the part and rectifies or whole correction, in order to reach the large batch test base plate of control that can be quick, save the time that need set for one by one, thereby improve better test convenience, and increase the efficiency of test, and then make the utility model discloses a production can more progress, more practical, more accord with the user and must, really accord with the requirement of the utility model patent application, propose patent application according to law.

However, the above description is only a preferred embodiment of the present invention, and should not be taken as limiting the scope of the invention. Therefore, all simple equivalent changes and modifications made in accordance with the claims and the contents of the present specification should be included in the scope of the present application.

Claims (3)

1. A memory detection device, comprising:

a test substrate;

a plurality of memory modules to be tested, which are arranged on the test substrate;

a central processing unit arranged on the test substrate and electrically connected to the plurality of memory modules to be tested;

a BIOS firmware disposed on the test substrate and electrically connected to the CPU, and configured to provide the test substrate with screening of the memory modules to be tested;

a serial presence detection chip (SPD) chip arranged on the test substrate and electrically connected to the BIOS firmware and the memory modules to be tested, wherein the BIOS firmware and the memory modules to be tested have a plurality of parameters stored therein, including main set values, extended set values and BIOS command sets of the memory modules, and can read the parameters from the SPD chip by the BIOS firmware; and

a Hyper server connected to the SPD chip of the test substrate from outside to write at least one of the BIOS command set and the setting value of the BIOS setting to be changed into the SPD chip, so that when the BIOS command set is read from the SPD chip after the structured BIOS firmware is started, at least one setting of the BIOS is directly changed based on the BIOS command set and becomes effective at the next startup.

2. The device as claimed in claim 1, wherein the memory module under test is a dual in-line memory module for mounting at least one memory chip.

3. The memory test device of claim 2, wherein the memory chip is a dynamic random access memory.

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