CN215222163U

CN215222163U - Sampling hold circuit

Info

Publication number: CN215222163U
Application number: CN202023315106.0U
Authority: CN
Inventors: 郝海华; 郑毅
Original assignee: Beijing Radico Photoelectric Technology Co ltd
Current assignee: Beijing Radico Photoelectric Technology Co ltd
Priority date: 2020-11-25
Filing date: 2020-12-31
Publication date: 2021-12-17
Anticipated expiration: 2030-12-31

Abstract

The utility model discloses a sample hold circuit. The sampling hold circuit comprises a switch unit, a signal sampling unit and an isolation unit; the switch unit is respectively connected with the signal sampling unit and the isolation unit. When an external analog signal needs to be sampled, a sampling control signal with preset sampling time is input to the switch unit to control the on-off of the switch unit, so that the external analog signal is transmitted to the signal sampling unit, a period of time is kept without loss, and the system waits for an idle period to be processed. The sample hold circuit has the characteristics of simple structure, small occupied area of a printed circuit board and low use cost.

Description

Sampling hold circuit

Technical Field

The utility model relates to a sample hold circuit belongs to analog circuit technical field.

Background

Sample and hold external analog signals are a common mode of operation for control systems. Generally, a control system needs to face a large variety and number of external analog signals, and a core processor of the control system has difficulty in simultaneously collecting, processing and responding to a plurality of external analog signals at the same time. In this case, the core processor may select a critical analog signal to immediately process in real time, sample the analog signal that is not urgently processed, and then perform lossless retention for a period of time, and wait for the control system to process again in an idle period. In addition, the external analog signal needs to be converted into a digital signal and then processed by the system, and the analog-to-digital conversion time is long, so that the system needs to be waited for processing in an idle period so as not to affect the real-time performance of the whole system.

For a pulse current signal as shown in fig. 1, when an external analog signal is sometimes pulsed or intermittently present rather than always present, it is necessary to synchronously sample and hold the analog signal at the time of its occurrence and then process the analog signal as needed.

Currently, a sampling and holding chip is adopted to realize the sampling and holding functions of external analog signals; although the performance and the precision of the sample-and-hold chip are excellent, the sample-and-hold chip occupies a large area, is high in use cost, is not suitable for occasions with general precision requirements, such as most of the acquisition occasions of analog quantities such as temperature, voltage, current and the like, and does not require particularly high precision and performance.

Disclosure of Invention

The utility model aims to solve the technical problem that a sample hold circuit is provided.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

a sample-and-hold circuit comprises a switch unit, a signal sampling unit and an isolation unit; the switch unit is respectively connected with the signal sampling unit and the isolation unit;

the switch unit is used for receiving a sampling control signal output by an external control unit when the external analog signal needs to be sampled so as to switch to a disconnected state after the external analog signal is conducted for preset sampling time, and the signal sampling unit is enabled to finish sampling and holding of the external analog signal.

The isolation unit is used for isolating the external analog signal sampled by the signal sampling unit and outputting the external analog signal to the control unit to wait for idle time processing.

Preferably, the signal sampling unit is implemented by a sampling capacitor, one end of the sampling capacitor is connected with the switch unit and the isolation unit, and the other end of the sampling capacitor is grounded.

Preferably, the isolation unit comprises an isolation module, a first filtering module and a first protection module; the isolation module is connected with the signal sampling unit, the switch unit, the first filtering module, the first protection module and an external power module.

Preferably, the isolation module is implemented by using an operational amplifier, the first filtering module is implemented by using a first capacitor, and the first protection module is implemented by using a first resistor; the positive input end of the operational amplifier is connected with the signal sampling unit and the switch unit, the inverting input end of the operational amplifier is connected with the output end of the operational amplifier and one end of the first resistor, the other end of the first resistor is connected with an external control unit, the power supply end of the operational amplifier is connected with one end of the first capacitor and an external power supply module, and the other end of the first capacitor and the grounding end of the operational amplifier are respectively grounded.

Preferably, the switch unit comprises a switch module and a second protection module; the switch module is connected with the second protection module, the signal sampling unit, the isolation unit, an external control unit and an analog signal circuit to be sampled.

Preferably, the second protection module is implemented by using a second resistor.

Preferably, when the switch module is implemented by using an analog switch, a second filtering module is arranged in the switch unit, and the second filtering module is implemented by using a second capacitor; the normally open pin of the analog switch is connected with the analog signal circuit to be sampled through the second resistor, the control pin of the analog switch is connected with the control unit, the power pin of the analog switch is connected with an external power module and one end of the first filter capacitor respectively, the other end of the first filter capacitor and the grounding pin of the analog switch are grounded respectively, and the public pin of the analog switch is connected with the signal sampling unit and the isolation unit.

Preferably, the switch module is implemented by a PMOS transistor, a gate of the PMOS transistor is connected to an external control unit, a source of the PMOS transistor is connected to the analog signal circuit to be sampled through the second resistor, and a drain of the PMOS transistor is connected to the signal sampling unit and the isolation unit.

Preferably, the switch module is implemented by using a photoelectric coupler, the anode of the photodiode of the photoelectric coupler is connected with an external power module through a third resistor, the cathode of the photodiode is connected with the control unit, the collector of the phototriode of the photoelectric coupler is connected with the analog signal circuit to be sampled through the second resistor, and the emitter of the phototriode is connected with the signal sampling unit and the isolation unit.

Preferably, the preset sampling time is greater than the product of the second resistor and the sampling capacitor by a preset multiple.

The utility model provides a sample hold circuit builds a complete sample hold circuit with switching device, signal sampling device and isolation device, through the sampling control signal who predetermines sampling time to the switching device input to the break-make of control switching device realizes letting outside analog signal transmit to the signal sampling device on, and on the loss keeps a period, the idle period of waiting system is handled again. The sample hold circuit has the characteristics of simple structure, small occupied area of a printed circuit board and low use cost.

Drawings

FIG. 1 is a schematic diagram of sampling an external pulsed current signal;

fig. 2 is a schematic structural diagram of a sample-and-hold circuit provided by the present invention;

fig. 3 is a schematic structural diagram of an isolation unit in the sample-and-hold circuit provided by the present invention;

fig. 4 is a schematic circuit diagram 1 of a sample-and-hold circuit provided by the present invention;

fig. 5 is a schematic structural diagram of a switch unit in the sample-and-hold circuit provided by the present invention;

fig. 6 is a schematic circuit diagram 2 of a sample-and-hold circuit provided by the present invention;

fig. 7 is a schematic circuit diagram 3 of the sample-and-hold circuit provided by the present invention.

Detailed Description

The technical content of the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments.

As shown in fig. 2, the sample-and-hold circuit provided by the present invention includes a switch unit 1, a signal sampling unit 2, and an isolation unit 3; the switch unit 1 is respectively connected with the signal sampling unit 2, the isolation unit 3, an external control unit and an analog signal circuit to be sampled, and the isolation unit 3 is connected with the external control unit.

The switch unit 1 is configured to receive a sampling control signal output by an external control unit when the external analog signal needs to be sampled, so as to switch to an off state after the external analog signal is conducted for a preset sampling time, so that the signal sampling unit 2 completes sampling and holding of the external analog signal.

And the isolation unit 3 is used for isolating the external analog signal sampled by the signal sampling unit 2 and outputting the external analog signal to the control unit to wait for idle time processing.

Wherein, the external control unit can be realized by adopting a singlechip. When external analog signals need to be sampled, sampling control signals with preset sampling time are input into the switch unit 1 through the single chip microcomputer, the switch unit 1 is conducted, the external analog signals are transmitted to the signal sampling unit 2, the sampling control signals are stopped being output to the switch unit 1 after the preset sampling time is reached, the switch unit 1 is disconnected, the external analog signals are kept on the signal sampling unit 2 at the moment and are output to the single chip microcomputer after being isolated by the isolation unit 3, and the single chip microcomputer is waited to be processed when the single chip microcomputer is idle.

The utility model discloses in, treat that sampling analog signal circuit can be for temperature sensor, current sensor, voltage sensor etc. are used for exporting analog signal's equipment.

As shown in fig. 4, the signal sampling unit 2 may be implemented using a sampling capacitor Cs. One end of the sampling capacitor Cs is connected with the switch unit 1 and the isolation unit 3, and the other end of the sampling capacitor Cs is grounded. The external analog signal is sampled by a sampling capacitor. For example, to ensure sampling efficiency, the sampling capacitor needs to have the leakage current as small as possible, and the capacitance of the sampling capacitor does not exceed a preset value, and according to experience, the capacitance of the sampling capacitor does not generally exceed 1000 pF.

As shown in fig. 3, the isolation unit 3 includes an isolation module 31, a first filtering module 32, and a first protection module 33; the isolation module 31 is connected to the signal sampling unit 2, the switch unit 1, the first filtering module 32, the first protection module 33, and an external power module.

Specifically, as shown in fig. 4, the isolation module 31 may be implemented by using an operational amplifier U2, and is used for isolating the external analog signal sampled by the signal sampling unit 2 and preventing the sampled external analog signal from being attenuated. The first filtering module 32 is implemented by using a first capacitor C1, and is used for filtering the operational amplifier to ensure that the operational amplifier works normally; the first protection module 33 is implemented by using a first resistor R1, and is used for isolating an external control unit and preventing an external analog signal sampled by the output signal sampling unit 2 of the operational amplifier U2 from being influenced by the control unit. The connection relationship among the components adopted by the isolation unit 3 is as follows: the positive input end of the operational amplifier U2 is connected with one end of the sampling capacitor Cs and the switch unit 1, the inverting input end of the operational amplifier U2 is connected with the output end of the operational amplifier U2 and one end of a first resistor R1, and the other end of the first resistor R1 is connected with an external control unit; a power supply terminal of the operational amplifier U2 is connected to one terminal of the first capacitor C1 and an external power supply module, and the other terminal of the first capacitor C1 and a ground terminal of the operational amplifier U2 are grounded, respectively.

The external power module can be realized by a direct current-to-direct current power module, the direct current-to-direct current power module can generate direct current voltage required by the sampling and holding circuit, and the direct current-to-direct current power module can provide +5v voltage for the sampling and holding circuit.

As shown in fig. 5, the switching unit 1 includes a switching module 11 and a second protection module 12; the switch module 11 is connected to the second protection module 12, one end of the sampling capacitor Cs, the positive input end of the operational amplifier U2, an external control unit, and an analog signal circuit to be sampled. The second protection module 12 is implemented by using a second resistor R2, and is used for isolating an analog signal circuit to be sampled and preventing an external analog signal from being affected by the switch module 11.

The utility model provides an among the sample hold circuit, switch module 11 can adopt any one in analog switch, PMOS pipe and the optoelectronic coupler. The connection relationship and the operation principle between the switch modules 11 and other units of the sample-and-hold circuit are described in detail below with reference to fig. 4, 6 and 7.

As shown in fig. 4, the switch module 11 may be implemented using an analog switch U1. In order to ensure that the analog switch U1 works normally, a second filtering module 13 is disposed in the switch unit 1, and the second filtering module 13 is implemented by using a second capacitor C2 and is used for filtering the analog switch U1. The normally open pin NO of the analog switch U1 is connected with an analog signal circuit to be sampled through a second resistor R2, a control pin IN of the analog switch U1 is connected with an external control unit, a power supply pin VCC of the analog switch U1 is respectively connected with an external power supply module and one end of a first filter capacitor C1, the other end of the first filter capacitor C1 and a grounding pin of the analog switch U1 are respectively grounded, and a common pin COM of the analog switch U1 is connected with one end of a sampling capacitor Cs and a positive input end of an operational amplifier U2.

An external analog signal IF is transmitted to a normally open pin NO of an analog switch U1 through a second resistor R2, when the external analog signal is required to be sampled, a sampling control signal Pulse _ S with preset sampling time, which is input to a control pin IN of the analog switch U1 by a control unit, is at a high level, so that the normally open pin NO of the analog switch U1 is conducted with a common pin COM, and at the moment, the external analog signal IF is transmitted to the common pin COM of the analog switch U1 through the normally open pin NO of the analog switch U1 through the inside of the analog switch U1 and is stored on a sampling capacitor Cs. When the time of the sampling control signal Pulse _ S input to the control pin IN of the analog switch U1 by the control unit reaches the sampling time, the sampling control signal Pulse _ S input to the control pin IN of the analog switch U1 by the control unit is converted to a low level, so that the normally open pin NO and the common pin COM of the analog switch U1 are disconnected, and at this time, the external analog signal is held on the sampling capacitor Cs, isolated by the operational amplifier U2, and output from the other end of the first resistor R1 to the control unit, and is processed when the control unit is idle.

As shown in fig. 6, the switch module 11 may be implemented by a PMOS transistor Q1. The grid electrode of the PMOS tube Q1 is connected with an external control unit, the source electrode of the PMOS tube Q1 is connected with an analog signal circuit to be sampled through a second resistor R2, and the drain electrode of the PMOS tube Q1 is connected with one end of a sampling capacitor Cs and the positive input end of an operational amplifier U2.

When the external analog signal IF is required to be sampled, the control unit inputs a sampling control signal Pulse _ S with a preset sampling time to the gate of the PMOS transistor Q1 to a low level, so that the PMOS transistor Q1 is turned on, and at this time, the external analog signal IF is transmitted from the source of the PMOS transistor Q1 to the drain of the PMOS transistor Q1 through the inside of the PMOS transistor Q1, and is stored in the sampling capacitor Cs. When the time of the sampling control signal Pulse _ S input to the gate of the PMOS transistor Q1 by the control unit reaches the sampling time, the sampling control signal Pulse _ S input to the gate of the PMOS transistor Q1 by the control unit is changed to a high level, so that the PMOS transistor Q1 is turned off, and at this time, the external analog signal is held on the sampling capacitor Cs, isolated by the operational amplifier U2, and then output from the other end of the first resistor R1 to the control unit, and is processed when the control unit is idle.

As shown in fig. 7, the switch module 11 may be implemented by a photo-coupler OP 1. The positive pole of the photodiode of the photoelectric coupler OP1 is connected with an external power module through a third resistor, the negative pole of the photodiode is connected with an external control unit, the collector of the phototriode of the photoelectric coupler OP1 is connected with an analog signal circuit to be sampled through a second resistor R2, and the emitter of the phototriode is connected with one end of a sampling capacitor Cs and the positive input end of an operational amplifier U2.

An external analog signal IF is transmitted to a collector electrode of a phototriode in the photoelectric coupler OP1 through a second resistor R2, when the external analog signal is required to be sampled, a sampling control signal Pulse _ S with preset sampling time, which is input to a cathode of a photodiode of the photoelectric coupler OP1 by a control unit, is converted into low level, the photodiode emits light, so that a phototriode of the photoelectric coupler OP1 is in a conducting state, at the moment, the external analog signal IF is transmitted to an emitter electrode of the phototriode through the interior of the phototriode of the photoelectric coupler OP1 and is stored on a sampling capacitor Cs

When the time of the sampling control signal Pulse _ S input to the cathode of the photodiode of the photocoupler OP1 by the control unit reaches the sampling time, the sampling control signal Pulse _ S input to the cathode of the photodiode of the photocoupler OP1 by the control unit is changed to a high level, so that the photocoupler OP1 is turned off, and at this time, the external analog signal is kept on the sampling capacitor Cs, isolated by the operational amplifier U2, and output from the other end of the first resistor R1 to the control unit, and is processed when the control unit is idle.

In order to ensure both the efficiency of sampling the analog signal and the integrity of the sampled analog signal, the product of the second resistor R2 and the sampling capacitor Cs, which is greater than 3-5 times the preset sampling time, is required. For example, the resistance of the second resistor R2 is 1K Ω, the capacitance of the sampling capacitor Cs is 1nF, and the product of the second resistor R2 and the sampling capacitor Cs is 1us, so that the preset sampling time is greater than 3-5 us.

The utility model discloses in, switch module 11 can encapsulate to SC70-6, and overall dimension is only 2.2mm 2.45mm, and switching frequency can reach 300MHZ, and the cost is about 0.4 yuan/piece. The isolation module 31 can be packaged as an SC-70, with the external dimension of only 2.2mm by 2.4mm, and the cost of about 0.7 yuan/chip. The cost of the sample-and-hold circuit can be as low as 1 yuan, and the occupied area of the sample-and-hold circuit is equivalent to the size of an SOP8 integrated chip.

The area of the sampling and holding circuit is very small, so that the corresponding sampling and holding circuit can be arranged at the position of the printed circuit board close to one or more analog signal circuits to be sampled, the arrangement mode can facilitate the wiring of the printed circuit board, and an external control unit can process the sampled analog signals at an idle time period conveniently. For example, 3 external analog signals, namely, one current analog signal on the left side of the pcb, one voltage analog signal on the right side of the pcb, and one temperature analog signal on the top of the pcb, need to be sampled. At this moment, the sampling and holding circuit can be respectively arranged on the position of the printed circuit board close to the current, voltage and temperature analog signals to be sampled, and the sampling and holding of a plurality of external analog signals can be realized under the condition of as few wiring as possible.

The utility model provides a sample hold circuit builds a complete sample hold circuit with switching device, signal sampling device and isolation device, through the sampling control signal who predetermines sampling time to the switching device input to control switching device's break-make realizes letting outside analog signal transmit to the signal sampling device on, and on not having the loss to keep a period, the idle period of waiting system is handled again. The sample hold circuit has the characteristics of simple structure, small occupied area of a printed circuit board and low use cost.

The sample-and-hold circuit provided by the present invention has been described in detail above. Any obvious modifications to the device, which would be obvious to those skilled in the art, without departing from the essential spirit of the invention, are intended to be covered by the appended claims.

Claims

1. A sample-and-hold circuit is characterized by comprising a switch unit, a signal sampling unit and an isolation unit; the switch unit is respectively connected with the signal sampling unit and the isolation unit;

the switch unit is used for receiving a sampling control signal output by an external control unit when the external analog signal needs to be sampled, and switching to a disconnected state after preset sampling time, so that the signal sampling unit finishes sampling and holding of the external analog signal;

and the isolation unit is used for isolating the external analog signal sampled by the signal sampling unit and outputting the external analog signal to the control unit to wait for idle time processing.

2. The sample-and-hold circuit of claim 1, wherein:

the signal sampling unit is realized by adopting a sampling capacitor, one end of the sampling capacitor is connected with the switch unit and the isolation unit, and the other end of the sampling capacitor is grounded.

3. The sample-and-hold circuit of claim 1, wherein:

the isolation unit comprises an isolation module, a first filtering module and a first protection module; the isolation module is connected with the signal sampling unit, the switch unit, the first filtering module, the first protection module and an external power module.

4. The sample-and-hold circuit of claim 3, wherein:

the isolation module is realized by adopting an operational amplifier, the first filtering module is realized by adopting a first capacitor, and the first protection module is realized by adopting a first resistor; the positive input end of the operational amplifier is connected with the signal sampling unit and the switch unit, the inverting input end of the operational amplifier is connected with the output end of the operational amplifier and one end of the first resistor, the other end of the first resistor is connected with an external control unit, the power supply end of the operational amplifier is connected with one end of the first capacitor and an external power supply module, and the other end of the first capacitor and the grounding end of the operational amplifier are respectively grounded.

5. The sample-and-hold circuit of claim 4, wherein:

the switch unit comprises a switch module and a second protection module; the switch module is connected with the second protection module, the signal sampling unit, the isolation unit, the control unit and the analog signal circuit to be sampled.

6. The sample and hold circuit of claim 5, wherein:

the second protection module is realized by adopting a second resistor.

7. The sample and hold circuit of claim 6, wherein:

when the switch module is realized by adopting an analog switch, a second filtering module is arranged in the switch unit and is realized by adopting a second capacitor; the normally open pin of the analog switch is connected with the analog signal circuit to be sampled through the second resistor, the control pin of the analog switch is connected with the control unit, the power pin of the analog switch is connected with an external power module and one end of the first capacitor respectively, the other end of the first capacitor and the grounding pin of the analog switch are grounded respectively, and the public pin of the analog switch is connected with the signal sampling unit and the isolation unit.

8. The sample and hold circuit of claim 6, wherein:

the switch module is realized by adopting a PMOS (P-channel metal oxide semiconductor) tube, the grid electrode of the PMOS tube is connected with the control unit, the source electrode of the PMOS tube is connected with the analog signal circuit to be sampled through the second resistor, and the drain electrode of the PMOS tube is connected with the signal sampling unit and the isolation unit.

9. The sample and hold circuit of claim 6, wherein:

the switch module is realized by adopting a photoelectric coupler, the anode of a photodiode of the photoelectric coupler is connected with an external power module through a third resistor, the cathode of the photodiode is connected with the control unit, the collector of a phototriode of the photoelectric coupler is connected with the analog signal circuit to be sampled through a second resistor, and the emitter of the phototriode is connected with the signal sampling unit and the isolation unit.

10. The sample-and-hold circuit of claim 1, wherein:

and the preset sampling time is greater than the product of the second resistor and the sampling capacitor by a preset multiple.