CN215183975U - Buried layer terminal structure - Google Patents

Abstract

The application discloses a buried layer terminal structure, which comprises an N-type semiconductor drift region, wherein the N-type semiconductor drift region comprises a P-type semiconductor field limiting ring, a P-type semiconductor buried layer and an N + type semiconductor field limiting ring, the width of the P-type semiconductor field limiting ring is larger than or equal to that of the N-type semiconductor field limiting ring, and the concentration of doped ions in the P-type semiconductor buried layer is smaller than that of the doped ions in the P-type semiconductor field limiting ring; the insulating medium layer is arranged on the upper surface of the N-type semiconductor drift region and is respectively contacted with the upper surface of part of the P-type semiconductor field limiting ring, the upper surface of part of the P-type semiconductor buried layer and the upper surface of part of the N + type semiconductor field limiting ring, and a contact hole is formed in a contact region of the insulating medium layer and the P-type semiconductor buried layer; and the first field plate is contacted with the P-type semiconductor buried layer through the contact hole. This application can make buried layer terminal structure be difficult to puncture under high temperature, and reliability and stability are better.

Description

Buried layer terminal structure

Technical Field

The application relates to the technical field of power semiconductor devices, in particular to a buried layer terminal structure.

Background

The power semiconductor device needs to select a proper terminal structure according to the application field, and the proportion of the terminal size in the chip is reduced, so that the current density of the chip under the same area can be improved. Since the JTE (junction termination extension) structure is proposed, the size of the power semiconductor device terminal gradually moves toward miniaturization.

As shown in fig. 1, a conventional JTE terminal generally includes: the semiconductor device comprises a cathode 1, an N + type semiconductor substrate 2, an N-type semiconductor drift region 3, a P-type semiconductor doping region 40, a P-type semiconductor doping junction terminal expansion region 50, an N + type semiconductor field limiting ring 6, an insulating medium layer 7, an anode 8 and a metal field plate 9; the traditional JTE terminal has the problems of low doping dosage of the terminal and the like. In order to solve the above problems, the existing improvement methods mainly include: deforming the structure of the traditional JTE terminal, or prolonging the knot pushing time to enable the knot depth to be deeper, and the like; however, the terminals obtained by the improved methods have unstable breakdown at high temperature, and are particularly susceptible to surface fixed charges.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present application provides a buried termination structure to solve the problems of instability at high temperature and susceptibility to the influence of the introduced surface fixed charges in the conventional power semiconductor device termination.

The application provides a buried layer terminal structure, this buried layer terminal structure includes: an N + type semiconductor substrate; the N-type semiconductor drift region is arranged on the upper surface of the N + type semiconductor substrate and comprises a P-type semiconductor field limiting ring, a P-type semiconductor buried layer and an N + type semiconductor field limiting ring, the P-type semiconductor buried layer and the N + type semiconductor field limiting ring respectively extend from the upper surface of the N-type semiconductor drift region to the inside, one side surface of the P-type semiconductor field limiting ring is flush with one side surface of the N-type semiconductor drift region, the P-type semiconductor buried layer is in contact with the junction of the bottom surface and the other side surface of the P-type semiconductor field limiting ring, a gap is reserved between the P-type semiconductor buried layer and the N + type semiconductor field limiting ring, and the other side surface of the N + type semiconductor field limiting ring is flush with the other side surface of the N-type semiconductor drift region, the width of the P-type semiconductor field limiting ring is greater than or equal to that of the N + type semiconductor field limiting ring; the concentration of the doped ions in the P-type semiconductor buried layer is smaller than that of the doped ions in the P-type semiconductor field limiting ring; the insulating medium layer is arranged on the upper surface of the N-type semiconductor drift region, is respectively contacted with the partial upper surface of the P-type semiconductor field limiting ring, the partial upper surface of the P-type semiconductor buried layer and the partial upper surface of the N + type semiconductor field limiting ring, and is provided with a contact hole in a contact region with the P-type semiconductor buried layer; the anode extends outwards from the upper surface of the P-type semiconductor field limiting ring and covers one side surface and part of the upper surface of the insulating medium layer; the first field plate extends outwards from the upper surface of the P-type semiconductor buried layer, covers part of the upper surface of the insulating medium layer and fills the contact hole, and a gap is reserved between the first field plate and the anode; the metal field plate is arranged opposite to the anode, extends outwards from the upper surface of the N + type semiconductor field limiting ring, covers the other side surface and part of the upper surface of the insulating medium layer, and has a gap with the first field plate; and the cathode is arranged on the bottom surface of the N + type semiconductor substrate.

The first field plate is a metal field plate or a polysilicon field plate.

Wherein the P-type semiconductor buried layer comprises a convex part and a non-convex part, the convex part is arranged on part of the upper surface of the non-convex part, the upper surface of the convex part is contacted with the lower surface of the insulating medium layer, and is contacted with the first field plate through the contact hole, the other side surface of the convex part is connected with the other side surface of the non-convex part to form the other side surface of the P-type semiconductor buried layer, the width of the convex part is smaller than that of the non-convex part, the upper surface of the non-convex part is contacted with the other side surface of the P-type semiconductor field limiting ring, one side surface of the non-protruding part is in contact with part of the bottom surface of the P-type semiconductor field limiting ring, and a gap is reserved between the upper surface of the non-protruding part and the upper surface of the N-type semiconductor drift region.

The depth of the P-type semiconductor field limiting ring is greater than that of the convex part, and the depth of the P-type semiconductor field limiting ring is less than the sum of the depth of the convex part and the depth of the non-convex part.

The width of the non-convex part is larger than or equal to that of the P-type semiconductor field limiting ring, and the width of the P-type semiconductor field limiting ring is larger than that of the convex part.

Wherein the non-convex part has a strip-shaped structure or an inverted trapezoid structure.

The insulating medium layer comprises an oxide layer, and the oxide layer is a silicon dioxide layer.

The insulating medium layer further comprises a passivation layer which is arranged on the upper surface of the oxide layer and forms the insulating medium layer with the oxide layer.

The buried layer terminal structure further comprises a P-type semiconductor doped region arranged between the N + type semiconductor substrate and the cathode.

And the concentration of the doping ions in the P-type semiconductor doping region is smaller than that of the doping ions in the P-type semiconductor field limiting ring and is larger than that of the doping ions in the P-type semiconductor buried layer.

The utility model provides an above-mentioned buried layer terminal structure, through set up first field board on insulating medium layer, make first field board pass through the contact hole and the terminal (the part that is close to the upper surface in N type semiconductor drift region of P type semiconductor buried layer) contact in JTE region, thereby make first field board and JTE inject into regional N + type semiconductor substrate and realize electricity contact, so can alleviate the regional afterbody electric field of JTE, can avoid the unstable problem of electric potential that the totally floating field board brought simultaneously, can realize higher and more stable breakdown voltage. Because the electric field at the tail part of the JTE region is relieved, the buried layer terminal structure is not easily influenced by surface fixed charges introduced by a manufacturing process line, so that the buried layer terminal structure is not easily broken down at high temperature, and the reliability and the stability are better.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a conventional JTE terminal in the prior art;

fig. 2 is a schematic diagram of a buried layer termination structure according to an embodiment of the present application;

fig. 3 is a schematic flow chart of a method for fabricating a buried termination structure according to an embodiment of the present application.

Each reference numeral represents:

1. a cathode; 2. an N + type semiconductor substrate; 3. an N-type semiconductor drift region; 4. a P-type semiconductor field limiting ring; 5. a P-type semiconductor buried layer; 6. an N + type semiconductor field limiting ring; 7. an insulating dielectric layer; 8. an anode; 9. a metal field plate; 10. a first field plate; 11. a contact hole;

40. a P-type semiconductor doped region; 50. a P-type semiconductor doped junction termination extension region;

51. a non-convex portion; 52. a convex portion;

x, horizontal direction.

Detailed Description

The technical solutions in the embodiments of the present application are described below with reference to the accompanying drawings, and the embodiments and technical features thereof described below may be combined with each other without conflict.

Referring to fig. 2, an embodiment of the present application provides a buried termination structure, including:

an N + type semiconductor substrate 2;

an N-type semiconductor drift region (N-drift)3 arranged on the upper surface of the N + type semiconductor substrate 2, wherein the N-type semiconductor drift region 3 comprises a P-type semiconductor field limiting ring 4, a P-type semiconductor buried layer 5 and an N + type semiconductor field limiting ring 6, the P-type semiconductor field limiting ring 4, the P-type semiconductor buried layer 5 and the N + type semiconductor field limiting ring 6 respectively extend from the upper surface of the N-type semiconductor drift region 3 to the inside, one side surface of the P-type semiconductor field limiting ring 4 is flush with one side surface of the N-type semiconductor drift region 3, the P-type semiconductor buried layer 5 is in contact with the junction of the bottom surface and the other side surface of the P-type semiconductor field limiting ring 4, a gap is reserved between the P-type semiconductor buried layer 5 and the N + type semiconductor field limiting ring 6, the other side surface of the N + type semiconductor field limiting ring 6 is flush with the other side surface of the N-type semiconductor drift region 3, and the width of the P type semiconductor field limiting ring 4 is greater than or equal to that of the N + type semiconductor field limiting ring 6; the concentration of the doped ions in the P-type semiconductor buried layer 5 is less than that of the doped ions in the P-type semiconductor field limiting ring 4;

the insulating medium layer 7 is arranged on the upper surface of the N-type semiconductor drift region 3, is respectively contacted with the partial upper surface of the P-type semiconductor field limiting ring 4, the partial upper surface of the P-type semiconductor buried layer 5 and the partial upper surface of the N + type semiconductor field limiting ring 6, and is provided with a contact hole 11 in a contact region with the P-type semiconductor buried layer 5;

the anode 8 extends outwards from the upper surface of the P-type semiconductor field limiting ring 4 and covers one side surface and part of the upper surface of the insulating medium layer 7;

the first field plate 10 extends outwards from the upper surface of the P-type semiconductor buried layer 5, covers part of the upper surface of the insulating dielectric layer 7, fills the contact hole 11 and has a gap with the anode 8;

the metal field plate 9 is arranged opposite to the anode 8, extends outwards from the upper surface of the N + type semiconductor field limiting ring 6, covers the other side surface and part of the upper surface of the insulating medium layer 7, and has a gap with the first field plate 10;

and a cathode 1 provided on the bottom surface of the N + type semiconductor substrate 2. It should be understood that the bottom surface of the N + -type semiconductor substrate 2 is disposed opposite to the upper surface of the N + -type semiconductor substrate 2.

In this embodiment, the first field plate is disposed on the insulating medium layer, and the first field plate is in contact with the end of the JTE region (i.e., the portion of the P-type semiconductor buried layer near the upper surface of the N-type semiconductor drift region) through the contact hole, so that the first field plate is in electrical contact with the N + type semiconductor substrate of the JTE injection region, thereby alleviating a tail electric field of the JTE region, and avoiding a potential instability problem caused by a completely floating field plate, and achieving a higher and more stable breakdown voltage. The buried layer terminal structure of the embodiment has better reliability at high temperature, is not easily influenced by surface fixed charges introduced by a manufacturing process line, and is particularly suitable for a high-voltage terminal structure.

In particular, the buried layer termination structure of the present embodiment may be used as a termination of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) device or a Fast Recovery Diode (FRD) device. Now, the operation principle of the buried layer terminal structure of this embodiment will be described by taking an FRD device as an example. When forward bias is applied to the cathode 1, and the anode 8 is grounded, the PN junction in the buried layer terminal structure is in a reverse bias state, the P-type semiconductor buried layer 5 is fully depleted due to light doping, and the P-type semiconductor buried layer 5 is connected with the first field plate 10 through the contact hole 11, so that the potential of the first field plate 10 is stabilized, and stable breakdown is realized.

In some embodiments, the first field plate 10 is a metal field plate or a polysilicon field plate. Illustratively, the metal field plate may be an aluminum field plate, a copper field plate, or an aluminum-copper alloy field plate, etc. Optionally, the buried layer terminal structure is an FRD terminal, and the first field plate 10 is a metal field plate; or, the buried layer terminal structure is an Insulated Gate Bipolar Transistor (IGBT) terminal, and the first field plate 10 is a metal field plate or a polysilicon field plate.

In some embodiments, the material of the first field plate 10 at the contact hole 11 may be the same as or different from the material of the region of the first field plate 10 at the upper surface of the insulating dielectric layer 7; that is, the contact hole 11 may be formed and then ion implantation may be performed or not.

In some embodiments, the dopant ions in the P-type buried semiconductor layer 5 are uniformly distributed or graded along the horizontal direction X. Illustratively, the concentration of the dopant ions in the P-type buried semiconductor layer 5 may gradually become larger or smaller along the horizontal direction X.

In some embodiments, the dopant ions in the P-type semiconductor field limiting ring 4 are the same as the dopant ions in the P-type semiconductor buried layer 5.

In some embodiments, the P-type buried semiconductor layer 5 includes a convex portion 52 and a non-convex portion 51, the convex portion 52 is provided on a part of the upper surface of the non-convex portion 51, the upper surface of the convex portion 52 is in contact with a part of the lower surface of the insulating medium layer 7, and is in contact with the first field plate 10 through the contact hole 11, the other side surface of the convex portion 52 is connected with the other side surface of the non-convex portion 51 to form the other side surface of the P-type buried semiconductor layer 5, the width of the convex portion 52 is smaller than that of the non-convex portion 51, the upper surface of the non-convex portion 51 is in contact with the other side surface of the P-type semiconductor field limiting ring 4, a side surface of the non-projecting portion 51 is in contact with a part of the bottom surface of the P-type semiconductor field limiting ring 4, there is a gap between the upper surface of the non-convex portion 51 and the upper surface of the N-type semiconductor drift region 3.

Further in some embodiments, the species and concentration of dopant ions in the raised portion 52 are the same as the species and concentration of dopant ions in the non-raised portion 51 at the same horizontal position.

In some embodiments, the depth of the P-type semiconductor field limiting ring 4 is greater than the depth of the convex portion 52, and the depth of the P-type semiconductor field limiting ring 4 is less than the sum of the depth of the convex portion 52 and the depth of the non-convex portion 51.

In some embodiments, the depth of the P-type semiconductor field limiting rings 4 is greater than or equal to the depth of the N + type semiconductor field limiting rings 6.

In some embodiments, the width of the non-protruding portion 51 is greater than or equal to the width of the P-type semiconductor field limiting ring 4, and the width of the P-type semiconductor field limiting ring 4 is greater than the width of the protruding portion 52.

In some embodiments, the non-raised portion 51 has an elongated configuration or an inverted trapezoidal configuration.

In some embodiments, the insulating dielectric layer 7 includes an oxide layer (not shown), which is a silicon dioxide layer. It should be understood that the insulating medium layer 7 may have a single-layer structure or a multi-layer structure. Illustratively, the insulating medium layer 7 has a single-layer structure, and the insulating medium layer 7 may be an oxide layer.

In other embodiments, the insulating dielectric layer 7 has a multi-layer structure, and the insulating dielectric layer 7 further includes a passivation layer (not shown) disposed on the upper surface of the oxide layer to form the insulating dielectric layer 7 with the oxide layer. Illustratively, the passivation layer may be, but is not limited to, a silicon nitride layer.

In other embodiments, the buried termination structure further includes a P-type semiconductor doped region (not shown) disposed between the N + semiconductor substrate 2 and the cathode 1. In this manner, IGBT terminations may be formed.

Further in some embodiments, the dopant ions in the P-type semiconductor doped region, the dopant ions in the P-type semiconductor field limiting ring 4 and the dopant ions in the P-type semiconductor buried layer 5 are the same, and the concentration of the dopant ions in the P-type semiconductor doped region is less than the concentration of the dopant ions in the P-type semiconductor field limiting ring 4 and greater than the concentration of the dopant ions in the P-type semiconductor buried layer 5.

In some embodiments, the N + -type semiconductor substrate 2 may be, but is not limited to, a silicon-based semiconductor substrate, and the N + -type semiconductor substrate 2 may be, for example, a silicon wafer.

In some embodiments, the Cathode 1(Cathode) may be a metal electrode or a non-metal electrode; and/or, the Anode (Anode)8 may be, but is not limited to, a metal electrode, and for example, the Anode 8 may be an aluminum electrode, a copper electrode, an aluminum-copper alloy electrode, or the like.

In some embodiments, the material of the metal field plate 9 may be aluminum, copper or aluminum-copper alloy, etc.

In some embodiments, the N-type semiconductor drift region 3 may be, but is not limited to, a layer of N-type semiconductor material or a layer of phosphorus doped N-type semiconductor material.

In some embodiments, the P-type semiconductor field limiting ring 4 may be an N-type semiconductor drift region 3 implanted with boron (B) ions; the P-type semiconductor buried layer 5 can be an N-type semiconductor drift region 3 implanted with B ions; the N + -type semiconductor field limiting ring 6 may be an N-type semiconductor drift region 3 implanted with arsenic (As) ions and/or phosphorus (P) ions.

In some embodiments, the one side may be a left side and the other side may be a right side.

Referring to fig. 3, an embodiment of the present application further provides a method for fabricating a buried termination structure as described above, including the following steps.

And S1, providing an N + type semiconductor substrate 2, and forming an N-type semiconductor drift region 3 on the upper surface of the N + type semiconductor substrate 2 through epitaxial growth. It should be understood that the number of epitaxial growings may be one or more.

And S2, forming an insulating medium layer 7 on the upper surface of the N-type semiconductor drift region 3.

S3, forming a P-type semiconductor field limiting ring 4 in the N-type semiconductor drift region 3 through photoetching and first ion implantation in sequence; and then, forming a P-type semiconductor buried layer 5 in the N-type semiconductor drift region 3 through photoetching and second ion implantation in sequence.

In some embodiments, in step S1, the epitaxial growth is an N-type epitaxial growth. In some embodiments, the etching is performed by dry etching, such as Reactive Ion Etching (RIE).

In some embodiments, in the step S3, the first ion implantation is boron ion implantation, and the second ion implantation is boron ion implantation.

In some embodiments, in the step S3, the number of times of the second ion implantation is one or two. That is, the non-convex portion 51 of the P-type buried semiconductor layer 5 may be formed by a first second ion implantation, and then the convex portion 52 of the P-type buried semiconductor layer 5 may be formed by a second ion implantation; alternatively, the non-convex portion 51 and the convex portion 52 of the P-type buried semiconductor layer 5 are simultaneously formed by one second ion implantation.

And S4, sequentially carrying out photoetching and third ion implantation to form an N + type semiconductor field limiting ring 6 in the N-type semiconductor drift region 3.

In some embodiments, in the step S4, the third ion implantation is arsenic ion and/or phosphorus ion implantation.

And S5, covering part of the upper surface of the N-type semiconductor drift region 3 and part of the upper surface of the insulating dielectric layer 7 through ion sputtering to form an anode 8, a first field plate 10 and a metal field plate 9 respectively.

And S6, depositing a cathode material on the bottom surface of the N + type semiconductor substrate 2 through ion sputtering to form a cathode 1.

In some embodiments, the first ion implantation, the second ion implantation, and the third ion implantation are followed by a high temperature ramp, wherein the temperature of the high temperature ramp is 900-. Optionally, the high temperature propelled gas atmosphere is N₂。

In other embodiments, the step S3 may be performed before the step S2.

The preparation method of the buried layer terminal structure is simple and is easy to realize large-scale production.

Although the application has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. This application is intended to embrace all such modifications and variations and is limited only by the scope of the appended claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification.

That is, the above description is only an embodiment of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by using the contents of the specification and the drawings, such as mutual combination of technical features between various embodiments, or direct or indirect application to other related technical fields, are included in the scope of the present application.

In addition, in the description of the present application, it is to be understood that the terms "depth", "width", "upper", "lower", "left", "right", "horizontal", "bottom", "inner", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present application. In addition, structural elements having the same or similar characteristics may be identified by the same or different reference numerals. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Claims (10)

1. A buried layer termination structure, comprising:

an N + type semiconductor substrate;

the N-type semiconductor drift region is arranged on the upper surface of the N + type semiconductor substrate and comprises a P-type semiconductor field limiting ring, a P-type semiconductor buried layer and an N + type semiconductor field limiting ring, the P-type semiconductor buried layer and the N + type semiconductor field limiting ring respectively extend from the upper surface of the N-type semiconductor drift region to the inside, one side surface of the P-type semiconductor field limiting ring is flush with one side surface of the N-type semiconductor drift region, the P-type semiconductor buried layer is in contact with the junction of the bottom surface and the other side surface of the P-type semiconductor field limiting ring, a gap is reserved between the P-type semiconductor buried layer and the N + type semiconductor field limiting ring, and the other side surface of the N + type semiconductor field limiting ring is flush with the other side surface of the N-type semiconductor drift region, the width of the P-type semiconductor field limiting ring is greater than or equal to that of the N + type semiconductor field limiting ring; the concentration of the doped ions in the P-type semiconductor buried layer is smaller than that of the doped ions in the P-type semiconductor field limiting ring;

the insulating medium layer is arranged on the upper surface of the N-type semiconductor drift region, is respectively contacted with the partial upper surface of the P-type semiconductor field limiting ring, the partial upper surface of the P-type semiconductor buried layer and the partial upper surface of the N + type semiconductor field limiting ring, and is provided with a contact hole in a contact region with the P-type semiconductor buried layer;

the anode extends outwards from the upper surface of the P-type semiconductor field limiting ring and covers one side surface and part of the upper surface of the insulating medium layer;

the first field plate extends outwards from the upper surface of the P-type semiconductor buried layer, covers part of the upper surface of the insulating medium layer and fills the contact hole, and a gap is reserved between the first field plate and the anode;

the metal field plate is arranged opposite to the anode, extends outwards from the upper surface of the N + type semiconductor field limiting ring, covers the other side surface and part of the upper surface of the insulating medium layer, and has a gap with the first field plate;

and the cathode is arranged on the bottom surface of the N + type semiconductor substrate.

2. The buried termination structure of claim 1, wherein the first field plate is a metal field plate or a polysilicon field plate.

3. The buried termination structure of claim 1, wherein the P-type buried semiconductor layer includes a raised portion and a non-raised portion, the convex part is arranged on part of the upper surface of the non-convex part, the upper surface of the convex part is contacted with the lower surface of the insulating medium layer, and is contacted with the first field plate through the contact hole, the other side surface of the convex part is connected with the other side surface of the non-convex part to form the other side surface of the P-type semiconductor buried layer, the width of the convex part is smaller than that of the non-convex part, the upper surface of the non-convex part is contacted with the other side surface of the P-type semiconductor field limiting ring, one side surface of the non-protruding part is in contact with part of the bottom surface of the P-type semiconductor field limiting ring, and a gap is reserved between the upper surface of the non-protruding part and the upper surface of the N-type semiconductor drift region.

4. The buried layer terminal structure of claim 3, wherein a depth of the P-type semiconductor field limiting ring is greater than a depth of the raised portion, and the depth of the P-type semiconductor field limiting ring is less than a sum of the depth of the raised portion and the depth of the non-raised portion.

5. The buried layer termination structure of claim 3, wherein a width of the non-protruding portion is greater than or equal to a width of the P-type semiconductor field limiting ring, and the width of the P-type semiconductor field limiting ring is greater than the width of the protruding portion.

6. The buried layer termination structure of claim 3, wherein the non-protruding portions have an elongated configuration or an inverted trapezoidal configuration.

7. The buried layer termination structure of claim 1, wherein the insulating dielectric layer comprises an oxide layer, and the oxide layer is a silicon dioxide layer.

8. The buried termination structure of claim 7, wherein the insulating dielectric layer further comprises a passivation layer disposed on an upper surface of the oxide layer.

9. The buried termination structure of claim 1, further comprising a P-type semiconductor doped region disposed between the N + type semiconductor substrate and the cathode.

10. The buried layer terminal structure of claim 9, wherein the dopant ions in the P-type semiconductor doped region, the dopant ions in the P-type semiconductor field limiting ring, and the dopant ions in the P-type semiconductor buried layer are the same, and wherein the concentration of the dopant ions in the P-type semiconductor doped region is less than the concentration of the dopant ions in the P-type semiconductor field limiting ring and greater than the concentration of the dopant ions in the P-type semiconductor buried layer.

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