CN215068129U - Master-slave equipment power supply circuit and master-slave equipment starting system - Google Patents

Abstract

The application provides a master-slave equipment power supply circuit, which comprises a first buffer circuit, a data interface and a second buffer circuit, wherein the first buffer circuit receives an electrifying signal provided by power supply equipment and buffers the electrifying signal to obtain a first electric signal, the first electric signal is used for providing first starting current for a host, the first buffer circuit is electrically connected with the second buffer circuit through the data interface, the data interface receives the first electric signal and transmits the first electric signal to the second buffer circuit, and the second buffer circuit provides second starting current for a slave according to the first electric signal. The second buffer circuit receives the first electric signal through the data interface, and the host can control whether the data interface sends the first electric signal or not, so that the slave is controlled to be turned on or off, and the power supply of the slave side is turned off by the host side. The master-slave equipment power supply circuit provided by the application enables power-on signals of the master machine and the slave machine to be more moderate. The application also provides a master-slave equipment starting system.

Description

Master-slave equipment power supply circuit and master-slave equipment starting system

Technical Field

The application relates to the technical field of power supply, in particular to a master-slave device power supply circuit and a master-slave device starting system.

Background

Many devices in life are divided into a master machine and a slave machine, and the master machine and the slave machine need to be powered and need to be communicated and interacted with each other. In the prior art, the master and the slave are usually supplied with power separately and then connected through a communication cable to realize communication interaction, so that the power supply of the slave cannot be turned on or off from the master side.

SUMMERY OF THE UTILITY MODEL

The application discloses master-slave equipment power supply circuit can solve the technical problem that the power supply of the slave machine side cannot be turned on or turned off by the master machine side.

In a first aspect, the present application provides a master-slave device power supply circuit, where the master-slave device power supply circuit includes a first buffer circuit, a data interface, and a second buffer circuit, the first buffer circuit receives a power-on signal provided by a power supply device and buffers the power-on signal to obtain a first electrical signal, the first electrical signal is used to provide a first starting current for a host, the first buffer circuit is electrically connected to the second buffer circuit through the data interface, the data interface receives the first electrical signal and transmits the first electrical signal to the second buffer circuit, and the second buffer circuit provides a second starting current for a slave according to the first electrical signal.

The second buffer circuit receives the first electric signal through the data interface, and the host can control whether the data interface sends the first electric signal or not, so that the slave is controlled to be turned on or off, and the power supply of the slave side is turned off by the host side. Meanwhile, compared with the prior art, the power supply circuit for the master and slave devices reduces cables for supplying power to the slave devices, so that the circuit is simplified, the power-on signals of the master device and the slave devices are more moderate by the aid of the first buffer circuit and the second buffer circuit, and the master device and the slave devices are prevented from being damaged by overlarge power-on signals.

Further, the first buffer circuit includes a first sub-buffer circuit and a second sub-buffer circuit, the first sub-buffer circuit receives a power-on signal and generates the first electrical signal, the second sub-buffer circuit is electrically connected to the first sub-buffer circuit, and the second sub-buffer circuit is configured to buffer the first electrical signal again to obtain the first start current.

Further, the master-slave device power supply circuit further comprises a first switch circuit, and the first switch circuit is used for controlling the opening or closing of the first sub-buffer circuit and the second sub-buffer circuit.

Furthermore, the first sub-buffer circuit includes a first capacitor and a first field effect transistor, two ends of the first capacitor are connected in parallel to the gate and the source of the first field effect transistor, the source of the first field effect transistor is used for receiving the power-on signal, the gate of the first field effect transistor is electrically connected to the first switch circuit, the second sub-buffer circuit includes a second capacitor and a second field effect transistor, two ends of the second capacitor are connected in parallel to the gate and the source of the second field effect transistor, the source of the second field effect transistor is used for receiving the first electrical signal, and the gate of the second field effect transistor is electrically connected to the first switch circuit.

Further, the second buffer circuit includes a third sub-buffer circuit and a fourth sub-buffer circuit, and the fourth sub-buffer circuit receives the first electrical signal and is configured to obtain the second start current according to the first electrical signal.

Further, the third sub-buffer circuit receives a power-on signal provided by a power supply device and buffers the power-on signal to obtain a second electrical signal, and the fourth sub-buffer circuit is electrically connected to the third sub-buffer circuit and is configured to buffer again according to the second electrical signal to obtain the second starting current.

Further, the master-slave device power supply circuit further comprises a second switch circuit, and the second switch circuit is used for controlling the third sub-buffer circuit and the fourth sub-buffer circuit to be turned on or turned off.

Further, the second switch circuit receives a control signal sent by a host through the data interface, and the second switch circuit controls the fourth sub-buffer circuit to be turned on or turned off according to the control signal.

Furthermore, the third sub-buffer circuit includes a third capacitor and a third field effect transistor, two ends of the third capacitor are connected in parallel to the gate and the source of the third field effect transistor, the source of the third field effect transistor is used for receiving the power-on signal, the gate of the third field effect transistor is electrically connected to the second switch circuit, the fourth sub-buffer circuit includes a fourth capacitor and a fourth field effect transistor, two ends of the fourth capacitor are connected in parallel to the gate and the source of the fourth field effect transistor, the source of the fourth field effect transistor is used for receiving the first electrical signal or the second electrical signal, and the gate of the fourth field effect transistor is electrically connected to the second switch circuit.

In a second aspect, the present application further provides a master-slave device starting system, where the master-slave device starting system includes a master, a slave, and the master-slave device power supply circuit according to the first aspect, where the master-slave device power supply circuit is configured to provide a first starting current for the master, and the master can control whether the slave is started through the master-slave device power supply circuit.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for a person skilled in the art to obtain other drawings based on the drawings without any inventive exercise.

Fig. 1 is a schematic diagram of a power supply circuit framework of a master-slave device according to a first embodiment of the present application.

Fig. 2 is a schematic diagram of a power supply circuit framework of a master device and a slave device according to an embodiment of the present application.

Fig. 3 is a partial circuit diagram of a first buffer circuit according to an embodiment of the present disclosure.

Fig. 4 is a schematic diagram of a data interface circuit according to an embodiment of the present application.

Fig. 5 is a schematic diagram of a power supply circuit framework of a master device and a slave device according to an embodiment of the present application.

Fig. 6 is a partial circuit diagram of a second buffer circuit according to an embodiment of the present disclosure.

Fig. 7 is a schematic diagram of a master-slave device start-up system framework according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.

Please refer to fig. 1, wherein fig. 1 is a schematic diagram of a power supply circuit framework of a master device and a slave device according to a first embodiment of the present application. The master-slave device power supply circuit 1 comprises a first buffer circuit 11, a data interface 12 and a second buffer circuit 13. The first buffer circuit 11 receives a power-on signal provided by a power supply device and buffers the power-on signal to obtain a first electrical signal, the first electrical signal is used for providing a first starting current for a host, the first buffer circuit 11 is electrically connected with the second buffer circuit 13 through the data interface 12, the data interface 12 receives the first electrical signal and transmits the first electrical signal to the second buffer circuit 13, and the second buffer circuit 13 provides a second starting current for a slave according to the first electrical signal.

It should be noted that, in general, as shown in fig. 1, the master-slave device power supply circuit 1 further includes an adapter, and a power supply device provides a power-on signal to the master-slave device power supply circuit 1 through the adapter. In other possible embodiments, the master-slave device power supply circuit 1 may also obtain the power-on signal in other manners, which is not limited in this application.

Specifically, the first buffer circuit 11 buffers the power-on signal, and the second buffer circuit 13 buffers the first electrical signal, so as to avoid a large current impact caused by an excessively large current value transmitted to the host or the slave in a short time, and damage to the host and the slave.

It can be understood that, in this embodiment, the host can turn off the second buffer circuit 13 through the data interface 12, thereby realizing the power supply of the slave side from the host side. Meanwhile, compared with the prior art, the master-slave device power supply circuit 1 provided by the application reduces cables for supplying power to the slave, so that the circuit is simplified, the power-on signals of the master and the slave are more moderate by the first buffer circuit 11 and the second buffer circuit 13, and the damage of the master and the slave by the excessive power-on signals is avoided.

In a possible embodiment, please refer to fig. 2, and fig. 2 is a schematic diagram of a power supply circuit framework of a master device and a slave device according to an embodiment of the present disclosure. The first buffer circuit 11 includes a first sub-buffer circuit 111 and a second sub-buffer circuit 112, the first sub-buffer circuit 111 receives a power-on signal and generates the first electrical signal, the second sub-buffer circuit 112 is electrically connected to the first sub-buffer circuit 111, and the second sub-buffer circuit 112 is configured to buffer the first electrical signal again to obtain the first start current.

It should be noted that the master may not be turned on simultaneously with the slave, that is, the power supply device provides different power-on signals when turning on the master or turning on the master and the slave simultaneously, and the power-on signal when turning on the master and the slave simultaneously should be greater than the power-on signal when only turning on the master. In order to avoid that the host is damaged by an excessive power-on signal when the host and the slave are simultaneously turned on, the second sub-buffer circuit 112 buffers the first electrical signal again and transmits the buffered first electrical signal to the host, so that the current transmitted to the host can reach a higher current value in a relatively longer time, and the purpose of protecting the host is achieved.

In a possible embodiment, referring to fig. 2 again, the master-slave device power supply circuit 1 further includes a first switch circuit 14, and the first switch circuit 14 is used for controlling the first sub-buffer circuit 111 and the second sub-buffer circuit 112 to be turned on or off.

Specifically, the first switch circuit 14 can control the first sub-buffer circuit 111 and the second sub-buffer circuit 112 to be turned on or off, so as to turn on or off the host. For example, when the host sends a turn-on request to the first switch circuit 14, the first switch circuit 14 controls the first sub-buffer circuit 111 and the second sub-buffer circuit 112 to turn on, so that the first electrical signal can be transmitted to the host; when the host sends a turn-off request to the first switch circuit 14, the first switch circuit 14 controls the first sub-buffer circuit 111 and the second sub-buffer circuit 112 to turn off, so that the first electrical signal stops being transmitted to the host.

In a possible embodiment, please refer to fig. 3, in which fig. 3 is a schematic diagram of a partial circuit of a first buffer circuit according to an embodiment of the present disclosure. The first sub-buffer circuit 111 includes a first capacitor C11 and a first fet Q11, two ends of the first capacitor C11 are connected in parallel to a gate g and a source s of the first fet Q11, the source s of the first fet Q11 is used for receiving the power-on signal, the gate g of the first fet Q11 is electrically connected to the first switch circuit 14, the second sub-buffer circuit 112 includes a second capacitor C12 and a second fet Q12, two ends of the second capacitor C12 are connected in parallel to the gate g and the source s of the second fet Q12, the source s of the second fet Q12 is used for receiving the first electrical signal, and the gate g of the second fet Q12 is electrically connected to the first switch circuit 14.

Specifically, in this embodiment, as shown in fig. 3, the first switch circuit 14 is two single-pole double-throw switches, and in other possible embodiments, the first switch circuit 14 may also be in other forms, which is not limited in this application. When the first switch circuit 14 controls the first sub-buffer circuit 111 to be turned off, the 2 terminal and the 3 terminal of the first switch circuit 14 are connected, the voltage value between the gate g and the source s of the first field effect transistor Q11 is almost zero, and the first field effect transistor Q11 does not reach the turn-on voltage, so that the turn-off of the first sub-buffer circuit 111 is controlled; when the first switch circuit 14 controls the first sub-buffer circuit 111 to be turned on, the terminal 2 of the first switch circuit 14 is connected to the terminal 1, the voltage value of the source s of the first fet Q11 is greater than the voltage value of the gate g of the first fet Q11, and when the voltage value between the source s and the gate g of the first fet Q11 is greater than the turn-on voltage, the first fet Q11 is turned on, thereby turning on the first sub-buffer circuit 111. It can be understood that, since the capacitor has a function of storing charges, the first capacitor C11 is connected in parallel to the gate g and the source s of the first fet Q11, so that the voltage values of the gate g and the source s of the first fet Q11 rise slowly, and a buffering effect is achieved.

Similarly, when the first switch circuit 14 controls the second sub-buffer circuit 112 to be turned off, the terminal 5 of the first switch circuit 14 is connected to the terminal 6, the voltage value between the gate g and the source s of the second fet Q12 is almost zero, and the voltage value of the second fet Q12 does not reach the turn-on voltage, so as to control the second sub-buffer circuit 112 to be turned off; when the second switch circuit 15 controls the second sub-buffer circuit 112 to be turned on, the terminal 5 of the second switch circuit 15 is connected to the terminal 4, the voltage value of the source s of the second fet Q12 is greater than the voltage value of the gate g of the second fet Q12, and when the voltage value between the source s and the gate g of the second fet Q12 is greater than the turn-on voltage, the second fet Q12 is turned on, thereby turning on the second sub-buffer circuit 112. The second capacitor C12 is connected in parallel to the gate g and the source s of the second fet Q12, so that the voltage value of the gate g and the source s of the second fet Q12 rises slowly, thereby achieving a buffering effect.

Specifically, as shown in fig. 3, the master-slave device power supply circuit 1 further includes a plurality of diodes, resistors and other electronic components, and in this embodiment, the diodes play a role in circuit protection, for example, the diode D12 protects a power-on signal provided by the power supply device from flowing in a reverse direction, the diode D11 is a Transient Voltage regulator (TVS) to protect the power supply device from surge, the diode D13, the diode D14, and the diode D15 are electrostatic discharge (ESD) protection, and the capacitor C13 and the resistor R15 are used for fast discharging after the host power supply is turned off. It is understood that the type of the diode and the resistance of the resistor may vary according to practical situations, and the present application is not limited thereto.

It should be noted that, in a normal case, the power-on signal is connected to the master-slave device power supply circuit 1 through a power adapter, and the power adapter is omitted in fig. 3 for illustration. In a possible embodiment, please refer to fig. 4, in which fig. 4 is a schematic diagram of a data interface circuit according to an embodiment of the present disclosure. Specifically, the connector J2 is a connection interface for power and data between the master and the slave, and is used for connecting the master and the slave. Pins 1 and 4 in the connector J2 are power and ground, respectively, and pins 2 and 3 are for data transmission. The diodes D6 and D7 are ESD protection tubes, and are used for ESD protection of the connection interface of the host computer of the connector J2 and the slave computer power supply and data.

In a possible embodiment, please refer to fig. 5, and fig. 5 is a schematic diagram of a power supply circuit framework of a master device and a slave device according to an embodiment of the present disclosure. The second buffer circuit 13 includes a third sub-buffer circuit 131 and a fourth sub-buffer circuit 132, and the fourth sub-buffer circuit 132 receives the first electrical signal and is configured to obtain the second start current according to the first electrical signal.

Specifically, as shown in fig. 5, the fourth sub-buffer circuit 132 is connected to a node between the first sub-buffer circuit 111 and the second sub-buffer circuit 112, so that when the slave is started, a large power-up signal provided by the power supply device can be buffered again by the second sub-buffer circuit 112 and then transmitted to the host, or buffered again by the fourth sub-buffer circuit 132 and then transmitted to the slave, thereby preventing the host or the slave from being damaged by the excessive power-up signal.

In a possible embodiment, referring to fig. 5 again, the third sub-buffer circuit 131 in fig. 5 receives a power-up signal provided by a power supply device and buffers the power-up signal to obtain a second electrical signal, the fourth sub-buffer circuit 132 is electrically connected to the third sub-buffer circuit 131, and the fourth sub-buffer circuit 132 is configured to buffer again according to the second electrical signal to obtain a second start current.

Specifically, in this embodiment, the master-slave device power supply circuit 1 provided by the present application may not only provide the second starting current for the slave device through the first electrical signal at the master device side, but also provide the second starting current for the slave device through the second electrical signal obtained after buffering the power-on signal provided by the power device at the slave device side.

In fig. 5, referring to fig. 5 again, the master-slave device power supply circuit 1 further includes a second switch circuit 15, and the second switch circuit 15 is used for controlling the third sub-buffer circuit 131 and the fourth sub-buffer circuit 132 to be turned on or off.

Specifically, the second switch circuit 15 can control the third sub-buffer circuit 131 and the fourth sub-buffer circuit 132 to be turned on or off, so as to turn on or off the slave. For example, when the master sends a slave turn-on request to the second switch circuit 15, the second switch circuit 15 controls the third sub-buffer circuit 131 and the fourth sub-buffer circuit 132 to turn on, so that the first electrical signal or the second electrical signal can be transmitted to the slave; when the master sends a slave shutdown request to the second switch circuit 15, the second switch circuit 15 controls the third sub-buffer circuit 131 and the fourth sub-buffer circuit 132 to be turned off, so that the first electrical signal or the second electrical signal stops being transmitted to the master.

In a possible embodiment, the second switch circuit 15 receives a control signal sent by the host through the data interface 12, and the second switch circuit 15 controls the fourth sub-buffer circuit 132 to be turned on or off according to the control signal.

Specifically, the data interface 12 has a function of data interaction between a master side and a slave side, and the master sends a control signal to the second switch circuit 15 through the data interface 12, or manually controls the second switch circuit 15 to be turned off, so as to control the slave side to be turned on or turned off.

In a possible embodiment, please refer to fig. 6 together, and fig. 6 is a partial circuit diagram of a second buffer circuit according to an embodiment of the present disclosure. The third sub-buffer circuit 131 includes a third capacitor C21 and a third fet Q21, two ends of the third capacitor C21 are connected in parallel to the gate g and the source s of the third fet Q21, the source s of the third fet Q21 is used to receive an power-on signal, the gate g of the third fet Q21 is electrically connected to the second switch circuit 15, the fourth sub-buffer circuit 132 includes a fourth capacitor C22 and a fourth fet Q22, two ends of the fourth capacitor C22 are connected in parallel to the gate g and the source s of the fourth fet Q22, the source s of the fourth fet Q22 is used to receive the first electrical signal or the second electrical signal, and the gate g of the fourth fet Q22 is electrically connected to the second switch circuit 15.

Specifically, the working principle of the third capacitor C21, the third fet Q21, the fourth capacitor C22 and the fourth fet Q22 is referred to the above description, and is not repeated herein. In this embodiment, as shown in fig. 6, the second switch circuit 15 is two single-pole double-throw switches, and in other possible embodiments, the second switch circuit 15 may also be in other forms, which is not limited in this application. When the second switch circuit 15 controls the third fet Q21 to turn off, the terminal 8 of the second switch circuit 15 is connected to the terminal 9; when the second switch circuit 15 controls the third fet Q21 to turn on, the terminal 8 of the second switch circuit 15 is connected to the terminal 7. Similarly, when the second switch circuit 15 controls the fourth fet Q22 to turn off, the terminal 11 of the second switch circuit 15 is connected to the terminal 12; when the second switch circuit 15 controls the fourth fet Q22 to turn on, the terminal 11 of the second switch circuit 15 is connected to the terminal 10.

Specifically, as shown in fig. 6, the master-slave device power supply circuit 1 further includes a plurality of diodes, resistors and other electronic components, and in this embodiment, the diodes play a role in circuit protection, for example, the diode D22 protects a power-on signal provided by the power supply device from flowing in a reverse direction, the diode D21 is a TVS diode to protect the power supply device from a surge, the diode D23, the diode D24, and the diode D25 are ESD protection, and the capacitor C23 and the resistor R25 are used for discharging quickly after the slave power supply is turned off. It is understood that the type of the diode and the resistance of the resistor may vary according to practical situations, and the present application is not limited thereto.

Fig. 7 is a schematic diagram of a master-slave device start system 2 according to an embodiment of the present application, where fig. 7 is a schematic diagram of a master-slave device start system framework. The master-slave device starting system 2 comprises a master 21, a slave 22 and the master-slave device power supply circuit 1 as described above, the master-slave device power supply circuit 1 is used for providing a first starting current for the master 21, and the master 21 can control whether the slave 22 is started or not through the master-slave device power supply circuit 1. Specifically, please refer to the above description for the master 21, the slave 22 and the master-slave device power supply circuit 1, which is not described herein again.

It is understood that the master-slave device start-up system 2 provided by the present application can turn off the power supply of the slave 22 from the master 21 side. Meanwhile, compared with the prior art, the master-slave device starting system 2 provided by the application only needs one power cable and one data cable at least, so that the circuit is simplified, and the first buffer circuit 11 and the second buffer circuit 13 make the power-on signals of the master 21 and the slave 22 more moderate, so that the master 21 and the slave 22 are prevented from being damaged by excessive power-on signals.

The principle and the implementation of the present application are explained herein by applying specific examples, and the above description of the embodiments is only used to help understand the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. The master-slave device power supply circuit is characterized by comprising a first buffer circuit, a data interface and a second buffer circuit, wherein the first buffer circuit receives a power-on signal provided by power supply equipment and buffers the power-on signal to obtain a first electric signal, the first electric signal is used for providing a first starting current for a host, the first buffer circuit is electrically connected with the second buffer circuit through the data interface, the data interface receives the first electric signal and transmits the first electric signal to the second buffer circuit, and the second buffer circuit provides a second starting current for a slave according to the first electric signal.

2. The master-slave device power supply circuit of claim 1, wherein the first buffer circuit comprises a first sub-buffer circuit and a second sub-buffer circuit, the first sub-buffer circuit receives a power-up signal and generates the first electrical signal, the second sub-buffer circuit is electrically connected to the first sub-buffer circuit, and the second sub-buffer circuit is configured to buffer the first electrical signal again to obtain the first start-up current.

3. The master-slave device power supply circuit of claim 2, further comprising a first switch circuit for controlling the first sub-buffer circuit and the second sub-buffer circuit to be turned on or off.

4. The master-slave device power supply circuit according to claim 3, wherein the first sub-buffer circuit comprises a first capacitor and a first field effect transistor, two ends of the first capacitor are connected in parallel to a gate and a source of the first field effect transistor, the source of the first field effect transistor is used for receiving the power-on signal, the gate of the first field effect transistor is electrically connected to the first switch circuit, the second sub-buffer circuit comprises a second capacitor and a second field effect transistor, two ends of the second capacitor are connected in parallel to the gate and the source of the second field effect transistor, the source of the second field effect transistor is used for receiving the first electrical signal, and the gate of the second field effect transistor is electrically connected to the first switch circuit.

5. The master-slave device power supply circuit according to any one of claims 1 to 4, wherein the second buffer circuit comprises a third sub-buffer circuit and a fourth sub-buffer circuit, and the fourth sub-buffer circuit receives the first electric signal and is configured to obtain the second starting current according to the first electric signal.

6. The master-slave device power supply circuit of claim 5, wherein the third sub-buffer circuit receives a power-on signal provided by a power supply device and buffers the power-on signal to obtain a second electrical signal, and the fourth sub-buffer circuit is electrically connected to the third sub-buffer circuit and is configured to buffer again according to the second electrical signal to obtain the second start-up current.

7. The master-slave device power supply circuit of claim 6, further comprising a second switch circuit for controlling the third sub-buffer circuit and the fourth sub-buffer circuit to be turned on or off.

8. The master-slave device power supply circuit of claim 7, wherein the second switch circuit receives a control signal sent by a host through the data interface, and the second switch circuit controls the fourth sub-buffer circuit to be turned on or off according to the control signal.

9. The master-slave device power supply circuit according to claim 7, wherein the third sub-buffer circuit includes a third capacitor and a third fet, two ends of the third capacitor are connected in parallel to a gate and a source of the third fet, the source of the third fet is used for receiving the power-on signal, the gate of the third fet is electrically connected to the second switch circuit, the fourth sub-buffer circuit includes a fourth capacitor and a fourth fet, two ends of the fourth capacitor are connected in parallel to the gate and the source of the fourth fet, the source of the fourth fet is used for receiving the first electrical signal or the second electrical signal, and the gate of the fourth fet is electrically connected to the second switch circuit.

10. A master-slave device start-up system, characterized in that the master-slave device start-up system comprises a master, a slave and a master-slave device power supply circuit according to any one of claims 1 to 9, the master-slave device power supply circuit is used for providing a first start-up current for the master, and the master can control whether the slave is started up or not through the master-slave device power supply circuit.

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