CN215067795U

CN215067795U - Frame type energy management type intelligent controller

Info

Publication number: CN215067795U
Application number: CN202120997265.9U
Authority: CN
Inventors: 程雪婷; 薛子腾
Original assignee: Hangzhou Zhijiang Switchgear Stock Co Ltd
Current assignee: Hangzhou Zhijiang Switchgear Stock Co Ltd
Priority date: 2021-05-11
Filing date: 2021-05-11
Publication date: 2021-12-07
Anticipated expiration: 2031-05-11

Abstract

The utility model discloses a frame-type energy management type intelligent control ware, including sampling circuit, reference circuit, digital signal processor chip U1, electric energy measurement chip U2, communication interface chip U7, keyboard interface chip U10, LCD display chip U6, regional chain chip U5, control interface chip U4, constant voltage power supply chip U3, analog power module M1, switching power module M2 and gateway chip U8, sampling circuit include current acquisition circuit, voltage acquisition circuit and low pass filter amplifier circuit, current acquisition circuit's an output and electric energy measurement chip U2's input electric connection, current acquisition circuit's No. two outputs and voltage acquisition circuit's output respectively with low pass filter amplifier circuit's input electric connection. The utility model has the characteristics of have that the cover is wide, connect many, speed is fast, with low costs, low power dissipation and framework excellence.

Description

Frame type energy management type intelligent controller

Technical Field

The utility model relates to a technical field of low pressure frame circuit breaker, more specifically say, relate to a frame-type energy management type intelligent control ware.

Background

With the rapid development of the industry, agriculture and modern national defense industry in China, higher requirements are put forward on the quantity and quality of electric power equipment, and the intelligent electric appliances are particularly applied to various intelligent electric appliances embedded with single-chip computers and digital signal processing chips (DSP) such as an intelligent frame circuit breaker (ACB) with nonlinear load, an intelligent Molded Case Circuit Breaker (MCCB), an intelligent dual-power automatic switching device (ATS), an intelligent reactive power compensation device, an intelligent motor protector, a soft starter, a variable frequency speed regulation device, an intelligent digital instrument series and the like, the sensor signal is millivolt to volt, but reliable operation under various nonlinear, impact and harmonic and unbalanced conditions is required, when the intelligent electric appliance runs under the severe condition, how to eliminate various electromagnetic interferences and improve the reliability, the usability and the maintainability of the intelligent electric appliance are important tasks which cannot be disassembled by designers of the intelligent electric appliance. The presence of harmonics produces a large deviation from conventional detection protection. Therefore, the energy management type controller becomes necessary, which is beneficial to the understanding and analysis of the power grid quality, the improvement of the power grid quality by adopting necessary measures, the improvement of the protection detection precision and the guarantee of the property safety of people.

The energy management type controller utilizes a high-speed DSP chip to process current signals, voltage signals and various auxiliary signals of the electric energy of the access circuit breaker in real time, realizes four-section protection functions of long overload, short delay, instantaneous, earth fault and the like, and simultaneously has the functions of active power, reactive power, power factor, frequency, electric energy, real-time clock, harmonic measurement, wireless communication, fault waveform recording, tripping frequency record inquiry, over-frequency and under-frequency protection, reverse power protection and the like. The system can realize multiple functions of local fault monitoring and protection, remote centralized monitoring and management, energy efficiency management and data analysis, fault reason analysis and the like. Meanwhile, the special electric energy chip is used for improving the measurement precision.

SUMMERY OF THE UTILITY MODEL

The utility model discloses an overcome the above-mentioned technical problem that exists among the prior art, now provide a frame-type energy management type intelligent control ware that has advantages such as measurement accuracy height and stability are strong.

The utility model discloses a frame-type energy management type intelligent controller, including sampling circuit 1, reference circuit 2, digital signal processor chip U1, electric energy measurement chip U2, communication interface chip U7, keyboard interface chip U10, LCD display chip U6, regional chain chip U5, control interface chip U4, constant voltage power supply chip U3, analog power module M1, switching power module M2 and gateway chip U8, sampling circuit 1 include current acquisition circuit 3, voltage acquisition circuit 4 and low pass filter amplifier circuit 5, current acquisition circuit 3's the output and electric energy measurement chip U2's input electric connection, current acquisition circuit 3's the output of two numbers and voltage acquisition circuit 4's the output respectively with low pass filter amplifier circuit 5's input electric connection, electric energy measurement chip U2's the output and digital signal processor chip U1's the input electric connection, the output end of the low-pass filter amplifying circuit 5 is electrically connected with the second input end of a digital signal processor chip U1, the output end of the reference circuit 2 is electrically connected with the third input end of a digital signal processor chip U1, the output end of the analog power supply module M1 is electrically connected with the first input end of a stabilized voltage power supply chip U3, the output end of the switch power supply module M2 is electrically connected with the second input end of a stabilized voltage power supply chip U3, the output end of the stabilized voltage power supply chip U3 is electrically connected with the fourth input end of a digital signal processor chip U1, the first output end of the digital signal processor chip U1 is electrically connected with the input end of a control interface chip U4, the second output end of the digital signal processor chip U1 is electrically connected with the input end of a communication interface chip U7, and the output end of the communication interface chip U7 is electrically connected with the input end of a gateway chip U8, the third output end of the digital signal processor chip U1 is electrically connected with the input end of the keyboard interface chip U10, the fourth output end of the digital signal processor chip U1 is electrically connected with the input end of the LCD display chip U6, and the fifth output end of the digital signal processor chip U1 is electrically connected with the input end of the region interlocking chip U5.

The utility model takes a high-speed digital signal processor as a core, and simultaneously adopts a special electric energy chip ATT7022EU with 19 AD, and the special chip samples and processes the accessed voltage and current signals and simultaneously obtains 0.5-level precision current and voltage signals through calibration; 1-level precision active and reactive power signals; the precision meets the precision requirement of a GB/T22264.1 instrument. Meanwhile, the quick processing capacity of the singlechip is utilized to carry out various protections such as long, short, instant and grounding; the method has the advantages that parameter setting, historical fault parameter query, fault waveform capture query, test tripping, operation parameters, active power, reactive power, power factors, distortion coefficients and harmonic rod head real-time display are realized through a friendly man-machine interaction interface displayed by a keyboard and an LCD, and the functions of fault tripping parameter display, field bus networking, multi-stage regional interlocking, neutral pole protection, load monitoring, MCR and the like are realized.

Preferably, the current collecting circuit 3 includes a current transformer CT, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a diode D1 and a diode D2, a pin 1 of the current transformer CT is electrically connected to one end of the resistor R1, the other end of the resistor R1 is electrically connected to one end of the capacitor C1, a cathode of the diode D1, an anode of the diode D2 and a pin 1 of the electric energy metering chip U2, a pin 2 of the current transformer CT is electrically connected to one end of the resistor R2 and grounded, the other end of the resistor R2 is electrically connected to one end of the capacitor C2, an anode of the diode D1, a cathode of the diode D2 and a pin 2 of the electric energy metering chip U2, and the other end of the capacitor C1 is electrically connected to the other end of the capacitor C2 and grounded.

Preferably, the voltage acquisition circuit 4 includes a voltage transformer PT, a resistor R8, a resistor R9, a resistor R10, a capacitor C9, and a capacitor C10, wherein a pin 1 of the voltage transformer PT is electrically connected to one end of the resistor R8 and one end of the resistor R9, the other end of the resistor R9 is electrically connected to one end of the capacitor C9 and a pin 3 of the power metering chip U2, a pin 2 of the voltage transformer PT is electrically connected to the other end of the resistor R8 and one end of the resistor R10 and is grounded, the other end of the resistor R10 is electrically connected to one end of the capacitor C10 and a pin 4 of the power metering chip U2, and the other end of the capacitor C9 is electrically connected to the other end of the capacitor C10 and is grounded.

Preferably, the low-pass filter amplifier circuit 5 includes an operational amplifier chip N2C, an operational amplifier chip N2D, a resistor R28, a resistor R29, a resistor R30, a resistor R31, a resistor R32, a resistor R33, a resistor R34, a resistor R35, a resistor R36, a resistor R37, a resistor R38, a resistor R39, a resistor R40, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C17 and a diode D17, wherein one end of the resistor R17 is electrically connected to one end of the resistor R17 and one end of the capacitor C17, the other end of the capacitor C17 is grounded, the other end of the resistor R17 is electrically connected to one end of the resistor R17, the other end of the resistor R17 is electrically connected to one end of the capacitor C17, and the other end of the capacitor C17 are electrically connected to the capacitor C363, the other end of the capacitor C17, the resistor R17 is electrically connected to the capacitor C17, and the other end of the capacitor C17 is electrically connected to the capacitor C17, the other end of the resistor R31 is electrically connected with the other end of the capacitor C14 and the 1 pin of the operational amplifier chip N2C, the 2 pin of the operational amplifier chip N2C is grounded, the other end of the capacitor C16 is electrically connected with one end of the resistor R32, one end of the resistor R37 and one end of the resistor R40, the other end of the resistor R37 is connected with +3.5V, the other end of the resistor R40 is grounded, the other end of the resistor R32 is electrically connected with the cathode of the diode D3, one end of the capacitor C18 and the 5 pin of the digital signal processor chip U1, the anode of the diode D3 and the other end of the capacitor C18 are grounded, the other end of the resistor R33 is electrically connected with one end of the resistor R34, the other end of the resistor R34 is electrically connected with one end of the capacitor C13, one end of the resistor R35 and one end of the resistor R36, and the other end of the capacitor C13 is grounded, the other end of the resistor R35 is respectively electrically connected with one end of a capacitor C15, a 3 pin of an operational amplifier chip N2D and one end of a capacitor C17, the other end of the resistor R36 is respectively electrically connected with the other end of a capacitor C15 and a 1 pin of an operational amplifier chip N2D, a 2 pin of the operational amplifier chip N2D is grounded, the other end of the capacitor C17 is respectively electrically connected with one end of a resistor R38, one end of the resistor R39 and a 6 pin of a digital signal processor chip U1, the other end of the resistor R39 is connected with +3.5V, and the other end of the resistor R38 is grounded.

Preferably, the reference circuit 2 includes a resistor R41, a resistor R42, a resistor R43, a polar capacitor C19, a capacitor C20 and a thyristor N1, wherein one end of the resistor R41 is connected to +5V, the other end of the resistor R41 is electrically connected to one end of the resistor R42, the pin 1 of the thyristor N1, the anode of the polar capacitor C19, one end of the capacitor C20 and the pin 7 of the dsp chip U1, the other end of the resistor R42 is electrically connected to one end of the resistor R43 and the pin 2 of the thyristor N1, and the other end of the resistor R43 is electrically connected to the pin 3 of the thyristor N1, the cathode of the polar capacitor C19 and the other end of the capacitor C20 and is grounded.

Preferably, the 5 pins of the electric energy metering chip U2 are electrically connected with the 4 pins of the digital signal processor chip U1, the 6 pins of the electric energy metering chip U2 are electrically connected with the 3 pins of the digital signal processor chip U1, the 7 pins of the electric energy metering chip U2 are electrically connected with the 2 pins of the digital signal processor chip U1, and the 8 pins of the electric energy metering chip U2 are electrically connected with the 1 pin of the digital signal processor chip U1.

Preferably, the 8 pins of the digital signal processor chip U1 are electrically connected to the 1 pin of the regulated power supply chip U3, the 2 pins of the regulated power supply chip U3 are electrically connected to the input terminal of the analog power supply module M1, the 3 pins of the regulated power supply chip U3 are electrically connected to the input terminal of the switching power supply module M2, the 9 pins of the digital signal processor chip U1 are electrically connected to the 1 pin of the control interface chip U4, the 10 pins of the digital signal processor chip U1 are electrically connected to the 2 pins of the control interface chip U4, the 11 pins of the digital signal processor chip U1 are electrically connected to the 3 pins of the control interface chip U4, the 12 pins of the digital signal processor chip U1 are electrically connected to the 1 pin of the region-interlocking chip U5, and the 13 pins of the digital signal processor chip U1 are electrically connected to the 2 pins of the region-interlocking chip U5, the 14 pins of the digital signal processor chip U1 are electrically connected with the 3 pins of the area interlocking chip U5, the 15 pins of the digital signal processor chip U1 are electrically connected with the 4 pins of the area interlocking chip U5, the 16 pins of the digital signal processor chip U1 are electrically connected with the 1 pin of the LCD display chip U6, the 17 pins of the digital signal processor chip U1 are electrically connected with the 2 pins of the LCD display chip U6, the 18 pins of the digital signal processor chip U1 are electrically connected with the 3 pins of the LCD display chip U6, the 19 pins of the digital signal processor chip U1 are electrically connected with the 4 pins of the LCD display chip U6, the 20 pins of the digital signal processor chip U1 are electrically connected with the 1 pin of the communication interface chip U7, the 21 pins of the digital signal processor chip U1 are electrically connected with the 2 pins of the communication interface chip U7, the 22 pins of the digital signal processor chip U1 are electrically connected with the 3 pins of the communication interface chip U7, the 6 pins of the communication interface chip U7 are electrically connected with the 1 pin of the gateway chip U8, the 5 pins of the communication interface chip U7 are electrically connected with the 2 pins of the gateway chip U8, the 4 pins of the communication interface chip U7 are electrically connected with the 3 pins of the gateway chip U8, the 23 pin of the digital signal processor chip U1 is electrically connected with the 1 pin of the keyboard interface chip U10, the 24 pins of the digital signal processor chip U1 are electrically connected with the 2 pins of the keyboard interface chip U10, the 25 pins of the digital signal processor chip U1 are electrically connected with the 3 pins of the keyboard interface chip U10, the 26 pins of the digital signal processor chip U1 are electrically connected with the 4 pins of the keyboard interface chip U10.

The utility model discloses a digital signal processor chip U1 adopts Microchip company's high performance Digital Signal Processor (DSP) Dsp30f6014, and electric energy measurement chip U2 adopts ATT 7022.

The utility model discloses following beneficial effect has: the system has the advantages of wide coverage, more connections, high speed, low cost, low power consumption and excellent architecture.

Drawings

Fig. 1 is a block diagram of the present invention.

Fig. 2 is a schematic diagram of the present invention.

Fig. 3 is a schematic diagram of the current collecting circuit of the present invention.

Fig. 4 is a schematic diagram of the voltage acquisition circuit of the present invention.

Fig. 5 is a schematic diagram of the low-pass filtering amplifying circuit of the present invention.

The circuit comprises a sampling circuit 1, a reference circuit 2, a current acquisition circuit 3, a voltage acquisition circuit 4 and a low-pass filtering amplification circuit 5.

Detailed Description

The technical solution of the present invention is further specifically described below by way of examples and with reference to the accompanying drawings.

Example (b): referring to fig. 1, fig. 2, fig. 3, fig. 4 and fig. 5 for further explanation, the frame-type energy management intelligent controller of this embodiment includes a sampling circuit 1, a reference circuit 2, a digital signal processor chip U1, an electric energy metering chip U2, a communication interface chip U7, a keyboard interface chip U10, an LCD display chip U6, a region interlock chip U5, a control interface chip U4, a regulated power supply chip U3, an analog power supply module M1, a switching power supply module M2 and a gateway chip U8, wherein the sampling circuit 1 includes a current collecting circuit 3, a voltage collecting circuit 4 and a low-pass filter amplifier circuit 5, a first output terminal of the current collecting circuit 3 is electrically connected to an input terminal of the electric energy metering chip U2, a second output terminal of the current collecting circuit 3 and an output terminal of the voltage collecting circuit 4 are electrically connected to an input terminal of the low-pass filter amplifier circuit 5, the output end of the electric energy metering chip U2 is electrically connected with the first input end of a digital signal processor chip U1, the output end of the low-pass filter amplifying circuit 5 is electrically connected with the second input end of a digital signal processor chip U1, the output end of the reference circuit 2 is electrically connected with the third input end of the digital signal processor chip U1, the output end of the analog power supply module M1 is electrically connected with the first input end of a voltage-stabilized power supply chip U3, the output end of the switch power supply module M2 is electrically connected with the second input end of a voltage-stabilized power supply chip U3, the output end of the voltage-stabilized power supply chip U3 is electrically connected with the fourth input end of a digital signal processor chip U1, the first output end of the digital signal processor chip U1 is electrically connected with the input end of a control interface chip U4, the second output end of the digital signal processor chip U1 is electrically connected with the input end of a communication interface chip U7, the output of communication interface chip U7 and gateway chip U8's input electric connection, No. three output and keyboard interface chip U10's input electric connection of digital signal processor chip U1, No. four output and LCD display chip U6's input electric connection of digital signal processor chip U1, No. five output and the input electric connection of regional chain chip U5 of digital signal processor chip U1.

The current acquisition circuit 3 comprises a current transformer CT, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a diode D1 and a diode D2, wherein a pin 1 of the current transformer CT is electrically connected with one end of a resistor R1, the other end of the resistor R1 is electrically connected with one end of the capacitor C1, the cathode of a diode D1, the anode of the diode D2 and a pin 1 of an electric energy metering chip U2, a pin 2 of the current transformer CT is electrically connected with one end of the resistor R2 and grounded, the other end of the resistor R2 is electrically connected with one end of the capacitor C2, the anode of the diode D1, the cathode of the diode D2 and a pin 2 of the electric energy metering chip U2, and the other end of the capacitor C1 is electrically connected with the other end of the capacitor C2 and grounded.

The voltage acquisition circuit 4 comprises a voltage transformer PT, a resistor R8, a resistor R9, a resistor R10, a capacitor C9 and a capacitor C10, wherein a pin 1 of the voltage transformer PT is electrically connected with one end of the resistor R8 and one end of the resistor R9 respectively, the other end of the resistor R9 is electrically connected with one end of the capacitor C9 and a pin 3 of the electric energy metering chip U2 respectively, a pin 2 of the voltage transformer PT is electrically connected with the other end of the resistor R8 and one end of the resistor R10 respectively and is grounded, the other end of the resistor R10 is electrically connected with one end of the capacitor C10 and a pin 4 of the electric energy metering chip U2 respectively, and the other end of the capacitor C9 is electrically connected with the other end of the capacitor C10 and is grounded.

The low-pass filtering amplifying circuit 5 comprises an operational amplifier chip N2C, an operational amplifier chip N2D, a resistor R28, a resistor R29, a resistor R30, a resistor R31, a resistor R32, a resistor R33, a resistor R34, a resistor R35, a resistor R36, a resistor R37, a resistor R38, a resistor R39, a resistor R40, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C17 and a diode D17, wherein one end of the resistor R17 is electrically connected with one end of the resistor R17 and one end of the capacitor C17 respectively, the other end of the capacitor C17 is grounded, the other end of the resistor R17 is electrically connected with one end of the resistor R17, the other end of the resistor R17 is electrically connected with one end of the capacitor C17, and one end of the capacitor C17 is electrically connected with one end of the capacitor C17, and the other end of the capacitor R17 is electrically connected with one end of the capacitor C363, the capacitor R17, and the other end of the capacitor C17 are electrically connected with one end of the capacitor C17, the other end of the resistor R31 is electrically connected with the other end of the capacitor C14 and the 1 pin of the operational amplifier chip N2C, the 2 pin of the operational amplifier chip N2C is grounded, the other end of the capacitor C16 is electrically connected with one end of the resistor R32, one end of the resistor R37 and one end of the resistor R40, the other end of the resistor R37 is connected with +3.5V, the other end of the resistor R40 is grounded, the other end of the resistor R32 is electrically connected with the cathode of the diode D3, one end of the capacitor C18 and the 5 pin of the digital signal processor chip U1, the anode of the diode D3 and the other end of the capacitor C18 are grounded, the other end of the resistor R33 is electrically connected with one end of the resistor R34, the other end of the resistor R34 is electrically connected with one end of the capacitor C13, one end of the resistor R35 and one end of the resistor R36, and the other end of the capacitor C13 is grounded, the other end of the resistor R35 is respectively electrically connected with one end of a capacitor C15, a 3 pin of an operational amplifier chip N2D and one end of a capacitor C17, the other end of the resistor R36 is respectively electrically connected with the other end of a capacitor C15 and a 1 pin of an operational amplifier chip N2D, a 2 pin of the operational amplifier chip N2D is grounded, the other end of the capacitor C17 is respectively electrically connected with one end of a resistor R38, one end of the resistor R39 and a 6 pin of a digital signal processor chip U1, the other end of the resistor R39 is connected with +3.5V, and the other end of the resistor R38 is grounded.

The reference circuit 2 comprises a resistor R41, a resistor R42, a resistor R43, a polar capacitor C19, a capacitor C20 and a thyristor N1, wherein one end of the resistor R41 is connected with +5V, the other end of the resistor R41 is electrically connected with one end of a resistor R42, a pin 1 of a thyristor N1, an anode of a polar capacitor C19, one end of a capacitor C20 and a pin 7 of a digital signal processor chip U1, the other end of the resistor R42 is electrically connected with one end of a resistor R43 and a pin 2 of a thyristor N1, and the other end of a resistor R43 is electrically connected with a pin 3 of a thyristor N1, a cathode of a polar capacitor C19 and the other end of a capacitor C20 and is grounded.

The electric energy metering chip U2's 5 pins and digital signal processor chip U1's 4 pins electric connection, electric energy metering chip U2's 6 pins and digital signal processor chip U1's 3 pins electric connection, electric energy metering chip U2's 7 pins and digital signal processor chip U1's 2 pins electric connection, electric energy metering chip U2's 8 pins and digital signal processor chip U1's 1 pin electric connection.

The 8 pins of the digital signal processor chip U1 are electrically connected with the 1 pin of the voltage stabilizing power supply chip U3, the 2 pins of the voltage stabilizing power supply chip U3 are electrically connected with the input end of the analog power supply module M1, the 3 pin of the voltage stabilizing power supply chip U3 is electrically connected with the input end of the switch power supply module M2, the 9 pin of the digital signal processor chip U1 is electrically connected with the 1 pin of the control interface chip U4, the 10 pin of the digital signal processor chip U1 is electrically connected with the 2 pin of the control interface chip U4, the 11 pin of the digital signal processor chip U1 is electrically connected with the 3 pin of the control interface chip U4, the 12 pin of the digital signal processor chip U1 is electrically connected with the 1 pin of the area interlocking chip U5, the 13 pin of the digital signal processor chip U1 is electrically connected with the 2 pin of the area interlocking chip U5, the 14 pins of the digital signal processor chip U1 are electrically connected with the 3 pins of the area interlocking chip U5, the 15 pins of the digital signal processor chip U1 are electrically connected with the 4 pins of the area interlocking chip U5, the 16 pins of the digital signal processor chip U1 are electrically connected with the 1 pin of the LCD display chip U6, the 17 pins of the digital signal processor chip U1 are electrically connected with the 2 pins of the LCD display chip U6, the 18 pins of the digital signal processor chip U1 are electrically connected with the 3 pins of the LCD display chip U6, the 19 pins of the digital signal processor chip U1 are electrically connected with the 4 pins of the LCD display chip U6, the 20 pins of the digital signal processor chip U1 are electrically connected with the 1 pin of the communication interface chip U7, the 21 pins of the digital signal processor chip U1 are electrically connected with the 2 pins of the communication interface chip U7, the 22 pins of the digital signal processor chip U1 are electrically connected with the 3 pins of the communication interface chip U7, the 6 pins of the communication interface chip U7 are electrically connected with the 1 pin of the gateway chip U8, the 5 pins of the communication interface chip U7 are electrically connected with the 2 pins of the gateway chip U8, the 4 pins of the communication interface chip U7 are electrically connected with the 3 pins of the gateway chip U8, the 23 pin of the digital signal processor chip U1 is electrically connected with the 1 pin of the keyboard interface chip U10, the 24 pins of the digital signal processor chip U1 are electrically connected with the 2 pins of the keyboard interface chip U10, the 25 pins of the digital signal processor chip U1 are electrically connected with the 3 pins of the keyboard interface chip U10, the 26 pins of the digital signal processor chip U1 are electrically connected with the 4 pins of the keyboard interface chip U10.

The above description is only for the specific embodiment of the present invention, but the structural features of the present invention are not limited thereto, and any person skilled in the art can make changes or modifications within the scope of the present invention.

Claims

1. A frame-type energy management type intelligent controller comprises a sampling circuit (1), a reference circuit (2), a digital signal processor chip U1, an electric energy metering chip U2, a communication interface chip U7, a keyboard interface chip U10, an LCD display chip U6, a region linkage chip U5, a control interface chip U4, a voltage-stabilized power supply chip U3, an analog power supply module M1, a switching power supply module M2 and a gateway chip U8, and is characterized in that the sampling circuit (1) comprises a current acquisition circuit (3), a voltage acquisition circuit (4) and a low-pass filtering amplification circuit (5), wherein a first output end of the current acquisition circuit (3) is electrically connected with an input end of the electric energy metering chip U2, and a second output end of the current acquisition circuit (3) and an output end of the voltage acquisition circuit (4) are respectively electrically connected with an input end of the low-pass filtering amplification circuit (5), the output end of the electric energy metering chip U2 is electrically connected with the first input end of a digital signal processor chip U1, the output end of the low-pass filtering amplifying circuit (5) is electrically connected with the second input end of a digital signal processor chip U1, the output end of the reference circuit (2) is electrically connected with the third input end of the digital signal processor chip U1, the output end of the analog power supply module M1 is electrically connected with the first input end of a voltage stabilizing power supply chip U3, the output end of the switching power supply module M2 is electrically connected with the second input end of a voltage stabilizing power supply chip U3, the output end of the voltage stabilizing power supply chip U3 is electrically connected with the fourth input end of a digital signal processor chip U1, the first output end of the digital signal processor chip U1 is electrically connected with the input end of a control interface chip U4, the second output end of the digital signal processor chip U1 is electrically connected with the input end of a communication interface chip U7, the output of communication interface chip U7 and gateway chip U8's input electric connection, No. three output and keyboard interface chip U10's input electric connection of digital signal processor chip U1, No. four output and LCD display chip U6's input electric connection of digital signal processor chip U1, No. five output and the input electric connection of regional chain chip U5 of digital signal processor chip U1.

2. A frame-type energy management intelligent controller according to claim 1, the current acquisition circuit (3) comprises a current transformer CT, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a diode D1 and a diode D2, a pin 1 of the current transformer CT is electrically connected with one end of a resistor R1, the other end of the resistor R1 is respectively and electrically connected with one end of a capacitor C1, the cathode of a diode D1, the anode of the diode D2 and a pin 1 of an electric energy metering chip U2, the 2 pins of the current transformer CT are electrically connected with one end of a resistor R2 and grounded, the other end of the resistor R2 is electrically connected with one end of a capacitor C2, the anode of a diode D1, the cathode of the diode D2 and the 2 pins of an electric energy metering chip U2, and the other end of the capacitor C1 is electrically connected with the other end of the capacitor C2 and grounded.

3. A frame-type energy management intelligent controller according to claim 1, wherein the voltage acquisition circuit (4) comprises a voltage transformer PT, a resistor R8, a resistor R9, a resistor R10, a capacitor C9 and a capacitor C10, wherein a pin 1 of the voltage transformer PT is electrically connected to one end of the resistor R8 and one end of the resistor R9, the other end of the resistor R9 is electrically connected to one end of the capacitor C9 and a pin 3 of the energy metering chip U2, a pin 2 of the voltage transformer PT is electrically connected to the other end of the resistor R8 and one end of the resistor R10 and grounded, the other end of the resistor R10 is electrically connected to one end of the capacitor C10 and a pin 4 of the energy metering chip U2, and the other end of the capacitor C9 and the other end of the capacitor C10 are electrically connected and grounded.

4. A frame-type energy management intelligent controller according to claim 1, wherein the low-pass filter amplifier circuit (5) comprises an operational amplifier chip N2C, an operational amplifier chip N2D, a resistor R28, a resistor R29, a resistor R30, a resistor R31, a resistor R32, a resistor R33, a resistor R34, a resistor R35, a resistor R36, a resistor R37, a resistor R38, a resistor R39, a resistor R40, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18 and a diode D3, wherein one end of the resistor R28 is electrically connected to one end of the resistor R33 and one end of the capacitor C11, the other end of the capacitor C11 is grounded, the other end of the resistor R28 is electrically connected to one end of the resistor R29, the other end of the resistor R8672 is electrically connected to one end of the capacitor R8672, and the other end of the capacitor R8672 is electrically connected to the capacitor C29, the other end of the resistor R30 is electrically connected to one end of a capacitor C14, a pin 3 of the operational amplifier chip N2C and one end of a capacitor C16, the other end of the resistor R31 is electrically connected to the other end of a capacitor C14 and a pin 1 of the operational amplifier chip N2C, a pin 2 of the operational amplifier chip N2C is grounded, the other end of the capacitor C16 is electrically connected to one end of a resistor R32, one end of a resistor R37 and one end of a resistor R40, the other end of the resistor R37 is connected to +3.5V, the other end of the resistor R40 is grounded, the other end of the resistor R32 is electrically connected to the cathode of a diode D3, one end of a capacitor C18 and a pin 5 of a digital signal processor chip U1, the anode of the diode D3 and the other end of a capacitor C18 are grounded, the other end of the resistor R33 is electrically connected to one end of the resistor R34, and the other end of the resistor R34 is electrically connected to one end of a capacitor C13, One end of a resistor R35 is electrically connected with one end of a resistor R36, the other end of the capacitor C13 is grounded, the other end of the resistor R35 is electrically connected with one end of a capacitor C15, a pin 3 of an operational amplifier chip N2D and one end of a capacitor C17, the other end of a resistor R36 is electrically connected with the other end of the capacitor C15 and a pin 1 of an operational amplifier chip N2D, a pin 2 of the operational amplifier chip N2D is grounded, the other end of the capacitor C17 is electrically connected with one end of the resistor R38, one end of a resistor R39 and a pin 6 of a digital signal processor chip U1, the other end of the resistor R39 is connected with +3.5V, and the other end of the resistor R38 is grounded.

5. A frame-type energy management intelligent controller according to claim 1, wherein the reference circuit (2) comprises a resistor R41, a resistor R42, a resistor R43, a polar capacitor C19, a capacitor C20 and a thyristor N1, wherein one end of the resistor R41 is connected to +5V, the other end of the resistor R41 is electrically connected to one end of the resistor R42, a pin 1 of the thyristor N1, an anode of the polar capacitor C19, one end of the capacitor C20 and a pin 7 of the dsp chip U1, the other end of the resistor R42 is electrically connected to one end of the resistor R43 and a pin 2 of the thyristor N1, and the other end of the resistor R43 is electrically connected to a pin 3 of the thyristor N1, a cathode of the polar capacitor C19 and the other end of the capacitor C20 and is grounded.

6. A frame-type energy management intelligent controller according to claim 1, wherein the 5 pins of the electric energy metering chip U2 are electrically connected to the 4 pins of the digital signal processor chip U1, the 6 pins of the electric energy metering chip U2 are electrically connected to the 3 pins of the digital signal processor chip U1, the 7 pins of the electric energy metering chip U2 are electrically connected to the 2 pins of the digital signal processor chip U1, and the 8 pins of the electric energy metering chip U2 are electrically connected to the 1 pin of the digital signal processor chip U1.

7. A frame-type energy management intelligent controller as claimed in claim 1, wherein the 8 pins of the digital signal processor chip U1 are electrically connected to the 1 pin of the constant voltage power supply chip U3, the 2 pins of the constant voltage power supply chip U3 are electrically connected to the input terminal of the analog power supply module M1, the 3 pins of the constant voltage power supply chip U3 are electrically connected to the input terminal of the switching power supply module M2, the 9 pins of the digital signal processor chip U1 are electrically connected to the 1 pin of the control interface chip U4, the 10 pins of the digital signal processor chip U1 are electrically connected to the 2 pins of the control interface chip U4, the 11 pins of the digital signal processor chip U1 are electrically connected to the 3 pins of the control interface chip U4, the 12 pins of the digital signal processor chip U1 are electrically connected to the 1 pin of the region-linked chip U5, the pin 13 of the digital signal processor chip U1 is electrically connected with the pin 2 of the area interlocking chip U5, the pin 14 of the digital signal processor chip U1 is electrically connected with the pin 3 of the area interlocking chip U5, the pin 15 of the digital signal processor chip U1 is electrically connected with the pin 4 of the area interlocking chip U5, the pin 16 of the digital signal processor chip U1 is electrically connected with the pin 1 of the LCD display chip U6, the pin 17 of the digital signal processor chip U1 is electrically connected with the pin 2 of the LCD display chip U6, the pin 18 of the digital signal processor chip U1 is electrically connected with the pin 3 of the LCD display chip U6, the pin 19 of the digital signal processor chip U1 is electrically connected with the pin 4 of the LCD display chip U6, the pin 20 of the digital signal processor chip U1 is electrically connected with the pin 1 of the communication interface chip U7, the 21 pin of the digital signal processor chip U1 is electrically connected with the 2 pin of the communication interface chip U7, the 22 pin of the digital signal processor chip U1 is electrically connected with the 3 pin of the communication interface chip U7, the 6 pin of the communication interface chip U7 is electrically connected with the 1 pin of the gateway chip U8, the 5 pin of the communication interface chip U7 is electrically connected with the 2 pin of the gateway chip U8, the 4 pin of the communication interface chip U7 is electrically connected with the 3 pin of the gateway chip U8, the 23 pin of the digital signal processor chip U1 is electrically connected with the 1 pin of the keyboard interface chip U10, the 24 pin of the digital signal processor chip U1 is electrically connected with the 2 pin of the keyboard interface chip U10, the 25 pin of the digital signal processor chip U1 is electrically connected with the 3 pin of the keyboard interface chip U10, the 26 pins of the digital signal processor chip U1 are electrically connected with the 4 pins of the keyboard interface chip U10.