CN215010692U

CN215010692U - Sound breaking eliminating circuit and sound breaking eliminating device

Info

Publication number: CN215010692U
Application number: CN202121128289.7U
Authority: CN
Inventors: 伍志锋; 杨信; 熊新斌
Original assignee: Shenzhen Jiarun Original Xinxian Technology Co ltd
Current assignee: Shenzhen Jiarun Original Xinxian Technology Co ltd
Priority date: 2021-05-21
Filing date: 2021-05-21
Publication date: 2021-12-03
Anticipated expiration: 2031-05-21

Abstract

The utility model provides a sound breaking and eliminating circuit and a sound breaking and eliminating device, wherein the sound breaking and eliminating circuit comprises a main switch circuit, a main control chip, a horn switch circuit and a power amplifier output circuit; the controlled end of the main switch circuit is connected with a power supply interface, the first connecting end of the main switch circuit and the signal output end of the main control chip are connected with the controlled end of the horn switch circuit, and the second connecting end of the main switch circuit is grounded; the first connecting end of the horn switch circuit is connected with a direct-current power supply and the power amplifier output circuit, and the second connecting end of the horn switch circuit is grounded. The technical scheme of the utility model, loudspeaker appear the technical problem of broken sound when can solving display device switching on and shutting down.

Description

Sound breaking eliminating circuit and sound breaking eliminating device

Technical Field

The utility model relates to a show technical field, in particular to broken sound cancelling circuit and broken sound cancelling device.

Background

When the display device is turned on or off, the loudspeaker and the earphone often send out sound breaking, and user experience is influenced. According to the technical scheme, the technical problem that a loudspeaker and an earphone are broken when the display device is turned on and turned off is mainly solved through software.

However, when the display device is turned on and off, the software cannot control the board card to normally operate, so that the earphone and the loudspeaker always have sound breaking; moreover, the existing technical scheme mainly solves the sound breaking problem of the loudspeaker and the earphone when the display device is turned on and turned off by reducing the sound breaking volume, and the sound breaking of the loudspeaker and the earphone can not be completely eliminated.

SUMMERY OF THE UTILITY MODEL

The utility model provides a broken sound cancelling circuit and broken sound cancelling device aims at solving the technical problem that broken sound appears in loudspeaker when display device switching on and shutting down, promotes user experience.

In order to achieve the above object, the present invention provides a sound breaking and canceling circuit, which includes a main switch circuit, a main control chip, a horn switch circuit and a power amplifier output circuit;

the controlled end of the main switch circuit is connected with a power supply interface, the first connecting end of the main switch circuit and the signal output end of the main control chip are connected with the controlled end of the horn switch circuit, and the second connecting end of the main switch circuit is grounded;

the first connecting end of the horn switch circuit is connected with a direct-current power supply and the power amplifier output circuit, and the second connecting end of the horn switch circuit is grounded.

Optionally, the main switch circuit includes a first sub-switch circuit and a second sub-switch circuit;

the controlled end of the first sub-switch circuit is connected with the power supply interface, the first connecting end of the first sub-switch circuit is grounded, and the second connecting end of the first sub-switch circuit is connected with the controlled end of the second sub-switch circuit;

the first connecting end of the second sub-switch circuit is connected with the signal output end of the main control chip and the controlled end of the horn switch circuit, and the second connecting end of the second sub-switch circuit is grounded.

Optionally, the first sub-switch circuit includes a first resistor, a second resistor, a diode, a capacitor, and a PNP triode;

one end of the first resistor and the anode of the diode are connected with the power supply interface, and the other end of the first resistor is connected with the base electrode of the PNP triode;

the negative electrode of the diode is connected with one end of the second resistor, one end of the capacitor and the emitting electrode of the PNP triode, and the other ends of the second resistor and the capacitor are grounded;

and the collector electrode of the PNP triode is connected with the controlled end of the second sub-switch circuit.

Optionally, the second sub-switch circuit includes a third resistor and a first NPN transistor;

one end of the third resistor is connected with the collector of the PNP triode, and the other end of the third resistor is connected with the base of the first NPN triode;

and the collector of the first NPN triode is connected with the signal output end of the main control chip and the controlled end of the horn switch circuit, and the emitter of the first NPN triode is grounded.

Optionally, the horn switch circuit includes a fourth resistor, a fifth resistor, a sixth resistor, and a second NPN transistor;

one end of the fourth resistor and one end of the fifth resistor are connected with the collector of the first NPN triode and the signal output end of the main control chip, and the other end of the fourth resistor is connected with the base of the second NPN triode;

a collector of the second NPN triode is connected with one end of the sixth resistor and the power amplifier output circuit, and the other end of the sixth resistor is connected with the direct-current power supply;

the other end of the fifth resistor and the emitting electrode of the second NPN triode are grounded.

Optionally, the main switch circuit further includes a third sub-switch circuit, and the sound breaking and canceling circuit further includes an earphone switch circuit;

the controlled end of the third sub-switch circuit is connected with the second connecting end of the first sub-switch circuit, the first connecting end of the third sub-switch circuit is connected with the controlled end of the earphone switch circuit and the signal output end of the main control chip, and the second connecting end of the third sub-switch circuit is grounded;

the first input end of the earphone switch circuit is connected with the first audio output end of the main control chip, and the first output end of the earphone switch circuit is connected with the first audio input end of an earphone;

the second input end of the earphone switch circuit is connected with the second audio output end of the main control chip, and the second output end of the earphone switch circuit is connected with the second audio input end of the earphone.

Optionally, the third sub-switch circuit includes a seventh resistor and a third NPN transistor;

one end of the seventh resistor is connected with the second connecting end of the first sub-switch circuit, and the other end of the seventh resistor is connected with the base electrode of the third NPN triode;

and the collector of the third NPN triode is connected with the controlled end of the earphone switch circuit and the signal output end of the main control chip, and the emitter of the third NPN triode is grounded.

Optionally, the earphone switch circuit includes a first transistor and a second transistor;

the controlled end of the first transistor is connected with the collector electrode of the third NPN triode and the signal output end of the main control chip, the input end of the first transistor is connected with the first audio output end of the main control chip, and the output end of the first transistor is connected with the first audio input end of the earphone;

the controlled end of the second transistor is connected with the collector of the third NPN triode and the signal output end of the main control chip, the input end of the second transistor is connected with the second audio output end of the main control chip, and the output end of the second transistor is connected with the second audio input end of the earphone.

Optionally, the first transistor and the second transistor are N-MOS transistors.

In order to achieve the above object, the present invention further provides a sound breaking and canceling device, which includes the sound breaking and canceling circuit as described above.

The technical scheme of the utility model, when display device starts, the voltage risees when utilizing the start to trigger the main switch circuit and turn off, recycles the signal output part of main control chip under the initialization state for the low level controls loudspeaker switch circuit and also turns off, and at this moment, power amplifier output circuit turns off under DC power supply's effect, makes loudspeaker can't receive any audio output signal through making power amplifier output circuit turn off, then loudspeaker can not produce the broken sound when starting; when the display device is shut down, the power supply interface is quickly powered down to trigger the main switch circuit to be switched on, when the main switch circuit is switched on, the signal output end of the main control chip is pulled down to a low level, so that the loudspeaker switch circuit is switched off, at the moment, the power amplifier output circuit is switched off under the action of the direct current power supply, the loudspeaker cannot receive any audio output signal by switching off the power amplifier output circuit, and the loudspeaker cannot break sound when the display device is shut down. So set up, loudspeaker send the technical problem of broken sound when can solving the switching on and shutting down, improved user experience.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

Fig. 1 is a block diagram of an embodiment of the sound breaking and canceling circuit of the present invention;

FIG. 2 is a block diagram of an embodiment of the main switch circuit of FIG. 1;

fig. 3 is a schematic circuit diagram of an embodiment of the sound breaking and canceling circuit of the present invention;

fig. 4 is a block diagram of another embodiment of the sound breaking and canceling circuit of the present invention;

fig. 5 is a schematic circuit diagram of another embodiment of the sound breaking and canceling circuit of the present invention.

The reference numbers illustrate:

10	main switch circuit	20	Master control chip
				30	Horn switch circuit	40	Power amplifier output circuit
50	Horn type loudspeaker	60	Earphone switch circuit
				70	Earphone set	101	First sub-switch circuit
102	Second sub-switch circuit	103	Third sub-switch circuit
				R1～R8	First to eighth resistors	C1	Capacitor with a capacitor element
D1	Diode with a high-voltage source	Q1	PNP triode
				Q2	A first NPN triode	Q3	Second NPN triode
Q4	Third NPN triode	Q5	A first transistor
				Q6	Second transistor	VIN	Power supply interface
GND	Ground

The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

It should be noted that, if directional indications (such as upper, lower, left, right, front and rear … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are changed accordingly.

In addition, if there is a description relating to "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.

Fig. 1 is a block diagram of an embodiment of the sound breaking and canceling circuit of the present invention.

Referring to fig. 1, the sound breaking and canceling circuit includes a main switch circuit 10, a main control chip 20, a horn switch circuit 30, and a power amplifier output circuit 40. The controlled end of the main switch circuit 10 is connected to a power supply interface VIN, the first connection end of the main switch circuit 10 and the signal output end SD of the main control chip 20 are both connected to the controlled end of the horn switch circuit 30, and the second connection end of the main switch circuit 10 is grounded; the first connection end of the horn switch circuit 30 is connected to a DC power supply DC and the power amplifier output circuit 40, and the second connection end of the horn switch circuit 30 is grounded.

The main switch circuit 10 has two states of on and off, and may be implemented by a circuit composed of an energy storage capacitor, a resistor, and various transistors, such as an insulating fet, a triode, and the like, without limitation. The on and off of the main switch circuit 10 is determined by the voltage at the power supply interface VIN.

The main control chip 20 may be a single chip, a DSP or a microprocessor such as an FPGA.

The horn switch circuit 30 has two states of on and off, and can be implemented by various transistor circuits, such as an insulating fet, a triode, and other compound switch circuits composed of a plurality of transistors, but not limited thereto. The horn switch circuit 30 has the following characteristics: when the controlled end of the horn switch circuit 30 is at a low level, the horn switch circuit 30 is turned off; when the controlled terminal of the horn switch circuit 30 is at a high level, the horn switch circuit 30 is turned on.

The power on/off pin of the power amplifier output circuit 40 is connected to the first connection terminal of the horn switch circuit 30 and the DC power supply DC, and the power amplifier output circuit 40 is electrically connected to a horn 50. The power amplifier output circuit 40 has the following characteristics: when the power on/off pin of the power amplifier switch circuit 40 is at a low level, the power amplifier output circuit 40 is started to operate and drives the loudspeaker 50 to sound; when the power on/off pin of the power amplifier output circuit 40 is at a high level, the power amplifier output circuit 40 is turned off and stops driving the loudspeaker 50 to sound.

As is well known, when the display apparatus is turned on or off, because the software of the main control chip 20 is in an abnormal operating state during the turning on or off process, the software is not controllable to the output state of the audio receiving device, such as a speaker and an earphone, but the main control chip 20 still releases the audio decoding signal to the audio receiving device, so that the audio receiving device, such as a speaker and an earphone, generates sound breaking.

To solve the above problem, the present embodiment provides a noise cancellation circuit, and the specific operating principle of the noise cancellation circuit is as follows:

when the display device is turned on, the voltage of the power supply interface VIN is increased to trigger the main switch circuit 10 to turn off, and meanwhile, the signal output terminal SD of the main control chip 20 is at a low level (the signal output terminal SD of the main control chip 20 is a pull-down pin of the main control chip 20, and the signal output terminal SD of the main control chip 20 is at a low level in an initialization state). Since the main switch circuit 10 is in an off state and the signal output terminal SD of the main control chip 20 is at a low level when being powered on, the controlled terminal of the horn switch circuit 30 is at a low level, and the horn switch circuit 30 is also turned off. In this case, a voltage of the DC power supply DC, for example, a voltage of 5V, flows into the power on/off pin of the power amplifier output circuit 40, so that the power amplifier output circuit 40 is turned off and stops working, and then the speaker 50 does not receive any audio output signal, and the speaker 50 does not emit any sound breaking.

When the display device is turned off, the power supply interface VIN is quickly powered down to trigger the main switch circuit 10 to be turned on, and the signal output end SD of the main control chip 20 is pulled down to a low level when the main switch circuit 10 is turned on, so that the controlled end of the horn switch circuit 30 is at the low level, and the horn switch circuit 30 is turned off. In this case, a voltage of the DC power supply DC, for example, a voltage of 5V, flows into the power on/off pin of the power amplifier output circuit 40, so that the power amplifier output circuit 40 is turned off and stops working, and then the speaker 50 does not receive any audio output signal, and the speaker 50 does not emit any sound breaking.

To sum up, the technical scheme of the utility model, when display device starts, the voltage risees and triggers main switch circuit 10 to turn off when utilizing the start, recycles signal output terminal SD of main control chip 20 under the initialization state for the low level controls loudspeaker switch circuit 30 and also turns off, and under this condition, power amplifier output circuit 40 turns off under DC power supply DC's effect, makes loudspeaker 50 can't receive audio output signal through making power amplifier output circuit 40 turn off, then loudspeaker 50 just can not produce the sound breaking when starting; when the display device is shut down, the power supply interface VIN is quickly powered down to trigger the main switch circuit 10 to be switched on, when the main switch circuit is switched on 10, the signal output end SD of the main control chip 20 is pulled down to a low level, so that the horn switch circuit 30 is switched off, in this case, the power amplifier output circuit 40 is switched off under the action of the direct current power supply DC, the horn 50 cannot receive any audio output signal by switching off the power amplifier output circuit 40, and then the horn 50 cannot generate sound breaking when the display device is shut down. By the arrangement, the technical problem that the loudspeaker 50 generates sound breaking when the computer is turned on and turned off can be solved, and the user experience is improved.

Optionally, referring to fig. 2, in an embodiment, the main switching circuit 10 includes a first sub-switching circuit 101 and a second sub-switching circuit 102; the controlled end of the first sub-switch circuit 101 is connected to the power supply interface VIN, the first connection end of the first sub-switch circuit 101 is grounded, and the second connection end of the first sub-switch circuit 101 is connected to the controlled end of the second sub-switch circuit 102; the first connection end of the second sub-switch circuit 102 is connected to the controlled end of the horn switch circuit 30 and the signal output end SD of the main control chip 20, and the second connection end of the second sub-switch circuit 102 is grounded.

The first sub-switch circuit 101 has two states of on and off, and may be implemented by a circuit formed by an energy storage capacitor, a resistor, and various transistors, such as an insulating fet, a triode, and the like, without limitation. In this embodiment, the first sub-switch circuit 101 may be a switch circuit that is turned on at a low level.

The second sub-switch circuit 102 has two states of on and off, and can be implemented by various transistor circuits, such as an insulated fet, a triode, and other compound switch circuits composed of multiple transistors, but not limited thereto. In this embodiment, the second sub-switch circuit 102 can be selected as a high-level conducting switch circuit.

The specific operating principle of the main switching circuit 10 is as follows:

when the display device is turned on, the voltage of the power supply interface VIN is increased to trigger the first sub-switch circuit 101 to turn off. When the first sub-switch circuit 101 is turned off, since no voltage reaches the controlled terminal of the second sub-switch circuit 102, the second sub-switch circuit 102 is also turned off, and at this time, the signal output terminal SD of the main control chip 20 is at a low level (the signal output terminal SD of the main control chip 20 is a pull-down pin of the main control chip 20, and the signal output terminal SD of the main control chip 20 is at a low level in an initialization state). Therefore, the controlled terminal of the horn switch circuit 30 is at a low level, and the horn switch circuit 30 is also turned off.

When the display device is turned off, the power supply interface VIN is quickly powered off to trigger the first sub-switch circuit 101 to be turned on. When the first sub-switch circuit 101 is turned on, the voltage of the energy storage capacitor inside the first sub-switch circuit 101 reaches the controlled terminal of the second sub-switch circuit 102 through the turned-on first sub-switch circuit 101, so that the second sub-switch circuit 102 is also turned on. The second sub-switch circuit 102 is turned on to pull the signal output terminal SD of the main control chip 20 low. Therefore, the controlled terminal of the horn switch circuit 30 is at a low level, and the horn switch circuit 30 is also turned off.

Optionally, referring to fig. 3, in an embodiment, the first sub-switch circuit 101 includes a first resistor R1, a second resistor R2, a diode D1, a capacitor C1, and a PNP transistor Q1; one end of the first resistor R1 and the anode of the diode D1 are connected with the power supply interface VIN, and the other end of the first resistor R1 is connected with the base electrode of the PNP triode Q1; the cathode of the diode D1 is connected to one end of the second resistor R2, one end of the capacitor C1, and the emitter of the PNP transistor Q1; the other end of the second resistor R2 and the other end of the capacitor C1 are grounded; the collector of the PNP transistor Q1 is connected to the controlled terminal of the second sub-switch circuit 102.

The first sub-switch circuit 101 operates as follows:

when the display device is turned on, the voltage of the power supply interface VIN charges the capacitor C1 through the diode D1, and meanwhile, the voltage of the power supply interface VIN reaches the base of the PNP triode Q1 through the first resistor R1, and due to the voltage characteristic of the diode D1, namely, the voltage difference, the voltage of the emitter of the PNP triode Q1 is lower than the base voltage thereof, and the PNP triode Q1 is turned off. Since the PNP transistor Q1 is turned off, no voltage reaches the controlled terminal of the second sub-switch circuit 102, and then the second sub-switch circuit 102 is also turned off.

When the display device is turned off, the power supply interface VIN is powered down quickly, at this time, the capacitor C1 discharges outwards through the second resistor R2 (wherein, the resistance value of the second resistor R2 is set reasonably, and the capacitor C1 discharges slowly by using the characteristic that the diode D1 has reverse cut-off), when the voltage of the capacitor C1 is higher than the preset voltage value of the power supply interface VIN, for example, when the voltage of the capacitor C1 is higher than 0.7V of the power supply interface VIN, the voltage of the emitter of the PNP triode Q1 is higher than the base voltage thereof, and the PNP triode Q1 is in a conducting state at the moment of turning off. Since the PNP transistor Q1 is turned on, the voltage of the capacitor C1 reaches the controlled terminal of the second sub-switch circuit 102 through the turned-on PNP transistor Q1, so that the second sub-switch circuit 102 is also turned on.

Optionally, referring to fig. 3, in an embodiment, the second sub-switch circuit 102 includes a third resistor R3 and a first NPN transistor Q2; one end of the third resistor R3 is connected with the collector of the PNP triode Q1, and the other end of the third resistor R3 is connected with the base of the first NPN triode Q2; the collector of the first NPN transistor Q2 is connected to the controlled terminal of the horn switch circuit 30 and the signal output terminal SD of the main control chip 20, and the emitter of the first NPN transistor Q2 is grounded.

Specifically, when the display device is turned on, the PNP transistor Q1 is turned off, and at this time, no voltage reaches the third resistor R3, so the first NPN transistor Q2 is also turned off, and the signal output terminal SD of the main control chip 20 is at a low level in the initialization state, so the controlled terminal of the horn switch circuit 30 is at a low level, and the horn switch circuit 30 is also turned off.

When the display device is turned off, the PNP transistor Q1 is turned on, and at this time, the voltage of the capacitor C1 reaches the third resistor R3 through the conductive PNP transistor Q1, and then reaches the base of the first NPN transistor Q2 through the third resistor R3, so that when the base voltage of the first NPN transistor Q2 is higher than the emitter voltage preset value, for example, the base voltage of the first NPN transistor Q2 is higher than the emitter voltage thereof by more than 0.7V, and the first NPN transistor Q2 is turned on. In this case, the signal output terminal SD of the main control chip 20 is pulled down to a low level, so that the controlled terminal of the horn switch circuit 30 is at a low level, and the horn switch circuit 30 is turned off.

Optionally, referring to fig. 3, in an embodiment, the horn switch circuit 30 includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a second NPN transistor Q3; wherein,

one end of the fourth resistor R4 and one end of the fifth resistor R5 are connected to the collector of the first NPN transistor Q2 and the signal output terminal SD of the main control chip 20, and the other end of the fourth resistor R4 is connected to the base of the second NPN transistor Q3; a collector of the second NPN triode Q3 is connected to one end of the sixth resistor R6 and the power amplifier output circuit 40 (connected to a power on/off pin of the power amplifier output circuit 40), and the other end of the sixth resistor R6 is connected to the DC power supply; the other end of the fifth resistor R5 and the emitter of the second NPN transistor Q3 are grounded.

The specific working principle is as follows:

when the display device is turned on, the PNP transistor Q1 is turned off, and at this time, no voltage reaches the third resistor R3, so the first NPN transistor Q2 is also turned off, and the signal output terminal SD of the main control chip 20 is at a low level in the initialization state, so the second NPN transistor Q3 is also turned off. In this case, the voltage of the DC power supply DC, for example, the voltage of 5V, flows into the power on/off pin of the power amplifier output circuit 40, so that the power amplifier output circuit 40 is turned off and stops working, and then the speaker 50 does not receive any audio output signal, and the speaker 50 does not emit any sound during power on.

When the display device is turned off, the PNP transistor Q1 is turned on, and at this time, the voltage of the capacitor C1 reaches the third resistor R3 through the turned-on PNP transistor Q1, and then reaches the base of the first NPN transistor Q2 through the third resistor R3, so that the first NPN transistor Q2 is turned on. In this case, the signal output terminal SD of the main control chip 20 is pulled low, so that the second NPN transistor Q3 is turned off. When the second NPN transistor Q3 is turned off, a voltage of the DC power supply DC, for example, a voltage of 5V, flows into the power on/off pin of the power amplifier output circuit 40, so that the power amplifier output circuit 40 is turned off and stops working, and then the speaker 50 does not receive any audio output signal, and the speaker 50 does not emit any sound breaking.

Optionally, referring to fig. 4, in an embodiment, the main switch circuit 10 further includes a third sub-switch circuit 103, and the sound-breaking cancellation circuit further includes an earphone switch circuit 50; the controlled end of the third sub-switch circuit 103 is connected to the second connection end of the first sub-switch circuit 101, the first connection end of the third sub-switch circuit 103 is connected to the controlled end of the earphone switch circuit 60 and the signal output end SD of the main control chip 10, and the second connection end of the third sub-switch circuit 103 is grounded.

A first input end of the earphone switch circuit 60 is connected with a first audio output end R of the main control chip 20, and a first output end of the earphone switch circuit 60 is connected with a first audio input end 1 of an earphone 70;

a second input terminal of the earphone switch circuit 60 is connected to the second audio output terminal L of the main control chip 20, and a second output terminal of the earphone switch circuit 60 is connected to the second audio input terminal 2 of the earphone 70.

The third sub-switch circuit 103 has two states of on and off, and can be implemented by various transistor circuits, such as an insulated fet, a triode, and other compound switch circuits composed of a plurality of transistors, but not limited thereto. In this embodiment, the third sub-switch circuit 103 can be selected as a high-level conducting switch circuit.

The earphone switch circuit 60 has two states of on and off, and can be implemented by various transistor-forming circuits, such as an insulating fet, a triode, and other compound switch circuits formed by a plurality of transistors, but not limited thereto. In this embodiment, the earphone switch circuit 60 may be a high-level conducting switch circuit.

The specific working principle is as follows:

when the display device is turned on, the voltage of the power supply interface VIN is increased to trigger the first sub-switch circuit 101 to turn off. When the first sub-switch circuit 101 is turned off, no voltage reaches the controlled terminal of the third sub-switch circuit 103, and then the third sub-switch circuit 103 is also turned off. In the initialization state, the signal output end SD of the main control chip 20 is at a low level, and therefore, the earphone switch circuit 60 is in the off state, so that the first audio input end 1 and the second audio input end 2 of the earphone 70 are not turned on at all, and the audio decoding signal output by the main control chip 20 cannot reach the earphone 70, and therefore, the earphone 70 does not generate any sound breaking when being turned on.

When the display device is turned off, the power supply interface VIN is quickly powered off to trigger the first sub-switch circuit 101 to be turned on. When the first sub-switch circuit 101 is turned on, the voltage of the energy storage capacitor inside the first sub-switch circuit 101 reaches the controlled terminal of the third sub-switch circuit 103 through the turned-on first sub-switch circuit 101, so that the third sub-switch circuit 103 is also turned on. The third sub-switch circuit 103 is turned on to pull the signal output terminal SD of the main control chip 20 low. Since the signal output end SD of the main control chip 20 is at a low level, the earphone switch circuit 60 is in an off state, so that the first audio input end 1 and the second audio input end 2 of the earphone 70 are not turned on at all, and the audio decoding signal output by the main control chip 20 cannot reach the earphone 70, so that the earphone 70 does not generate any sound break when being turned on.

In summary, the third sub-switch circuit 103 and the earphone switch circuit 60 are provided in this embodiment, the third sub-switch circuit 103 and the main control chip 20 cooperate to enable the earphone switch circuit 60 to be in the off state when the headset is powered on and powered off, so that the audio decoding signal output by the main control chip 20 cannot reach the earphone 70, and therefore the earphone 70 cannot generate any sound breaking no matter the headset is powered on or powered off.

Optionally, referring to fig. 5, in an embodiment, the third sub-switch circuit 103 includes a seventh resistor R7 and a third NPN transistor Q4; one end of the seventh resistor R7 is connected to the second connection end of the first sub-switch circuit 101, and the other end of the seventh resistor R7 is connected to the base of the third NPN triode Q4; the collector of the third NPN transistor Q4 is connected to the controlled terminal of the headphone switch circuit 60 and the signal output terminal SD of the main control chip 20, and the emitter of the third NPN transistor Q4 is grounded.

Specifically, when the display device is turned on, the voltage of the power supply interface VIN is increased to trigger the first sub-switch circuit 101 to turn off. When the first sub-switch circuit 101 is turned off, since no voltage reaches the seventh resistor R7, the third NPN transistor Q4 is also turned off. In the initialization state, the signal output terminal SD of the main control chip 20 is at a low level, and therefore, the earphone switch circuit 60 is in an off state. In this case, the first audio input terminal 1 and the second audio input terminal 2 of the earphone 70 are not conducted at all, and then the audio decoding signal output by the main control chip 20 cannot reach the earphone 70, so that the earphone 70 does not generate any sound breaking when being powered on.

When the display device is turned off, the power supply interface VIN is quickly powered off to trigger the first sub-switch circuit 101 to be turned on. When the first sub-switch circuit 101 is turned on, the voltage of the energy storage capacitor inside the first sub-switch circuit 101 reaches the seventh resistor R7 through the turned-on first sub-switch circuit 101, so that the third NPN transistor Q4 is also turned on. The third NPN transistor Q4 turns on to pull the signal output terminal SD of the main control chip 20 low. Since the signal output terminal SD of the main control chip 20 is at a low level, the earphone switch circuit 60 is in an off state. In this case, the first audio input terminal 1 and the second audio input terminal 2 of the earphone 70 are not conducted at all, and then the audio decoding signal output by the main control chip 20 cannot reach the earphone 70, so that the earphone 70 does not generate any sound breaking when being powered on.

Optionally, referring to fig. 5, in one embodiment, the headset switch circuit 60 includes a first transistor Q5 and a second transistor Q6; wherein,

a controlled end of the first transistor Q5 is connected to a collector of the third NPN triode Q4 and the signal output end SD of the main control chip 20, an input end of the first transistor Q5 is connected to the first audio output end R of the main control chip 20, and an output end of the first transistor R5 is connected to the first audio input end 1 of the earphone 70;

the controlled end of the second transistor Q6 is connected to the collector of the third NPN transistor Q4 and the signal output end SD of the main control chip 20, the input end of the second transistor Q6 is connected to the second audio output end L of the main control chip 20, and the output end of the second transistor Q6 is connected to the second audio input end 2 of the earphone 70.

Optionally, in this embodiment, the first transistor Q5 and the second transistor Q6 are both N-MOS transistors.

Specifically, when the display device is turned on, the voltage of the power supply interface VIN is increased to trigger the first sub-switch circuit 101 to turn off. When the first sub-switch circuit 101 is turned off, the third NPN transistor Q4 is also turned off because no voltage reaches the seventh resistor R7. At this time, since the signal output terminal SD of the main control chip 20 is at a low level in the initialization state, the first transistor Q5 and the second transistor Q6 are in an off state. In this case, the first audio input terminal 1 and the second audio input terminal 2 of the earphone 70 are not conducted at all, and then the audio decoding signal output by the main control chip 20 cannot reach the earphone 70, so that the earphone 70 does not generate any sound breaking when being powered on.

When the display device is turned off, the power supply interface VIN is quickly powered off to trigger the first sub-switch circuit 101 to be turned on. When the first sub-switch circuit 101 is turned on, the voltage of the energy storage capacitor inside the first sub-switch circuit 101 reaches the seventh resistor R7 through the turned-on first sub-switch circuit 101, so that the third NPN transistor Q4 is also turned on. The conduction of the third NPN transistor Q4 pulls the signal output terminal SD of the main control chip 20 low. Since the signal output terminal SD of the main control chip 20 is at a low level, the first transistor Q5 and the second transistor Q6 are in an off state. In this case, the first audio input terminal 1 and the second audio input terminal 2 of the earphone 70 are not conducted at all, and then the audio decoding signal output by the main control chip 20 cannot reach the earphone 70, so that the earphone 70 does not generate any sound breaking when being powered on.

Optionally, referring to fig. 5, in an embodiment, the sound break cancellation circuit further includes an eighth resistor R8; the signal output terminal SD of the main control chip 20 is connected to the controlled terminal of the speaker switch circuit 30 and the controlled terminal of the earphone switch circuit 60 through an eighth resistor R8. The eighth resistor R8 is a current limiting resistor for protecting circuit components.

The utility model also provides a sound breaking and eliminating device, which comprises the sound breaking and eliminating circuit, the detailed structure of the sound breaking and eliminating circuit can refer to the above embodiment, and the details are not repeated herein; it can be understood that, because the utility model discloses an above-mentioned broken sound cancelling circuit has been used among the broken sound cancelling device, consequently, the utility model discloses a broken sound cancelling device's embodiment includes all technical scheme of the whole embodiments of above-mentioned broken sound cancelling circuit, and the technical effect who reaches is also identical, no longer gives details here.

The above is only the optional embodiment of the present invention, and not the scope of the present invention is limited thereby, all the equivalent structure changes made by the contents of the specification and the drawings are utilized under the inventive concept of the present invention, or the direct/indirect application in other related technical fields is included in the patent protection scope of the present invention.

Claims

1. A sound breaking and eliminating circuit is characterized by comprising a main switch circuit, a main control chip, a horn switch circuit and a power amplifier output circuit;

2. The sound break cancellation circuit of claim 1, wherein the main switching circuit includes a first sub-switching circuit and a second sub-switching circuit;

3. The sound break cancellation circuit of claim 2, wherein the first sub-switch circuit comprises a first resistor, a second resistor, a diode, a capacitor, and a PNP transistor;

4. The sound breaking and canceling circuit of claim 3, wherein the second sub-switch circuit comprises a third resistor and a first NPN transistor;

5. The sound breaking and eliminating circuit of claim 4, wherein the horn switch circuit comprises a fourth resistor, a fifth resistor, a sixth resistor and a second NPN transistor;

6. The sound break cancellation circuit of claim 2, wherein the main switch circuit further comprises a third sub-switch circuit, the sound break cancellation circuit further comprising an earphone switch circuit;

7. The sound breaking and canceling circuit of claim 6, wherein the third sub-switch circuit comprises a seventh resistor and a third NPN transistor;

8. The sound break cancellation circuit of claim 7, wherein the headphone switch circuit comprises a first transistor and a second transistor;

9. The sound break cancellation circuit according to claim 8, wherein the first transistor and the second transistor are N-MOS transistors.

10. A sound break eliminating apparatus, characterized in that the sound break eliminating apparatus comprises a sound break eliminating circuit according to any one of claims 1 to 9.