CN215008229U

CN215008229U - Array substrate, display panel and display device

Info

Publication number: CN215008229U
Application number: CN202120602393.9U
Authority: CN
Inventors: 刘泽旭; 高锦成; 钱海蛟; 赵立星; 陈亮; 汪涛; 朱登攀; 陆文涛; 张冠永
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Display Lighting Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Display Lighting Co Ltd
Priority date: 2021-03-22
Filing date: 2021-03-22
Publication date: 2021-12-03
Anticipated expiration: 2031-03-22

Abstract

The application provides an array substrate, a display panel and a display device, which are used for reducing the generation of poor short circuit between a grid electrode and a source electrode and poor short circuit between the source electrode and a common electrode wiring, and improving the product yield. The array substrate includes in a thickness direction: a substrate base plate; the gate line fixing part and the common electrode are made of the same conductive material and are positioned in the same structural layer; the gate line fixing part is used for fixing the gate line on the substrate. The display panel comprises the array substrate. The display device comprises the display panel.

Description

Array substrate, display panel and display device

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a display panel and a display device.

Background

With the development of the daily life of people, the demand of consumers on the picture quality of display products is higher and higher, and various products with high resolution of 8K and high refresh rate of 120Hz are produced. Because high-end product is to the demand of charging rate, need further promote grid yield and performance in order to satisfy the demand of present product, however, because present gate line adopts copper (Cu) material more, in the actual production process, need adopt molybdenum lithium (MoNb) to increase the adhesion of copper (Cu) and glass, prevent that the phenomenon of droing appears in the coating film in-process membrane copper.

At present, the cost of the molybdenum lithium target is high, fine particles are generated in the coating process, and as shown in fig. 1, the fine particles P often cause circuit defects of an array substrate, which cause poor gate-source short circuits or poor source-common electrode routing short circuits, and affect the product yield. The gate semi-permeable membrane exposure process (Half-Tone) can form a film without using a molybdenum-lithium target in the gate film forming process, but the process is difficult to be applied to narrow-frame products due to the problem of product yield. Therefore, for such narrow-frame products, a gate semi-permeable membrane exposure process cannot be adopted to avoid particle defects caused by the molybdenum-lithium target material.

The difference between the final grid size and the exposed grid size is 3.6um-4.2um level because the grid semi-permeable membrane exposure process (Half-Tone) needs two times of etching, and the difference is 1.2um-1.5um level for the common exposure process. As shown in fig. 2, in the gate semi-permeable film exposure process, two etching processes are performed, and redundant portions W of 1.1um to 1.5um appear on two sides of the gate 60', respectively, which results in an excessive size difference. The overall size of the peripheral wiring of the display screen is designed to be 12um-13.4um, and the size is often required to be designed to be 11.4um level when a customer designs a narrow frame required by a product. Due to the fact that the difference value between the final grid size of the grid semi-permeable membrane exposure process and the exposed grid size is too large, the situation that peripheral wiring is broken badly and highly occurs often can be caused, and the yield cannot meet production requirements and customer supply. In view of such circumstances, only the ordinary exposure process can be adopted.

Therefore, how to reduce the short circuit between the gate and the source and the short circuit between the source and the common electrode under the existing process conditions is a technical problem to be solved in the field.

SUMMERY OF THE UTILITY MODEL

The application provides an array substrate, a display panel and a display device, which can reduce the generation of poor short circuit between a grid electrode and a source electrode and poor short circuit between the source electrode and a common electrode wiring, thereby improving the product yield.

According to a first aspect of embodiments of the present application, there is provided an array substrate including, in a thickness direction:

a substrate base plate;

the grid line fixing part and the common electrode are arranged on the substrate and insulated from each other, and the grid line fixing part and the common electrode are made of the same conductive material and are positioned in the same structural layer;

the grid line fixing part is used for fixing the grid line on the substrate, the grid line and the common electrode wire are made of the same material and are positioned in the same structural layer, and the grid line and the common electrode wire are arranged in an insulated mode;

a first insulating layer on the substrate, the first insulating layer overlying the gate line, the common electrode trace, and the common electrode;

the pixel structure comprises a first insulating layer, a second insulating layer and a pixel electrode, wherein the first insulating layer is positioned on the substrate, the second insulating layer is positioned on the first insulating layer, and the pixel electrode is positioned on the second insulating layer.

Optionally, the gate line fixing portion and the common electrode are made of the same metal material.

Optionally, the gate line fixing portion and the common electrode are made of the same transparent conductive material.

Optionally, an orthographic projection of the gate line fixing portion on the substrate base plate completely coincides with an orthographic projection of the gate line on the substrate base plate.

Optionally, the gate line fixing part and the common electrode are made of indium tin oxide; the gate line and the common electrode are made of copper; the pixel electrode is made of a transparent conductive material, and the pixel electrode is made of indium tin oxide.

Optionally, the thickness of the common electrode is the same as that of the gate line fixing part, and the thickness of the common electrode is 0.03um to 0.07 um;

the thickness of the common electrode wire is the same as that of the gate line, and the thickness of the common electrode wire is 0.35-0.60 um;

the thickness of the first insulating layer is 0.35um-0.45 um;

the thickness of the second insulating layer is 0.55um-0.65 um;

the thickness of the pixel electrode is 0.03um-0.07 um.

Optionally, the gate line and the common electrode trace are both of a single-layer metal structure.

Optionally, the array substrate includes a plurality of pixel units, each pixel unit includes a thin film transistor, a pixel electrode, a common electrode, and a common electrode trace, the thin film transistor includes a gate, a source, and a drain, and the gate is a partial structure of the gate line. According to a second aspect of the embodiments of the present application, there is provided a display panel including the array substrate as described above.

According to a third aspect of embodiments of the present application, there is provided a display device including the display panel as described above.

The utility model provides an array substrate, display panel and display device, the gate line is fixed on the substrate base plate through the gate line fixed part with the conducting material that the common electrode is the same to can replace the molybdenum lithium material layer with the gate line fixed part of the conducting material that the common electrode is the same with the adhesion between increase gate line and the substrate base plate, thereby avoid grid and source short circuit bad or source and common electrode to walk the bad condition of line short circuit and produce, thereby improve the product yield.

Drawings

Fig. 1 is a partial actual microscopic view of an array substrate in the prior art.

Fig. 2 is a schematic cross-sectional view of a portion of a prior art array substrate.

Fig. 3 is a schematic top view of a part of an array substrate according to an exemplary embodiment of the present application.

Fig. 4 is a sectional view taken along a-a' direction in fig. 3.

Fig. 5 is a sectional view taken along the direction B-B' in fig. 3.

Fig. 6 is a flowchart of a method for manufacturing an array substrate according to an exemplary embodiment of the present application.

Fig. 7 to 10 are process step diagrams of a method for manufacturing an array substrate according to an exemplary embodiment of the present application.

Fig. 11 is a partial actual microscopic view of an array substrate according to an exemplary embodiment of the present application.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus consistent with certain aspects of the present application, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The use of the terms "a" or "an" and the like in the description and in the claims of this application do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "plurality" includes two, and is equivalent to at least two. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The embodiment provides an array substrate, a display panel and a display device.

As shown in fig. 3 to 5, the array substrate 1 includes a plurality of pixel units 10, and each pixel unit 10 may include a thin film transistor including a gate electrode 21, a source electrode 23, and a drain electrode 22, a pixel electrode 70, a common electrode 30, and a common electrode trace 50, where the gate electrode 21 is a partial structure of the gate line 60. The thin film transistor further includes an active layer 24, and the source and

drain electrodes

23 and 22 are located on the active layer 24. The source electrode 23 is connected to the pixel electrode 70, and the source electrode 23 and the drain electrode 22 may be switched with each other. The gate electrode 21 and the source electrode 23 are simultaneously energized to make the active layer 24 conductive, and after the active layer 24 is turned on, the source electrode 23 energizes the gate electrode 21 to complete the charging process for the pixel through the gate electrode 21. In fig. 1, a1 denotes a thin film transistor device region, and a portion of the gate line 60 in the region a1 constitutes the gate electrode 21 of the thin film transistor, i.e., the gate electrode 21 is a partial structure of the gate line 60.

The array substrate 1 includes in the thickness direction T: a base substrate 80; a gate line fixing part 40 and a common electrode 30 which are disposed on the base substrate 80 and insulated from each other, the gate line fixing part 40 and the common electrode 30 being made of the same conductive material and being located in the same structural layer; the gate line fixing part 40 is used for fixing the gate line 60 on the substrate base plate 80, the gate line 60 and the common electrode wire 50 are made of the same material and are located in the same structural layer, and the gate line 60 and the common electrode wire 50 are arranged in an insulated mode; a first insulating layer 81 disposed on the substrate 80, wherein the first insulating layer 81 covers the gate line 60, the common electrode trace 50 and the common electrode 30; an active layer 24 on the first insulating layer 81, and source and drain

electrodes

23 and 22 on the active layer 24; a second insulating layer 83 on the first insulating layer 81, the second insulating layer 83 overlying the active layer 24 and the source and drain

electrodes

23 and 22; and a pixel electrode 70 on the second insulating layer 83. The first insulating layer 81 is a gate electrode 21 insulating layer, and the second insulating layer 83 is a passivation layer.

In this way, the gate line 60 is fixed on the substrate 80 through the gate line fixing portion 40 of the same conductive material as the common electrode 30, so that the molybdenum-lithium material layer can be replaced by the gate line fixing portion 40 of the same conductive material as the common electrode 30 to increase the adhesion between the gate line 60 and the substrate 80, thereby avoiding the occurrence of the short circuit failure between the gate electrode 21 and the source electrode 23 or the short circuit failure between the source electrode 23 and the common electrode trace 50, and improving the product yield.

The orthographic projection of the gate line fixing part 40 on the substrate 80 is completely overlapped with the orthographic projection of the gate line 60 on the substrate 80, so that the gate line fixing part 40 is ensured not to influence the size of the gate line 60, and the beneficial effect of accurately controlling the size of the gate line 60 is achieved; in addition, the gate line fixing portion 40 is disposed below the gate line 60, and the gate line fixing portion 40 can fix the gate line 60 and also provide a complete supporting function for the gate line 60, so that the problem of bottom fracture of the first insulating layer due to absence of the gate line fixing portion 40 at a partial position (particularly at an edge) below the gate line 60 is solved.

In the present embodiment, the gate line fixing portion 40 and the common electrode 30 are made of the same transparent conductive material, and specifically, the gate line fixing portion 40 and the common electrode 30 are made of Indium Tin Oxide (hereinafter, referred to as Indium Tin Oxide), but the present invention is not limited thereto, and may also be made of a transparent conductive material such as graphene. The material of the gate line 60 and the common electrode 30 may generally be a metal material (e.g., copper, aluminum, etc.). The pixel electrode 70 is made of a transparent conductive material, specifically, the pixel electrode 70 is made of Indium tin Oxide (ito), but is not limited thereto, and may also be Indium gallium Zinc Oxide (izo), Indium gallium tin Oxide (izo), or the like.

In other embodiments, the material of the gate line fixing part 40 and the common electrode 30 may also be the same metal material. But not limited thereto, the material of the gate line fixing portion 40 and the common electrode 30 may be other material that can achieve conductivity.

Optionally, the thickness of the common electrode 30 is the same as that of the gate line fixing portion 40, the thickness of the common electrode 30 is 0.03um to 0.07um, and preferably, the thickness of the common electrode 30 is 0.04 um.

The thickness of the common electrode wire 50 is the same as that of the gate line 60, and the thickness of the common electrode wire 50 is 0.35um to 0.60 um; the common electrode trace 50 and the gate line 60 preferably have a thickness of 0.45um for the sake of transmittance and manufacturing cost.

The thickness of the first insulating layer 81 is 0.35um-0.45um, and preferably, the thickness of the first insulating layer 81 is 0.40 um.

The thickness of the second insulating layer 83 is 0.55um-0.65um, and preferably, the thickness of the second insulating layer 83 is 0.60 um.

The thickness of the pixel electrode 70 is 0.03um to 0.07 um; the thickness of the pixel electrode 70 is preferably 0.04um in view of transmittance and manufacturing cost.

The gate line 60 and the common electrode trace 50 are each a single-layer metal structure.

The gate line fixing part 40 and the common electrode 30 are of the same layer structure formed by the same mask. That is, the gate line fixing part 40 and the common electrode 30 are formed in the same process step to improve the production efficiency.

The gate line 60 and the common electrode trace 50 are formed in the same layer structure through the same mask. I.e., the gate lines 60 and the common electrode wire 50 are formed in the same process step to improve the production efficiency.

The first insulating layer 81 is formed by a PECVD (Plasma Enhanced Chemical Vapor Deposition, which refers to a Vapor Deposition method of Plasma Enhanced chemistry) process at a temperature of 350 to 370 ℃. The crystallization process of the common electrode 30 and the gate line fixing portion 40 is completed in the process of forming the first insulating layer 81 by the PECVD process.

This is because, in the prior art, the original manufacturing process flow is that after the first conductive layer is formed, the first conductive layer is patterned to form the common electrode 30, then the second conductive layer is formed, and then the second conductive layer is patterned to form the gate line 60 and the common electrode trace 50. After the patterning of the first conductive layer is completed, a crystallization process (annealing process) is performed to reduce the resistance of the common electrode 30, and the temperature of the crystallization process is usually 220 to 240 ℃. In the present embodiment, the common electrode 30 may be crystallized at a high temperature during the formation of the first insulating layer 81, thereby simplifying the process flow. That is, compared with the prior art, the annealing process after the patterning of the first conductive layer can be omitted in the embodiment, thereby simplifying the process flow.

The temperature of the PECVD process is 350-370 ℃, and preferably, the temperature of the PECVD process is 360 ℃.

The embodiment also provides a display panel. The display panel comprises the array substrate 1.

The embodiment also provides a display device. The display device comprises the display panel.

Fig. 6 is a flowchart of a method for manufacturing an array substrate according to the present embodiment. As shown in fig. 6, the manufacturing method includes the following steps:

step 100: forming a first conductive layer on a substrate;

step 200: forming a second conductive layer on the first conductive layer;

step 300: patterning the second conductive layer to form a gate line and a common electrode wire, wherein the common electrode wire and the gate line are arranged in an insulated mode;

step 400: patterning the first conductive layer to form a common electrode and a gate line fixing part located below the gate line, wherein the gate line fixing part is used for fixing the gate line on the substrate, the common electrode part is located below the common electrode routing, and the common electrode and the gate line fixing part are arranged in an insulated mode;

step 500: forming a first insulating layer on the substrate, wherein the first insulating layer covers the gate line, the common electrode trace and the common electrode;

step 600: forming a second insulating layer on the first insulating layer;

step 700: and forming a pixel electrode on the second insulating layer.

In the manufacturing method of the array substrate provided by this embodiment, on one hand, the gate line is fixed on the substrate through the gate line fixing portion made of the same conductive material as the common electrode, so that the molybdenum-lithium material layer can be replaced by the gate line fixing portion made of the same conductive material as the common electrode to increase the adhesion between the gate line and the substrate, thereby avoiding the occurrence of poor gate-source short circuit or poor source-common electrode routing short circuit, and improving the product yield.

On the other hand, in the prior art, the conventional preparation process flow includes, after the first conductive layer is formed, patterning the first conductive layer to form the common electrode, then forming the second conductive layer, and then patterning the second conductive layer to form the gate line and the common electrode wiring. In the embodiment, the first conducting layer and the second conducting layer are sequentially formed, then the second conducting layer is patterned to form the gate line and the common electrode wiring, and the first conducting layer is patterned to form the common electrode and the gate line fixing part, so that the usage amount of the molybdenum-lithium target material can be reduced and the production cost of the product can be reduced only by changing the process flow without changing a new mask on the original equipment.

In addition, unlike the exposure process of the gate semi-permeable film for forming the gate line mentioned in the background art, which requires two times of etching, the embodiment only performs one time of etching when the gate line is patterned, so that the unwanted portion beside the gate and the undesirable problem of the increase of parasitic capacitance do not occur.

It should be noted that, when patterning the second conductive layer, the second conductive layer is patterned by using the patterned gate line as a mask to form a gate line fixing portion located below the gate line in this embodiment.

If the preparation method of patterning the first conductive layer and then patterning the second conductive layer is adopted, a mask plate for forming a fixed part of the common electrode and the gate line needs to be changed, thereby increasing the cost. If a modified mask is adopted, after the public electrode and the grid line fixing part are firstly prepared in a patterning mode, in the process of preparing the grid line in a patterning mode, due to the limitation of the alignment accuracy of the exposure process, the situation that the graph of the grid line and the graph of the grid line fixing part are staggered by 2-3 microns can occur, and the risk that the bottom of the first insulating layer is broken exists; in the embodiment, the patterned gate line is used as the mask to pattern the second conductive layer to form the gate line fixing portion located below the gate line, so that the situation that the pattern of the gate line and the pattern of the gate line fixing portion are staggered is avoided, and the risk can be well avoided.

Specifically, as shown in fig. 7 to 10, the semiconductor packaging method of the present embodiment includes:

in step 100, as shown in fig. 7, a first conductive layer 91 is formed on the base substrate 80, and the material of the first conductive layer 91 is a conductive material. The first conductive layer 91 may be formed on the substrate base plate 80 by a deposition or sputtering process or the like.

The materials of the gate line fixing part 40 and the common electrode 30 are the same transparent conductive material, and specifically, the materials of the gate line fixing part 40 and the common electrode 30 may include, but are not limited to: indium Tin Oxide (Indium Tin Oxide), graphene, and the like.

Preferably, in forming the first conductive layer 91 on the base substrate 80, the first conductive layer 91 is formed by rotating a target. Thus, the uniformity of film formation is better because of the rotary target material.

In step 200, as shown in fig. 8, a second conductive layer 92 is formed on the first conductive layer 91. The second conductive layer 92 may be formed on the first conductive layer 91 by a deposition or sputtering process.

In the embodiment, the structure of the second conductive layer 92 is a single-layer metal structure, and in forming the second conductive layer 92 on the first conductive layer 91, the second conductive layer 92 is formed by using a multi-cavity coating apparatus, and each cavity forms a layer structure with a partial thickness in the single-layer metal structure, so as to reduce the risk of chipping the substrate 80 and improve the yield of products.

This is because, in the prior art, the gate line and the common electrode trace have a multi-layer structure, that is, a molybdenum lithium metal material layer and a copper metal material layer are sequentially stacked in a direction from close to the substrate to far from the substrate along the thickness direction T, that is, the second conductive layer in the prior art includes the molybdenum lithium metal material layer and the copper metal material layer. When the second conducting layer is formed, the second conducting layer is formed by adopting a multi-cavity coating device, the multi-cavity coating device is generally divided into two to three cavity coating films, and a molybdenum-lithium metal material layer is arranged in the second conducting layer, so that the molybdenum-lithium metal material layer needs to occupy one cavity of the multi-cavity coating device for coating, the copper metal material layer is coated in the rest cavity, the thickness of the single-cavity coating film is too high, and the material of the substrate below the molybdenum-lithium metal material layer is glass, so that the substrate is easily broken, and the yield of products is influenced.

In this embodiment, the second conductive layer 92 is a single-layer metal structure (copper metal), so that all cavities of the multi-cavity coating device are coated with copper films, that is, each cavity forms a layer structure with a partial thickness in the single-layer metal structure, and the thickness of the film layer in each cavity is reduced, thereby reducing the risk of fragments of the substrate 80 and improving the yield of products.

In step 300, as shown in fig. 9, the second conductive layer 92 is patterned to form a gate line 60 and a common electrode trace 50, and the common electrode trace 50 and the gate line 60 are insulated from each other.

Specifically, the gate line 60 and the common electrode wire 50 are formed through process steps of coating photoresist, exposing, developing, etching, and stripping the photoresist.

In patterning the second conductive layer 92 to form the gate line 60 and the common electrode trace 50, an etching solution having a high selectivity ratio for the second conductive layer 92 is used for etching. It should be noted that the selectivity refers to the etching selectivity, and the etching selectivity refers to the relative etching rate of one material to another material under the same etching condition. Which is defined as the ratio of the etch rate of the material being etched to the etch rate of another material. The etching liquid having a high selection ratio for the second conductive layer 92 means that the etching liquid has a high ratio of the etching rate for the film layer to be etched (the second conductive layer 92) to the etching rate for the film layers not to be etched (the first conductive layer 91 and the other film layers).

Specifically, the high selection ratio herein refers to an etching selection ratio of 100 to 1 or more, that is, the etching rate of the film to be etched is 100 times higher than that of the film not to be etched, so that the film to be etched can be etched in a targeted manner, and the influence on the film not to be etched is reduced. Since the first conductive layer 91 is exposed in the process of etching the gate line 60 and the common electrode trace 50, the second conductive layer 92 is etched by the etching solution with a high selectivity ratio, so that the influence on the first conductive layer 91 and other film layers in the etching process can be avoided.

In the present embodiment, the gate line 60 and the common electrode trace 50 are formed using the same mask.

In step 400, as shown in fig. 10, the first conductive layer 91 is patterned to form a common electrode 30 and a gate line fixing portion 40 located below the gate line 60, the gate line fixing portion 40 is used to fix the gate line 60 on the substrate 80, the common electrode 30 is partially located below the common electrode trace 50, and the common electrode 30 and the gate line fixing portion 40 are insulated from each other.

Specifically, the common electrode 30 and the gate line fixing part 40 are formed through process steps of coating photoresist, exposing, developing, etching, and stripping the photoresist.

In patterning the first conductive layer 91 to form the common electrode 30 and the gate line fixing portion 40 located below the gate line 60, etching is performed using an etching liquid having a high selection ratio for the first conductive layer 91. Here, the high selection ratio also means a selection ratio of 100 to 1 or more. The related concepts regarding high selection ratio have been explained above and will not be reiterated here.

The first conductive layer 91 is etched by the etching liquid with the high selection ratio, so that the influence on the first conductive layer 91 and other film layers can be avoided in the etching process.

In the present embodiment, the common electrode 30 and the gate line fixing portion 40 under the gate line 60 are formed by patterning the first conductive layer 91 using the same mask.

When the first conductive layer 91 is patterned, the gate line 60 blocks the first conductive layer 91 below the gate line 60, so that the orthographic projection of the gate line fixing part 40 on the substrate 80 can be completely overlapped with the orthographic projection of the gate line 60 on the substrate 80, the size of the gate line 60 can not be influenced by the gate line fixing part 40, and the beneficial effect of accurately controlling the size of the gate line 60 is achieved; in addition, the gate line fixing portion 40 is disposed below the gate line 60, and the gate line fixing portion 40 can fix the gate line 60 and also provide a complete supporting function for the gate line 60, so that the problem of bottom fracture of the first insulating layer due to absence of the gate line fixing portion 40 at a partial position (particularly at an edge) below the gate line 60 is solved.

In step 500, a first insulating layer 81 is formed on the substrate 80, and the first insulating layer 81 covers the gate lines 60, the common electrode traces 50 and the common electrodes 30.

In forming the first insulating layer 81 on the base substrate 80, the first insulating layer 81 is formed by a PECVD process at a temperature of 350 to 370 ℃. The crystallization process of the common electrode 30 and the gate line fixing portion 40 is completed in the process of forming the first insulating layer 81 by the PECVD process.

As described above, in the prior art, after the first conductive layer 91 is formed, the first conductive layer 91 is patterned to form the common electrode 30, then the second conductive layer 92 is formed, and then the second conductive layer 92 is patterned to form the gate line 60 and the common electrode trace 50. After the patterning of the first conductive layer 91 is completed, a crystallization process (annealing process) is performed to reduce the resistance of the common electrode 30, and the temperature of the crystallization process is usually 220 to 240 ℃. In the present embodiment, the common electrode 30 may be crystallized at a high temperature during the formation of the first insulating layer 81, thereby simplifying the process flow. That is, compared with the prior art, the annealing process after the patterning of the first conductive layer can be omitted in the embodiment, thereby simplifying the process flow.

Before entering step 600, the method further includes forming an active layer 24 on the first insulating layer 81, and forming a source electrode 23 and a drain electrode 22 on the active layer 24.

In step 600, a second insulating layer 83 is formed on the first insulating layer 81, and the second insulating layer 83 covers the active layer 24 and the source and drain

electrodes

23 and 22.

In step 700, a pixel electrode 70 is formed on the second insulating layer 83, and the pixel electrode 70 is connected to the drain electrode 22 through a via hole.

The array substrate of the embodiment is manufactured by the manufacturing method. The actual microscopic view of the array substrate 1 manufactured by the above manufacturing method is shown in fig. 11, and it can be seen that there are no fine particles on the actual microscopic view of the array substrate 1 because the mo-li material layer is avoided.

The defect rate of short circuit between the grid electrode and the source electrode or between the source electrode and the common electrode wiring of the array substrate manufactured by the manufacturing method of the embodiment is improved, and the defect rate is specifically shown in the following table:

as can be seen from the above table, the short-circuit defect rate of the gate and the source is reduced by 0.02%, and the short-circuit defect rate of the source and the common electrode trace is reduced by 0.27%, so that the short-circuit defect rate of the gate and the source or the short-circuit defect rate of the source and the common electrode trace of the array substrate is improved.

The manufacturing method in the embodiment can be applied to a production line which needs to use photoresist to manufacture an exposure mask plate in the OLED manufacturing industry and the like.

The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

Claims

1. An array substrate, comprising in a thickness direction:

a substrate base plate;

2. The array substrate of claim 1, wherein the gate line fixing portion and the common electrode are made of the same metal material.

3. The array substrate of claim 1, wherein the gate line fixing portion and the common electrode are made of the same transparent conductive material.

4. The array substrate of claim 1, wherein an orthographic projection of the gate line fixing portion on the base substrate is completely coincident with an orthographic projection of the gate line on the base substrate.

5. The array substrate of claim 1, wherein the gate line fixing portion and the common electrode are made of indium tin oxide; the gate line and the common electrode are made of copper; the pixel electrode is made of a transparent conductive material, and the pixel electrode is made of indium tin oxide.

6. The array substrate of claim 1,

the thickness of the public electrode is the same as that of the gate line fixing part, and the thickness of the public electrode is 0.03-0.07 um as that of the gate line fixing part;

the thickness of the first insulating layer is 0.35um-0.45 um;

the thickness of the second insulating layer is 0.55um-0.65 um;

the thickness of the pixel electrode is 0.03um-0.07 um.

7. The array substrate of claim 1, wherein the gate line and the common electrode trace are both a single-layer metal structure.

8. The array substrate according to any one of claims 1 to 7, wherein the array substrate comprises a plurality of pixel units, each pixel unit comprises a thin film transistor, a pixel electrode, a common electrode and a common electrode trace, the thin film transistor comprises a gate electrode, a source electrode and a drain electrode, and the gate electrode is a partial structure of the gate line.

9. A display panel comprising the array substrate according to any one of claims 1 to 8.

10. A display device characterized by comprising the display panel according to claim 9.