CN214849398U - Interface circuit of electric connector - Google Patents
Interface circuit of electric connector Download PDFInfo
- Publication number
- CN214849398U CN214849398U CN202120594306.XU CN202120594306U CN214849398U CN 214849398 U CN214849398 U CN 214849398U CN 202120594306 U CN202120594306 U CN 202120594306U CN 214849398 U CN214849398 U CN 214849398U
- Authority
- CN
- China
- Prior art keywords
- connector
- interface
- circuit
- state
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Details Of Connecting Devices For Male And Female Coupling (AREA)
Abstract
The embodiment of the utility model discloses electric connector interface circuit, interface circuit is including being used for with the first connector of first type interface electricity connection, being used for with second type interface electricity connection's second connector, state output winding displacement, be used for detecting the first detection circuitry of first connector interface state and being used for detecting the anti-cluster circuit that prevents of second connector interface state from this, the detection of electric connector's interface state when realizing different grade type interface connection improves the interface and inserts the commonality of detection method, reduces and inserts the detection cost.
Description
Technical Field
The utility model relates to an electronic equipment technical field, concretely relates to electric connector interface circuit.
Background
With the increasing use requirements of various electronic devices, the insertion state detection for the universal interface has become a common design requirement.
However, because the types of the existing universal interfaces are various, the specific structures of the interfaces are also greatly different, and when the insertion detection is carried out, a detection circuit corresponds to one type of interface, so that the universality is poor, and the use cost is high.
SUMMERY OF THE UTILITY MODEL
In view of this, the embodiment of the present invention provides an electrical connector interface circuit to detect the interface state of the electrical connector when different types of interfaces are connected, improve the universality of the interface insertion detection method, and reduce the insertion detection cost.
An embodiment of the utility model provides an electric connector interface circuit, interface circuit includes:
the first connector is used for being electrically connected with the first type interface;
a second connector for electrically connecting with a second type interface;
a state output flat cable;
the first detection circuit is connected between the first connector and the state output flat cable, and is used for detecting the interface state of the first connector and sending the interface state of the first connector to the state output flat cable;
and the anti-reverse-serial circuit is connected between the second connector and the state output flat cable, is used for detecting the interface state of the second connector and sending the interface state of the second connector to the state output flat cable.
Further, the first Type interface is an OTG line interface with a Type-C structure.
Further, the second type interface is an OTG line interface with a micro USB structure.
Further, the first detection circuit outputs a low level signal to the status output flat cable when the first connector is electrically connected with the first type interface.
Further, the anti-reverse-serial circuit outputs a low-level signal to the state output flat cable when the second connector is connected with the second type interface.
Further, the anti-deserializing circuit includes:
and the anode of the diode is connected with the first detection circuit, and the cathode of the diode is connected with the second connector.
Further, the first connector has a first configuration pin and a second configuration pin, and the voltages of the first configuration pin and the second configuration pin are changed according to the cable connection state of the first connector;
the first detection circuit includes:
the grid electrode of the field effect transistor is connected with a first voltage end through a first resistor, the source electrode of the field effect transistor is connected with a grounding end, and the drain electrode of the field effect transistor is connected with the first voltage end through a second resistor;
the base electrode of the bipolar transistor is connected with the drain electrode of the field effect transistor, the collector electrode of the bipolar transistor is connected with a second voltage end through a third resistor, and the emitter electrode of the bipolar transistor is connected with the ground end;
the fourth resistor is connected between the grid of the field effect transistor and the second configuration pin;
the fifth resistor is connected between the grid of the field effect transistor and the first configuration pin;
and the capacitor is connected between the grid of the field effect transistor and the grounding terminal.
Further, the field effect transistor is an N-channel MOS transistor.
Further, the second connector has an identification pin, and the anti-reverse-string circuit includes:
and the anode of the diode is connected with the collector of the bipolar transistor, and the cathode of the diode is connected with the identification pin.
Further, the interface circuit further includes:
and the processor is connected with the state output flat cable and used for determining the interface state of the electric connector.
The utility model discloses technical scheme detects the interface state of first connector through first detection circuitry, prevent the interface state of anti-reverse string circuit detection second connector, and the interface state that first connector of state output winding displacement output and second connector detected, and then confirm the interface state of electric connector, the detection of electric connector interface state when realizing that first type interface and second connector are connected to first connector, improve the commonality that inserts the detection method, reduce the use cost who inserts the detection.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a schematic diagram of an electrical connector interface circuit;
fig. 2 is a circuit diagram of an electrical connector interface circuit.
In the figure, 1, an electrical connector interface circuit; 11. a first connector; 12. a second connector; 13. a first detection circuit; 14. an anti-reverse-string circuit; 15. a state output flat cable; 16. a processor; 2. a first type interface; 3. a second type of interface.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout the description, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
When the existing universal interface is used for insertion detection, a detection circuit is generally corresponding to one type of interface, so that the universality is poor and the use cost is high. Based on this, the embodiment of the utility model provides an electric connector interface circuit to use the insertion detection of compatible Type-C interface and micro USB interface simultaneously as the example, introduce electric connector interface circuit.
Fig. 1 is a schematic diagram of an electrical connector interface circuit. As shown in fig. 1, the electrical connector interface circuit 1 of the present embodiment includes a first connector 11, a second connector 12, a first detection circuit 13, an anti-reverse-serial circuit 14, and a status output flat cable 15. Wherein the first connector 11 is adapted to be electrically connected to the first type interface 2. The second connector 12 is for electrical connection with the second type interface 3. The first detection circuit 13 is connected between the first connector 11 and the status output cable 15, and is configured to detect the interface status of the first connector 11 and send the interface status of the first connector 11 to the status output cable 15. The anti-deserializing circuit 14 is connected between the second connector 12 and the status output flat cable 15, and is configured to detect the interface status of the second connector 12 and send the interface status of the second connector 12 to the status output flat cable 15.
According to the technical scheme, the interface state of the first connector is detected through the first detection circuit, the anti-reverse-serial circuit detects the interface state of the second connector, the interface states detected by the first connector and the second connector are output through the state output flat cable, the interface state of the electric connector is further determined, the detection of the interface states of the electric connector when different types of interfaces are inserted into the electric connector is achieved, the universality of the insertion detection method is improved, and the use cost of the insertion detection is reduced.
Optionally, the first Type interface in this embodiment is an OTG line interface of a Type-C structure. The second type interface is an OTG line interface with a micro USB structure. The OTG line is a cable for connecting different peripheral equipment or mobile equipment. Compared with the traditional USB technology, the OTG line has the function of realizing data transmission between different mobile devices under the condition of no computer. For example: the mobile phone is connected with USB equipment such as a U disk through an OTG line, so that the mobile phone can directly access the content in the U disk.
Optionally, the first detection circuit of this embodiment outputs a low-level output signal to the status output flat cable when the first connector is electrically connected to the first type interface. Therefore, the electric connector interface circuit detects the interface state of the first connector by judging the level of the output signal.
Optionally, the interface circuit in this embodiment further includes a processor, and the processor is connected to the status output cable and configured to determine the interface status of the electrical connector. When the detection circuit is used, output signals output by the first detection circuit and the anti-reverse-serial circuit are transmitted to the processor through the state output flat cable, and the processor determines the interface state of the electric connector according to the level of the output signals, so that the insertion detection of different types of interfaces is realized.
Further, the first detection circuit of this embodiment outputs a low level signal to the status output flat cable when the first connector is connected to the OTG line interface of the Type-C structure, and outputs a high level signal to the status output flat cable when the first connector is not connected to the OTG line interface of the Type-C structure or is connected to a non-OTG line interface. Therefore, when the first connector is inserted into the OTG line interface with the Type-C structure, the detection of the electric connector interface circuit on the electric connector interface state is realized.
Optionally, the anti-deserializing circuit of this embodiment outputs a low level signal to the status output flat cable when the second connector is connected to the second type interface, and sends the low level signal to the processor through the status output flat cable. Therefore, the processor judges the level of the received signal to realize the detection of the interface state of the second connector by the electric connector interface circuit.
Further, the anti-reverse-serial circuit of this embodiment outputs a low level signal to the status output flat cable when the second connector is connected with the OTG line interface of the micro USB structure, and outputs a high level signal to the status output flat cable when the OTG line interface of the micro USB structure is not connected or the non-OTG line interface is connected. Therefore, when the second connector interface state is inserted into the OTG line interface with the micro USB structure, the detection of the electric connector interface state by the electric connector interface circuit is realized.
It should be understood that, in this embodiment, a state output flat cable may also be omitted, and the first detection circuit and the anti-reverse-serial circuit are simultaneously connected to the processor, so that signals output by the first detection circuit and the anti-reverse-serial circuit are directly sent to the processor, and the level of the output signals of the first detection circuit and the second detection circuit is determined by the processor, thereby implementing insertion detection of different types of interfaces.
According to the technical scheme, the output signals of the first detection circuit and the anti-reverse-serial circuit are transmitted to the processor, and the interface states of the first connector and the second connector on the electric connector are determined by determining the level of the received signal through the processor, so that the state detection of different types of interfaces during insertion is realized while the original design of the electric connector is not changed, the universality of the insertion detection method is improved, and the use cost of the insertion detection of different types of interfaces is reduced.
Fig. 2 is a circuit diagram of an electrical connector interface circuit. As shown in fig. 2, in the interface circuit of the electrical connector, the first connector 11 adopts a standard Type-C interface structure for accessing an OTG line with a Type-C structure. Wherein the first connector 11 is configured with pins A1-A12, pins B1-B12, pins 1-2, and pins 5-8. Pins A1 and A12, pins B1 and B12, and pins 1-2 and 5-8 are all connected to ground, and pins A4 and A9, and pins B4 and B9 are all connected to the power supply VBUS. In addition, the pin a5 and the pin B5 in the first connector 11 are both configuration pins. The pin a5 is a first configuration pin, the pin B5 is a second configuration pin, and the voltages of the pin a5 and the pin B5 are both changed according to the cable connection status of the first electrical connector 11. When the first connector 11 is connected with an OTG line with a Type-C structure, the configuration pin of the first connector 11 is in a low level state; when an OTG line or a non-OTG line of a non-Type-C structure is connected, the configuration pin of the first connector 11 is in a high level state. Specifically, when the OTG line of the Type-C structure is inserted into the first connector 11 in the first direction, it assumes a low state through the pin a 5. When the OTG line of the Type-C structure is inserted into the first connector 11 in the second direction, the pin B5 assumes a low state.
As shown in fig. 2, the second connector 12 is a standard micro USB interface structure, and is used for accessing an OTG line interface of the micro USB structure. Wherein the second connector 12 is provided with pins 1-11. Pin 1 is connected to the power supply source VBUS. Pin 2 is connected to both pins a7 and B7 in the first connector 11. Pin 3 is connected to both pins a6 and B6 of the first connector 11. Pin 4 is configured as an identification pin, connects an anti-deserializing circuit, and outputs a signal USB _ ID. Pin 5 and pins 6-11 are connected to ground. At the time of detection, the identification pin 4 is in a low level state when the OTG line of the micro USB structure is connected to the second connector 12. When the second connector 12 is connected with an OTG line or a non-OTG line of a non-micro USB structure, the identification pin 4 is in a high level state.
Alternatively, as shown in fig. 2, the first detection circuit 13 in the present embodiment includes a field effect transistor Q2, a bipolar transistor Q1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a capacitor C. The gate g of the fet is connected to the first voltage terminal through the first resistor R1, the source s is connected to the ground terminal, and the drain d is connected to the first voltage terminal through the second resistor R2. The base b of the bipolar transistor Q1 is connected to the drain d of the fet Q2, the collector c is connected to the second voltage terminal through the third resistor R3, and the emitter collector e is connected to the ground terminal. The fourth resistor R4 is connected between the gate g of the fet Q2 and the second configuration pin B5. The fifth resistor R5 is connected between the gate g of the fet Q2 and the first configuration pin a 5. The capacitor C is connected between the gate g of the fet Q2 and ground.
Further, the field effect transistor Q2 in this embodiment is an N-channel MOS transistor connected with the diode D2, the anode of the diode D2 is connected to the source s of the MOS transistor, and the cathode of the diode D2 is connected to the drain D of the MOS transistor. The voltage of the first voltage end is 3.3V, and the voltage of the second voltage end is 1.8V.
When the OTG line with the Type-C structure is not inserted into the first connector 11 or the non-OTG line is inserted into the first connector 11, the pin a5 and the pin B5 in the first connector 11 are in a high level state, the MOS transistor in the first detection circuit 13 is turned on, and the bipolar transistor Q1 is turned off to output a high level output signal USB _ ID.
When the OTG line of Type-C structure is inserted into the first connector 11, the pin a5 and the pin B5 in the first connector 11 are pulled to a low level state by the pull-down resistor in the OTG line, the MOS transistor in the first detection circuit 13 is turned off, and the bipolar transistor Q1 is turned on, and outputs a low level output signal USB _ ID.
When the OTG line of the micro USB structure is inserted into the second connector 12, the pin ID in the second connector 12 is grounded, and the diode D1 is turned on. At this time, the anti-deserializing circuit outputs the output signal USB _ ID of the low level.
When the OTG line of the micro USB structure is not inserted into the second connector 11 or the non-OTG line is inserted into the second connector 11, the pin ID of the second connector 12 is in a floating state, the diode D1 maintains an off state, and the existence of the anti-reverse-series circuit maintains the first detection circuit 13 to output the high-level output signal USB _ ID.
Optionally, the output signal USB _ ID in this embodiment may be transmitted to the processor through a status output cable, so that the processor determines that the OTG line with the Type-C structure is inserted in the first connector or the OTG line with the micro USB structure is inserted in the second connector when receiving the low-level signal USB _ ID. The output signal USB _ ID may also be transmitted to the inside of the processor through a pin by providing the pin on the processor, so that the processor detects the insertion state in the first connector and the second connector.
The utility model discloses technical scheme uses through the cooperation of first detection circuitry with prevent anti-string circuit for output low level's output signal USB _ ID when first connector inserts the OTG line of Type-C structure or the OTG line of second connector access micro USB structure, output high level's output signal USB _ ID when the OTG line or the person who does not insert Type-C structure of first connector inserts non-OTG line, output high level's output signal USB _ ID when the OTG line or the person who does not insert micro USB structure of second connector inserts non-OTG line. Therefore, the processor determines the interface use state of the electric connector according to the level high-low state of the received signal USB _ ID, so that the state detection when the electric connector is inserted into different types of interfaces is realized, the universality of the insertion detection method is improved, and the use cost of the insertion detection is reduced.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included within the protection scope of the present invention.
Claims (10)
1. An electrical connector interface circuit, the interface circuit comprising:
the first connector is used for being electrically connected with the first type interface;
a second connector for electrically connecting with a second type interface;
a state output flat cable;
the first detection circuit is connected between the first connector and the state output flat cable, and is used for detecting the interface state of the first connector and sending the interface state of the first connector to the state output flat cable;
and the anti-reverse-serial circuit is connected between the second connector and the state output flat cable, is used for detecting the interface state of the second connector and sending the interface state of the second connector to the state output flat cable.
2. The interface circuit of claim 1, wherein the first Type interface is an OTG line interface of a Type-C structure.
3. Interface circuit according to claim 1, characterized in that the second type interface is a micro USB structured OTG line interface.
4. The interface circuit of claim 1, wherein the first detection circuit outputs a low level signal to a status output cable when the first connector is electrically connected to the first type of interface.
5. The interface circuit according to claim 1, wherein the anti-deserializing circuit outputs a low-level signal to a status output bus when the second connector is connected with the second type of interface.
6. The interface circuit of claim 1, wherein the anti-deserialization circuit comprises:
and the anode of the diode is connected with the first detection circuit, and the cathode of the diode is connected with the second connector.
7. The interface circuit according to claim 1, wherein the first connector has a first configuration pin and a second configuration pin, and voltages of the first configuration pin and the second configuration pin vary according to a cable connection state of the first connector;
the first detection circuit includes:
the grid electrode of the field effect transistor is connected with a first voltage end through a first resistor, the source electrode of the field effect transistor is connected with a grounding end, and the drain electrode of the field effect transistor is connected with the first voltage end through a second resistor;
the base electrode of the bipolar transistor is connected with the drain electrode of the field effect transistor, the collector electrode of the bipolar transistor is connected with a second voltage end through a third resistor, and the emitter electrode of the bipolar transistor is connected with the ground end;
the fourth resistor is connected between the grid of the field effect transistor and the second configuration pin;
the fifth resistor is connected between the grid of the field effect transistor and the first configuration pin;
and the capacitor is connected between the grid of the field effect transistor and the grounding terminal.
8. The interface circuit of claim 7, wherein the field effect transistor is an N-channel type MOS transistor.
9. The interface circuit of claim 7, wherein the second connector has an identification pin, the anti-deserialization circuit comprising:
and the anode of the diode is connected with the collector of the bipolar transistor, and the cathode of the diode is connected with the identification pin.
10. The interface circuit of claim 1, wherein the interface circuit further comprises:
and the processor is connected with the state output flat cable and used for determining the interface state of the electric connector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120594306.XU CN214849398U (en) | 2021-03-23 | 2021-03-23 | Interface circuit of electric connector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120594306.XU CN214849398U (en) | 2021-03-23 | 2021-03-23 | Interface circuit of electric connector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214849398U true CN214849398U (en) | 2021-11-23 |
Family
ID=78759645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120594306.XU Active CN214849398U (en) | 2021-03-23 | 2021-03-23 | Interface circuit of electric connector |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN214849398U (en) |
-
2021
- 2021-03-23 CN CN202120594306.XU patent/CN214849398U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100495377C (en) | Method for inspecting type of connected peripheral apparatus and terminal interface | |
| CN103064489B (en) | A kind of method and terminal of carrying out internal circuit selection according to USB interface state | |
| US20040230733A1 (en) | Interface for peripheral device detection | |
| US10241935B2 (en) | Portable device, cable assembly, and USB system | |
| US10658860B2 (en) | Electronic device, charger within the electronic device, and detecting method for detecting abnormal status of connector of electronic device | |
| US20070278999A1 (en) | USB mini B power supply system for quickly charging USB mini B devices | |
| US8886852B2 (en) | Techniques for achieving complete interoperability between different types of data and multimedia interfaces in handheld devices | |
| CN101102119B (en) | A charging detection circuit of appliance device and charging detection method | |
| US10845398B2 (en) | Interface circuitry for bidirectional power connector | |
| US20220011382A1 (en) | Usb interface detection module | |
| US20070075680A1 (en) | Charging mode control circuit | |
| US10200019B2 (en) | Power removal monitor circuit for interface disconnect detect | |
| CN103208822A (en) | Universal serial bus (USB) charging control circuit | |
| CN214849398U (en) | Interface circuit of electric connector | |
| CN103166062B (en) | Electronic installation and adapter thereof | |
| CN104701933B (en) | OTG selective charging circuit and portable loudspeaker box | |
| CN103491412A (en) | MHL device identification circuit with standby charging function | |
| CN104636096A (en) | Graphic card and electronic device | |
| CN206726209U (en) | Peripheral hardware insertion detection circuit and terminal device | |
| CN112086830B (en) | Data line circuit communicating with iOS device | |
| CN203760209U (en) | MHL cable and MHL cable hot plug detecting system | |
| CN217307303U (en) | Charging circuit capable of identifying external negative pole and charging base capable of being positively and negatively plugged | |
| CN221041793U (en) | Gating system of Type-C interface | |
| CN103700444B (en) | A kind of MHL cable, MHL cable hot plug detection system and detection method | |
| CN221007843U (en) | Poor contact detection device for USB interface design |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |