CN214848609U - Wafer and electronic equipment comprising same - Google Patents
Wafer and electronic equipment comprising same Download PDFInfo
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- CN214848609U CN214848609U CN202120583153.9U CN202120583153U CN214848609U CN 214848609 U CN214848609 U CN 214848609U CN 202120583153 U CN202120583153 U CN 202120583153U CN 214848609 U CN214848609 U CN 214848609U
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Abstract
The utility model relates to a wafer and contain electronic equipment of this wafer. The wafer at least comprises: a substrate; and M layers of metal located on the substrate, the M layers of metal being at different distances from the substrate; the circuit is characterized in that a pad lead is led out from a first layer of metal closest to the substrate; wherein M is a positive integer greater than or equal to 1. In the wafer, the pad lead is led out from the first layer of metal closest to the substrate of the wafer, so that the technical problem that the pad lead cannot be led out after the front surface of the wafer is subjected to hybrid bonding in the prior art is solved, and meanwhile, the stacking of multiple layers of metal does not exist, so that the input and output pad capacitance is small, and the influence on output signals and other signals is small.
Description
Technical Field
The utility model relates to a memory field. Specifically, the present invention relates to a wafer and an electronic apparatus including the wafer, in which pad leads are led out from the back surface of the wafer.
Background
Hybrid Bonding (HB) technology is a Wafer Level Electrical Connection (Wafer Level Electrical Connection) technology developed on the basis of CMOS image sensors in recent years.
In the prior art, a Wafer Level Electrical Connection (Wafer Level Electrical Connection) is mainly applied to an input/output Interface (I/O Interface) interconnection, and a new Wafer Level Electrical Connection is mainly applied to a functional circuit Connection.
Fig. 1A to 1C show the process steps of hybrid bonding in the prior art. FIG. 1A shows a Logic Wafer (Logic Wafer) and a Dynamic Random Access Memory (DRAM) Wafer, respectively, fabricated in different processes, where the Logic Wafer is shown to include at least the top metal of the Logic Wafer substrate and the Logic Wafer, and the DRAM Wafer includes at least the top metal of the DRAM Wafer substrate and the DRAM Wafer. The growth of bond posts on logic and DRAM wafers is illustrated in fig. 1B, which shows the growth of the logic wafer vias and the connection of the logic wafer top metal to the logic wafer vias, and the DRAM wafer vias and the connection of the DRAM wafer top metal to the DRAM wafer vias. Fig. 1C shows the face-to-face bonding of the logic and DRAM wafers shown in fig. 1A and 1B.
Fig. 2 shows an example of pad leads leading from the front side of a wafer as commonly used in the prior art. In fig. 2, pad leads are drawn from the top metal of the wafer (here the third layer metal).
In hybrid bonding, after the logic wafer and the DRAM wafer are bonded face-to-face at the front side, signal lines to be interconnected with the outside cannot be led out from the front side. In addition, when a pad lead is led out from the front surface of a wafer in the prior art, such as in fig. 2, a signal inside a chip is always connected to a top metal layer through a metal layer (a first metal layer and a second metal layer in fig. 2) nearest to a substrate, and the like, and the stacking of the multiple metal layers causes a parasitic capacitance on the signal to be large, thereby affecting the quality of an output signal, and also affects the quality of other signals through parasitic capacitive coupling.
Therefore, there is a need to solve the above technical problems in the prior art.
SUMMERY OF THE UTILITY MODEL
The utility model relates to a wafer and contain electronic equipment of this wafer. In the wafer, the pad lead is led out from the first layer of metal closest to the substrate of the wafer, so that the technical problem that the pad lead cannot be led out after the front surface of the wafer is subjected to hybrid bonding in the prior art is solved, and meanwhile, the stacking of multiple layers of metal does not exist, so that the input and output pad capacitance is small, and the influence on output signals and other signals is small.
According to the utility model discloses an aspect provides a wafer, the wafer includes at least:
a substrate; and the number of the first and second groups,
m layers of metal positioned on the substrate, wherein the distances between the M layers of metal and the substrate are different from each other; it is characterized in that the preparation method is characterized in that,
a pad lead that is drawn from a first layer of metal closest to the substrate;
wherein M is a positive integer greater than or equal to 1.
According to a preferred embodiment of the present invention, the wafer is a combination wafer obtained after the logic wafer and the memory wafer are mixed and bonded.
According to a preferred embodiment of the wafer of the present invention, the pad lead is led out from a first layer of metal closest to a substrate of the logic wafer.
According to a preferred embodiment of the wafer of the present invention, the pad lead is led out from a first layer of metal closest to a substrate of the memory wafer.
According to a preferred embodiment of the wafer of the present invention, the first pad lead is drawn from the first layer metal closest to the substrate of the logic wafer, and the second pad lead is drawn from the first layer metal closest to the substrate of the memory wafer.
According to a preferred embodiment of the wafer of the present invention, the M layers of metal communicate with each other through a signal line.
According to a preferred embodiment of the wafer of the present invention, the pad lead is led out from a position in the substrate where the substrate thickness is relatively thin, the position where the substrate thickness is relatively thin being obtained by a grinding process.
According to a preferred embodiment of the wafer of the present invention, there is a hole at a position where the substrate thickness is relatively thin, and the pad lead is led out from the first layer metal through the hole.
According to a preferred embodiment of the wafer of the present invention, the substrate thickness is relatively thin, which means that the substrate thickness is 3 microns.
According to a preferred embodiment of the wafer according to the present invention, there is a first back pad in the hole.
According to the utility model discloses a preferred embodiment of wafer, first back pad is connected first layer metal and second back pad, the pad lead wire with second back pad is connected.
According to a preferred embodiment of the wafer of the present invention, the second backside pads are aluminum pads.
According to a second aspect of the present invention, there is provided an electronic device comprising a wafer according to any of the above embodiments.
According to a third aspect of the present invention, there is provided a method of manufacturing a wafer, the method at least comprising:
producing a substrate of a wafer;
arranging M layers of metal on a substrate of the wafer, wherein the distances between the M layers of metal and the substrate are different from each other;
leading out a pad lead from a first layer of metal closest to the substrate;
wherein M is a positive integer greater than or equal to 1.
According to a preferred embodiment of the method of the present invention, the wafer is a composite wafer obtained after hybrid bonding of a logic wafer and a memory wafer.
According to a preferred embodiment of the method of the present invention, the method further comprises:
and leading out the bonding pad lead from the first layer of metal closest to the substrate of the logic wafer.
According to a preferred embodiment of the method of the present invention, the method further comprises:
the pad leads are led out from a first layer of metal closest to a substrate of the memory wafer.
According to a preferred embodiment of the method of the present invention, the method further comprises:
a first pad lead is led out from the first layer of metal closest to the substrate of the logic wafer, and a second pad lead is led out from the first layer of metal closest to the substrate of the memory wafer.
According to a preferred embodiment of the method of the present invention, the method further comprises:
and the M layers of metal are communicated through a signal wire.
According to a preferred embodiment of the method of the present invention, the method further comprises:
and leading out the bonding pad lead from the position, with relatively thin substrate thickness, in the substrate, and obtaining the position with relatively thin substrate thickness through a grinding process.
According to a preferred embodiment of the method of the present invention, the method further comprises:
providing a hole at a position where the substrate thickness is relatively thin, and leading out the pad lead from the first layer metal through the hole.
According to a preferred embodiment of the method of the present invention, the method further comprises:
the relatively thin substrate thickness was set to a substrate thickness of 3 microns.
According to a preferred embodiment of the method of the present invention, the method further comprises:
a first back pad is disposed in the hole.
According to a preferred embodiment of the method of the present invention, the method further comprises:
the first back pad connects the first layer of metal to a second back pad, and the pad lead is connected to the second back pad.
According to a preferred embodiment of the method of the present invention, the method further comprises:
the second backside pads are provided as aluminum pads.
According to a fourth aspect of the present invention, there is provided an electronic device comprising a wafer manufactured according to the method of any of the above.
Drawings
The invention will be more readily understood by the following description in conjunction with the accompanying drawings, in which:
fig. 1A to 1C show the process steps of hybrid bonding in the prior art.
Fig. 2 shows an example of pad wiring led out from the front side of a wafer in the prior art.
Fig. 3 shows a general schematic cross-sectional view of lead out pad wires in a wafer according to the present invention.
Fig. 4 is a schematic illustration of a wafer cross-section according to an embodiment of the present invention.
Fig. 5 is a schematic illustration of a wafer cross-section according to another embodiment of the present invention.
Fig. 6 is a schematic illustration of a wafer cross-section according to yet another embodiment of the present invention.
Fig. 7 is a flow chart of one embodiment of a method of fabricating a wafer according to the present invention.
Detailed Description
Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
Fig. 3 shows a general schematic cross-sectional view of a lead out pad in a wafer according to the present invention.
The wafer 300 shown in fig. 3 may be a logic wafer, a memory wafer such as a DRAM wafer, or a combination wafer obtained after the logic wafer and the memory wafer are hybrid bonded.
In this context, a logic wafer refers to a wafer that implements a logic function, and a memory wafer is a wafer that implements a memory function.
As shown in fig. 3, the wafer 300 includes: a substrate 30; and a first layer of metal 31 and a second layer of metal 35 on the substrate 30.
Those skilled in the art will appreciate that both the first layer metal 31 and the second layer metal 35 in the wafer 300 are fabricated on the substrate 30. The substrate of the wafer 300 may be made of a single crystalline semiconductor material such as known in the art and the metal layer may be made of an aluminum material such as known in the art.
In addition, since the pad wires 32 in the present invention are led out from the back surface of the substrate 30, in order to explain the gist of the present invention more clearly, a cross-sectional view of the wafer 300 after being turned over is shown in fig. 3. Furthermore, to avoid obscuring the spirit of the present invention, only a portion of the wafer is shown in fig. 3, and those skilled in the art will appreciate that the wafer 300 also includes some components not shown in fig. 3.
In fig. 3, the first layer metal 31 and the second layer metal 35 are at different distances from the substrate 30, the first layer metal 31 being closer to the substrate 30 and the second layer metal 35 being farther from the substrate 30. It should be understood that only two layers of metal are shown in fig. 3 for purposes of illustration. In fact, the wafer 300 may include multiple layers of metal. In the case where the wafer 300 includes a plurality of layers of metal, the distances of the plurality of layers of metal and the substrate 30 are different from each other.
As shown in fig. 3, pad leads 32 in the wafer 300 are drawn from the first layer of metal 31 closest to the substrate 30. If the internal signal is from the second layer metal 35 or higher layer metal, the second layer metal 35 or higher layer metal is connected to the first layer metal 31 through a thinner signal line such as signal line 36.
Therefore, the technical problem that bonding pad leads which are interconnected with the outside cannot be led out after the logic wafer and the memory wafer are face-to-face mixed and bonded on the front surfaces in the prior art is solved. In addition, since the pad lead 32 is led out from the first layer metal 31, there is no lamination of multiple layers of metals, so that the input/output pad capacitance is small, and the influence on the output signal and other signals is small.
The specific operation steps of the lead out pad wire 32 are further detailed below in conjunction with fig. 3.
In a first step, the substrate 30 of the wafer 300 is ground thin so that the thickness d (as shown in fig. 3) of the substrate 30 is about 3 microns. The polishing process used herein may be any one of the prior art as long as the substrate can be polished thin.
In addition, it should be understood that a substrate thickness of 3 microns as referred to herein is preferred, and not necessarily so. This value may vary as the technology evolves.
In a second step, etching openings are made by etching at locations having a thickness d of about 3 microns.
Note that the depth of the opening needs to reach the first-layer metal 31 so that the pad wiring 32 can be led out from the first-layer metal 31.
The etching process referred to herein may be any etching process known in the art, such as coating a photoresist layer on a surface and then selectively exposing the resist layer through a mask, wherein the mask selectively etches the surface of the substrate by leaving a resist pattern on the surface of the substrate after development due to the difference in dissolution rate of the exposed and unexposed portions of the resist layer in a developer.
Third, a first backside pad 33 is etched in the hole, where the first backside pad 33 may be an aluminum pad.
In the fourth step, a second back pad 34 is grown on the first back pad 33, and the pad wire 32 is connected to the second back pad 34. The second backside pads 34 may also be aluminum pads. The growth processes mentioned herein are metal growth processes known in the art.
This enables the pad leads 32 to be led out from the first layer of metal 31 on the substrate of the wafer 300.
Fig. 4 is a schematic illustration of a wafer cross-section according to an embodiment of the present invention.
The wafer 400 shown in fig. 4 is a combination wafer resulting after hybrid bonding of a logic wafer and a memory wafer. The upper half of the dotted line shown in fig. 4 is a logic wafer and the lower half of the dotted line is a memory wafer. And after being turned, the logic wafer is mixed and bonded with the memory wafer. Here, in order to avoid obscuring the gist of the present invention, the hybrid bonding process is not further detailed.
In the wafer 400 shown in fig. 4, the pad wires 42 are led out from the first layer of metal 41 on the substrate 40 of the logic wafer. To clearly show the lead-out of the pad lead 42, the logic wafer shown in fig. 4 includes: a substrate 40; a first layer of metal 41; pad wires 42; the first back pad 43; and a second backside pad 44.
Since the pad leads are not drawn from the memory wafer in fig. 4, the memory wafer is only schematically shown to include a substrate 40 'and a first layer of metal 41'.
Fig. 5 is a schematic illustration of a wafer cross-section according to another embodiment of the present invention.
The wafer 500 shown in fig. 5 is a combination wafer resulting after the logic and memory wafers are hybrid bonded. The upper half of the dotted line shown in fig. 5 is a logic wafer and the lower half of the dotted line is a memory wafer. And after being turned, the logic wafer is mixed and bonded with the memory wafer. Again, to avoid obscuring the teachings of the present invention, no further details are given to the hybrid bonding process.
In the wafer 500 shown in fig. 5, pad wires 52 are drawn from the first layer of metal 51 in the logic wafer. To clearly show the lead-out of the pad wire 52, the logic wafer shown in fig. 5 includes: a substrate 50; a first layer metal 51; pad wires 52; the first back pad 53; and a second backside pad 54.
In addition, in the wafer 500 shown in fig. 5, the pad wire 52 'is led out from the first-layer metal 51' in the memory wafer. To clearly show the lead-out of the pad leads 52', the memory wafer shown in fig. 5 includes: a substrate 50'; a first layer of metal 51'; pad wires 52'; a first back pad 53'; and a second backside pad 54'.
Fig. 6 is a schematic illustration of a wafer cross-section according to an embodiment of the present invention.
The wafer 600 shown in fig. 6 is a combination wafer resulting after the logic and memory wafers are hybrid bonded. The upper half of the dotted line shown in fig. 6 is a logic wafer, and the lower half of the dotted line is a memory wafer. And after being turned, the logic wafer is mixed and bonded with the memory wafer. Here, in order to avoid obscuring the gist of the present invention, the hybrid bonding process is not further detailed.
In the wafer 600 shown in fig. 4, the pad wires 62 ' are led out from the first layer of metal 61 ' on the substrate 60 ' of the memory wafer. To clearly show the lead-out of the pad lead 62', the memory wafer shown in fig. 6 includes: a substrate 60'; a first layer of metal 61'; pad wires 62'; a first back pad 63'; second backside pads 64'.
Since the pad leads are not drawn from the logic wafer in fig. 6, the logic wafer is only schematically shown to include a substrate 60 and a first layer of metal 61.
Fig. 7 is a flow chart of one embodiment of a method of fabricating a wafer according to the present invention.
Step 701: a substrate for a production wafer.
Step 702: arranging M layers of metal on a substrate of the wafer, wherein the distances between the M layers of metal and the substrate are different from each other; wherein M is a positive integer greater than or equal to 1.
Step 703: pad leads are led out from the first layer of metal closest to the substrate.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. It is to be understood that the scope of the invention is defined by the claims.
Claims (13)
1. A wafer, comprising:
a substrate; and the number of the first and second groups,
m layers of metal positioned on the substrate, wherein the distances between the M layers of metal and the substrate are different from each other;
a pad lead that is drawn from a first layer of metal closest to the substrate;
wherein M is a positive integer greater than or equal to 1.
2. The wafer of claim 1, wherein the wafer is a combination wafer obtained after hybrid bonding of a logic wafer and a memory wafer.
3. The wafer of claim 2, wherein the pad wire is routed from a first layer of metal closest to a substrate of the logic wafer.
4. The wafer of claim 2, wherein the pad leads are routed from a first layer of metal closest to a substrate of the memory wafer.
5. The wafer of claim 2, wherein a first pad lead is routed from a first layer of metal closest to a substrate of the logic wafer and a second pad lead is routed from the first layer of metal closest to the substrate of the memory wafer.
6. The wafer of claim 1, wherein the M layers of metal communicate with each other through signal lines.
7. The wafer of claim 1, wherein the pad lead is led out from a position in the substrate where the substrate thickness is relatively thin, and the position where the substrate thickness is relatively thin is obtained through a grinding process.
8. The wafer of claim 7, wherein there is a hole where the substrate thickness is relatively thin, the pad lead being led out of the first layer metal through the hole.
9. The wafer of claim 7 or 8, wherein the substrate thickness is relatively thin, which means that the substrate thickness is 3 microns.
10. The wafer of claim 8, wherein there is a first back pad in the hole.
11. The wafer of claim 10, wherein the first back-side pad connects the first layer of metal to a second back-side pad, and wherein the pad lead connects to the second back-side pad.
12. The wafer of claim 11, in which the second back pad is an aluminum pad.
13. An electronic device, characterized in that the electronic device comprises a wafer according to any one of claims 1-12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120583153.9U CN214848609U (en) | 2021-03-22 | 2021-03-22 | Wafer and electronic equipment comprising same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120583153.9U CN214848609U (en) | 2021-03-22 | 2021-03-22 | Wafer and electronic equipment comprising same |
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| Publication Number | Publication Date |
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| CN214848609U true CN214848609U (en) | 2021-11-23 |
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| CN202120583153.9U Active CN214848609U (en) | 2021-03-22 | 2021-03-22 | Wafer and electronic equipment comprising same |
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- 2021-03-22 CN CN202120583153.9U patent/CN214848609U/en active Active
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