CN214846694U - Multi-mode device and chip - Google Patents
Multi-mode device and chip Download PDFInfo
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- CN214846694U CN214846694U CN202120656992.9U CN202120656992U CN214846694U CN 214846694 U CN214846694 U CN 214846694U CN 202120656992 U CN202120656992 U CN 202120656992U CN 214846694 U CN214846694 U CN 214846694U
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Abstract
The application discloses a multi-mode device and a chip, wherein the device can comprise a memory, a processor and four circuit modules; wherein the memory and the processor support any one of a 4-wire SPI mode, a 3-wire SPI mode and a 2-wire I2C mode; the four circuit modules comprise a first circuit module, a second circuit module, a third circuit module and a fourth circuit module; the first circuit module comprises a clock input end, the second circuit module comprises a chip selection input end, the third circuit module comprises a data input end, and the fourth circuit module comprises a data output end. The device can work in different modes, flexibly support different types of main equipment, and avoid the condition that a communication end connected with the main equipment cannot be used under the condition that GPIO resources of the main equipment are limited.
Description
Technical Field
The application relates to the field of chip design, in particular to a multi-mode device and a chip.
Background
Existing Serial Peripheral Interface (SPI) devices, such as 4-wire SPI, 3-wire SPI, or Inter-Integrated Circuit (12C) devices, all support only one communication protocol, and the number of corresponding General Purpose Input Output (GPIO) ports is also determined. For example, 4 GPIO ports are required for a 4-wire SPI, 3 GPIO ports are required for a 3-wire SPI, and 2 GPIO ports are required for a 2-wire I2C.
However, if the master device is originally connected to the 3-wire SPI device, and resources of the GPIO port are limited due to other connections, and the master device needs to be connected to a device with fewer GPIO ports, the currently connected 3-wire SPI device cannot meet communication requirements, and other I2C devices may need to be additionally replaced.
Disclosure of Invention
In order to solve at least one of the above technical problems, the present application provides the following solutions.
In a first aspect, an embodiment of the present application further provides a multi-mode device, where the device includes: the device comprises a memory, a processor and four circuit modules;
the memory and the processor support any one of a 4-wire SPI mode, a 3-wire SPI mode and a 2-wire I2C mode;
the four circuit modules comprise a first circuit module, a second circuit module, a third circuit module and a fourth circuit module;
the first circuit module comprises a clock input end, the second circuit module comprises a chip selection input end, the third circuit module comprises a data input end, and the fourth circuit module comprises a data output end.
Optionally, each of the four circuit modules includes a pull-up enable PUEN terminal, a digital enable DIEN terminal, and an output enable OE terminal;
the levels of the PUEN terminal, the DIEN terminal and the OE terminal are configurable.
Optionally, the device operates in the 4-wire SPI mode when the clock input, the chip select input, the data input, and the data output are all in an operating state.
Optionally, the device operates in the 3-wire SPI mode when the clock input, the chip select input, and the data input are all in an operating state and the data output is in a high impedance state.
Optionally, the device operates in 2-wire I2C mode with both the clock input and the data input in an active state, the chip select input in a pull-up state, and the data output in a high impedance state.
Optionally, in the case that the device operates in the 4-wire SPI mode, the DIEN terminal on the first circuit module is a constant 1, the OE terminal is a constant 0, and the PUEN terminal is a pull-up enable, configured as 0;
the DIEN end on the second circuit module is a constant 1, the OE end is a constant 0, and the PUEN end is pull-up enabling and is configured to be 0;
the DIEN end on the third circuit module is configured to be 1, the OE end is configured to be 0, and the PUEN end is pull-up enabling and is configured to be 0;
the DIEN terminal of the fourth circuit module is configured to be 0, the OE terminal is configured to be 1, and the PUEN terminal is pull-up enable and is configured to be 0.
Optionally, in the case that the device operates in the 3-wire SPI mode, the DIEN terminal on the first circuit module is a constant 1, the OE terminal is a constant 0, and the PUEN terminal is a pull-up enable, configured as 0;
the DIEN end on the second circuit module is a constant 1, the OE end is a constant 0, and the PUEN end is pull-up enabling and is configured to be 0;
the level of a DIEN end and the level of an OE end on the third circuit module are controlled by hardware, and the PUEN end is pull-up enabled and is configured to be 0;
the DIEN terminal and the OE terminal on the fourth circuit module are configured to be 0, and the PUEN terminal is pull-up enabling and is configured to be 0.
Optionally, in the case that the device operates in the 2-wire I2C mode, the DIEN terminal on the first circuit block is a constant 1, the OE terminal is a constant 0, and the PUEN terminal is a pull-up enable, configured as 1;
the DIEN end on the second circuit module is a constant 1, the OE end is a constant 0, and the PUEN end is pull-up enabling and is configured to be 1;
a DIEN end on the third circuit module is a normal 1, an OE end is a hardware control level, and a PUEN end is a pull-up enable and is configured to be 1;
the DIEN terminal and the OE terminal on the fourth circuit module are configured to be 0, and the PUEN terminal is pull-up enabling and is configured to be 0.
Optionally, in the case that the device operates in the 4-wire SPI mode, the processor executes initialization code of the 4-wire SPI mode stored in the memory;
or, in the case that the device operates in the 3-wire SPI mode, the processor executes the initialization code of the 3-wire SPI mode stored in the memory;
alternatively, in the case where the device is operating in 2-line I2C mode, the processor runs memory-stored initialization code for 2-line I2C mode.
In a second aspect, an embodiment of the present application further provides a chip, where the chip includes the multi-mode device provided in the embodiment of the present application.
The embodiment of the application provides a multi-mode device and a chip, wherein the device can comprise a memory, a processor and four circuit modules; wherein the memory and the processor support any one of a 4-wire SPI mode, a 3-wire SPI mode and a 2-wire I2C mode; the four circuit modules comprise a first circuit module, a second circuit module, a third circuit module and a fourth circuit module; the first circuit module comprises a clock input end, the second circuit module comprises a chip selection input end, the third circuit module comprises a data input end, and the fourth circuit module comprises a data output end. The device can work in different modes, flexibly support different types of main equipment, and avoid the condition that a communication end connected with the main equipment cannot be used under the condition that GPIO resources of the main equipment are limited.
Drawings
FIG. 1 is a schematic diagram of a multi-mode device according to an embodiment of the present application;
fig. 2 is a schematic diagram of a circuit module according to an embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures.
In addition, in the embodiments of the present application, the words "optionally" or "exemplarily" are used for indicating as examples, illustrations or explanations. Any embodiment or design described herein as "optionally" or "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the words "optionally" or "exemplarily" etc. is intended to present the relevant concepts in a concrete fashion.
The embodiment of the present application provides a multi-mode device, as shown in fig. 1, which includes a memory 101, a processor 102, and four circuit modules 103;
in the apparatus, the memory and the processor may support any one of a 4-line SPI mode, a 3-line SPI mode, and a 2-line I2C mode. Namely, the device is used as a cluster device, and when the device is connected with any main device, the device can carry out adaptation and communication according to the GPIO port resource condition of the main device. For example, if the GPIO port resource of the master device is sufficient and the requirement for the communication rate is high, the apparatus may be set to operate in the 4-wire SPI mode to communicate with the master device; if the main device GPIO has less resources and has lower requirements on the communication rate, the device can be set to work in a 2-wire I2C mode; if the resources of the master GPIO and the requirement on the communication speed are between 4-line SPI and 2-line I2C, the device can be set to work in a 3-line SPI mode.
Exemplarily, as shown in fig. 2, it is assumed that the four circuit blocks include a first circuit block, a second circuit block, a third circuit block, and a fourth circuit block. Wherein the first circuit block may comprise a clock input (PAD _ CSK), the second circuit block may comprise a chip select input (PAD _ CSN), the third circuit block may comprise a data input (PAD _ MOSI), and the fourth circuit block may comprise a data output (PAD _ MISO).
The embodiment of the application provides a multi-mode device, which can comprise a memory, a processor and four circuit modules; wherein the memory and the processor support any one of a 4-wire SPI mode, a 3-wire SPI mode and a 2-wire I2C mode; the four circuit modules comprise a first circuit module, a second circuit module, a third circuit module and a fourth circuit module; the first circuit module comprises a clock input end, the second circuit module comprises a chip selection input end, the third circuit module comprises a data input end, and the fourth circuit module comprises a data output end. The device can work in different modes, flexibly support different types of main equipment, and avoid the condition that a communication end connected with the main equipment cannot be used under the condition that GPIO resources of the main equipment are limited.
As shown IN fig. 2, IN one example, each of the four circuit blocks may include an input IN terminal, an output OUT terminal, a pull-down enable PDEN terminal, a pull-up enable PUEN terminal, a digital enable DIEN terminal, and an output enable OE terminal. Unlike the prior art apparatus that supports a communication mode (e.g., 4-wire SPI mode or 3-wire SPI mode), in the multi-mode device in the present embodiment, the levels of the PUEN terminal, the DIEN terminal, and the OE terminal are configurable, i.e., the high and low levels of the PUEN terminal, the DIEN terminal, and the OE terminal can be flexibly configured, and these three ports cooperate with the internal circuit of each circuit module and other ports on each circuit module, e.g., corresponding ports PAD _ CSK, PAD _ CSN, PAD _ MOSI, and PAD _ MISO on the four circuit modules shown in fig. 2, so that the device can operate in different modes.
Of course, the above-mentioned device may also include other functional circuits besides four circuit modules, and for the sake of more clear circuit diagram presentation, the operation principle of the device in different modes in this application is explained, and only a part of the diagram is shown here, as shown in fig. 2.
In one example, in the case that the clock input terminal of the first circuit module, the chip select input terminal of the second circuit module, the data input terminal of the third circuit module, and the data output terminal of the fourth circuit module shown in fig. 2 are all in the working state, the device operates in the 4-wire SPI mode.
In another case, the clock input terminal of the first circuit module, the chip select input terminal of the second circuit module, and the data input terminal of the third circuit module are all in a working state, and the data output terminal of the fourth circuit module is in a high impedance state, and the device operates in a 3-wire SPI mode.
In the third case, when the clock input terminal of the first circuit block and the data input terminal of the third circuit block are both in an operating state, the chip select input terminal of the second circuit block is in a pull-up state, and the data output terminal of the fourth circuit block is in a high impedance state, the apparatus operates in the 2-line I2C mode.
Further, when the device operates in different modes, the other ports on each circuit module are set as follows:
under the condition that the device works in a 4-wire SPI mode, a DIEN end on a first circuit module is a constant 1, an OE end on the first circuit module is a constant 0, and a PUEN end is pull-up enabling and is configured to be 0; the DIEN end on the second circuit module is a constant 1, the OE end is a constant 0, and the PUEN end is pull-up enabling and is configured to be 0; the DIEN end on the third circuit module is configured to be 1, the OE end is configured to be 0, and the PUEN end is pull-up enabling and is configured to be 0; the DIEN terminal of the fourth circuit module is configured to be 0, the OE terminal is configured to be 1, and the PUEN terminal is pull-up enable and is configured to be 0.
Under the condition that the device works in a 3-wire SPI mode, a DIEN end on a first circuit module is a constant 1, an OE end is a constant 0, and a PUEN end is a pull-up enable and is configured to be 0; the DIEN end on the second circuit module is a constant 1, the OE end is a constant 0, and the PUEN end is pull-up enabling and is configured to be 0; the level of the DIEN terminal and the level of the OE terminal on the third circuit module are controlled by hardware, for example, the OE terminal is controlled to be a high level in a hardware control manner, and the DIEN terminal is a low level, which indicates that the logic of the two ports in the circuit is output; if the hardware controls the OE end to be low level and the DIEN end to be high level, the port is input, the PUEN end is pull-up enabling and is configured to be 0; the DIEN terminal and the OE terminal on the fourth circuit module are configured to be 0, and the PUEN terminal is pull-up enabling and is configured to be 0.
Under the condition that the device works in a 2-wire I2C mode, a DIEN end on the first circuit module is a constant 1, an OE end is a constant 0, and a PUEN end is a pull-up enable and is configured to be 1; the DIEN end on the second circuit module is a constant 1, the OE end is a constant 0, and the PUEN end is pull-up enabling and is configured to be 1; a DIEN end on the third circuit module is a normal 1, an OE end is a hardware control level, and a PUEN end is a pull-up enable and is configured to be 1; the DIEN terminal and the OE terminal on the fourth circuit module are configured to be 0, and the PUEN terminal is pull-up enabling and is configured to be 0.
The following describes in table form the detailed settings of the ports of the multi-mode device when operating in different modes, specifically as follows:
TABLE 14 line SPI mode
TABLE 23 line SPI mode
TABLE 32 line I2C mode
Since the device can support different working or communication modes, when the device works in different modes, the processor needs to be correspondingly controlled in addition to correspondingly controlling each port on the hardware circuit, and the initialization process of the corresponding mode is operated according to different interface modes.
For example, in the case where the above-described device operates in the 4-wire SPI mode, the processor may execute the initialization code of the 4-wire SPI mode stored in the memory.
Illustratively, the initialization code for the 4-wire SPI mode includes:
powering on, and waiting for POR to be pulled high;
address F3 writes 16' h0840, turns off MOSI _ PAD _ PU, SPI _3_ WIRE _ EN;
address F1 writes 8' h00, turns off CSK _ PAD _ PU, CSN _ PAD _ PU;
read and write other registers.
Alternatively, in the case where the device operates in 3-wire SPI mode, the processor may run initialization code of the 3-wire SPI mode stored in the memory.
Illustratively, the initialization code of the 3-wire SPI mode includes:
powering on, and waiting for POR to be pulled high;
address F3 writes 16' h0940, turning off MOSI _ PAD _ PU;
address F1 writes 8' h00, turns off CSK _ PAD _ PU, CSN _ PAD _ PU;
read and write other registers.
In the case of the device operating in 2-line I2C mode, the processor runs memory-stored initialization code for 2-line I2C mode.
Illustratively, the initialization code for the 2-line I2C mode includes:
powering on, and waiting for POR to be pulled high;
read and write other registers.
The multi-mode device can be supported to work in different modes through different initialization processes of a software layer, and therefore various main devices can be flexibly supported.
The embodiment of the application also provides a chip, which can comprise the multi-mode device, and can work in various different modes and flexibly support the main equipment connected with the multi-mode device.
From the above description of the embodiments, it is obvious for those skilled in the art that the present application can be implemented by software and necessary general hardware, and certainly can be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) to implement the methods or functions described in the embodiments of the present application.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present application and the technical principles employed. It will be understood by those skilled in the art that the present application is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the application. Therefore, although the present application has been described in more detail with reference to the above embodiments, the present application is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present application, and the scope of the present application is determined by the scope of the appended claims.
Claims (10)
1. A multi-mode device, comprising: the device comprises a memory, a processor and four circuit modules;
the memory and the processor support any one of a 4-wire Serial Peripheral Interface (SPI) mode, a 3-wire SPI mode and a 2-wire integrated circuit (I2C) mode;
the four circuit modules comprise a first circuit module, a second circuit module, a third circuit module and a fourth circuit module;
the first circuit module comprises a clock input end, the second circuit module comprises a chip selection input end, the third circuit module comprises a data input end, and the fourth circuit module comprises a data output end.
2. The apparatus of claim 1, wherein each of the four circuit blocks comprises a pull-up enable PUEN terminal, a digital enable DIEN terminal, and an output enable OE terminal;
the levels of the PUEN terminal, the DIEN terminal and the OE terminal are configurable.
3. The apparatus of claim 1, wherein the apparatus operates in a 4-wire SPI mode when the clock input, the chip select input, the data input, and the data output are all in an active state.
4. The apparatus of claim 1, wherein the apparatus operates in 3-wire SPI mode when the clock input, the chip select input, and the data input are all in an active state and the data output is in a high impedance state.
5. The apparatus of claim 1, wherein the apparatus operates in a 2-line I2C mode with the clock input and the data input both in an active state, the chip select input in a pull-up state, and the data output in a high impedance state.
6. The apparatus of claim 3, wherein when the apparatus operates in 4-wire SPI mode, the DIEN terminal on the first circuit block is constant 1, the OE terminal is constant 0, and the PUEN terminal is pull-up enabled and configured to be 0;
a DIEN end on the second circuit module is a constant 1, an OE end is a constant 0, and a PUEN end is a pull-up enable and is configured to be 0;
a DIEN end on the third circuit module is configured to be 1, an OE end is configured to be 0, and a PUEN end is pull-up enabling and is configured to be 0;
the DIEN terminal of the fourth circuit module is configured to be 0, the OE terminal of the fourth circuit module is configured to be 1, and the PUEN terminal of the fourth circuit module is pull-up enable and is configured to be 0.
7. The apparatus of claim 4, wherein when the apparatus operates in 3-wire SPI mode, the DIEN terminal on the first circuit block is constant 1, the OE terminal is constant 0, and the PUEN terminal is pull-up enabled and configured to be 0;
a DIEN end on the second circuit module is a constant 1, an OE end is a constant 0, and a PUEN end is a pull-up enable and is configured to be 0;
the level of a DIEN end and the level of an OE end on the third circuit module are controlled by hardware, and the PUEN end is pull-up enabled and is configured to be 0;
and the DIEN terminal and the OE terminal on the fourth circuit module are configured to be 0, and the PUEN terminal is pull-up enable and is configured to be 0.
8. The apparatus of claim 5, wherein when the apparatus operates in 2-wire I2C mode, the DIEN terminal of the first circuit block is constant 1, the OE terminal is constant 0, and the PUEN terminal is pull-up enabled and configured as 1;
a DIEN end on the second circuit module is a constant 1, an OE end is a constant 0, and a PUEN end is a pull-up enable and is configured to be 1;
a DIEN end on the third circuit module is a normal 1, an OE end is a hardware control level, and a PUEN end is a pull-up enable and is configured to be 1;
and the DIEN terminal and the OE terminal on the fourth circuit module are configured to be 0, and the PUEN terminal is pull-up enable and is configured to be 0.
9. The device according to any one of claims 1-8, wherein in case the device operates in 4-wire SPI mode, the processor runs initialization code of the 4-wire SPI mode stored by the memory;
or, in the case that the device operates in a 3-wire SPI mode, the processor executes initialization code of the 3-wire SPI mode stored by the memory;
alternatively, in the case where the apparatus operates in the 2-line I2C mode, the processor executes the initialization code of the 2-line I2C mode stored in the memory.
10. A chip comprising a multi-mode device as claimed in any one of claims 1 to 9.
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| CN202120656992.9U CN214846694U (en) | 2021-03-31 | 2021-03-31 | Multi-mode device and chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115098428A (en) * | 2022-07-11 | 2022-09-23 | 深圳市金科泰通信设备有限公司 | SPI data transmission method and device, electronic equipment and storage medium |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115098428A (en) * | 2022-07-11 | 2022-09-23 | 深圳市金科泰通信设备有限公司 | SPI data transmission method and device, electronic equipment and storage medium |
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