CN214799448U - Digital display time relay - Google Patents
Digital display time relay Download PDFInfo
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- CN214799448U CN214799448U CN202121144691.4U CN202121144691U CN214799448U CN 214799448 U CN214799448 U CN 214799448U CN 202121144691 U CN202121144691 U CN 202121144691U CN 214799448 U CN214799448 U CN 214799448U
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Abstract
The utility model provides a digital display time relay, set for return circuit, delay time and set for return circuit, display circuit and output circuit including power return circuit, timing return circuit, delay time. The utility model discloses a digital display time relay adopts application specific integrated circuit, comes to set for time delay time base and time delay through five dial switch, and the display part adopts the quadbit charactron. The utility model discloses a digital display time relay's internal line is simple, has increased substantially the reliability and the accuracy nature of machine, has saved manufacturer's manual work and material expense greatly, reduces production and maintenance cost, has improved production efficiency and yield.
Description
Technical Field
The utility model belongs to the electronic equipment field, concretely relates to digital display time relay.
Background
The digital display time relay belongs to an electrified delay type, and has the advantages of small volume, wide delay range, high delay precision, convenience in setting, strong anti-interference performance, high reliability and the like. The circuit is suitable for various high-precision and high-reliability time delay elements which are connected or disconnected according to preset time in an automatic control field cooperation control circuit with alternating current of 50/60Hz, working voltage of 380V or below or direct current working voltage of 24V.
The digital display time relay manufactured by various manufacturers has the disadvantages that the internal circuit of the digital display time relay is complex, the production process is complicated, the production and maintenance cost is high, and the universality and the reliability of the machine are high.
In order to meet the requirements of manufacturers on low cost, high reliability, high accuracy and the like of digital display time relays, improve the production efficiency and the yield and reduce the production and maintenance cost, the redesign of the conventional digital display time relays has important practical significance and commercial value.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a digital display time relay, this digital display time relay's timing module adopt application specific integrated circuit, and the internal circuit is simple, and reliability and accuracy improve by a wide margin, have saved manufacturer's manual work and material cost greatly, have improved production efficiency.
In order to achieve the above purpose, the utility model adopts the technical scheme that:
the utility model provides a digital display time relay, include:
a delay time base setting circuit, which sets the delay time base by different set values of a group of 8421 dial switches, wherein 9 different delay time bases are provided;
a delay time setting loop, which sets the specific delay time from one bit to thousand bits through the different setting values of four groups of 8421 dial switches;
the timing loop comprises an application specific integrated circuit IC1, determines the delay time base and the delay time of the digital display time relay by reading the level signals of the delay time base setting loop and the delay time setting loop, and outputs a corresponding level trigger signal for the output loop after the delay time is finished;
the output loop comprises a snap relay and is used for reading a delay time signal in the timing loop, and the snap relay is controlled to act after the delay is finished;
the display loop comprises four-digit eight-segment nixie tubes and is used for displaying the timing state and the working state of the digital display time relay in real time;
and the power supply loop is used for supplying power to the display loop, the timing loop, the delay time base setting loop, the delay time setting loop and the output loop by reducing and rectifying the input alternating voltage into direct voltage.
The time delay time base setting loop comprises a resistor R7, an 8421 dial switch KY5 and diodes D18-D21; the port e of the special integrated circuit IC1 is in a high impedance state during programming, a 70K pull-down resistor is connected in the special integrated circuit IC1, a diode or a gate circuit is formed by an 8421 dial switch KY5, diodes D18-D21 and a resistor R7, data set by a user are sent to the special integrated circuit IC1 through the port e to be latched, and the special integrated circuit IC1 sets different delay time bases by reading the latched data; 8421 dial switch KY5 sets 0.1S, 1S, 0.1M, 1M, 0.1H, 1H, MS, HM, and 0.01S of the delay time base with 9 levels 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, and 1000, respectively.
The thousands of bits of the delay time setting circuit comprise a resistor R3, an 8421 dial switch KY1, diodes D2-D5 and a port a of an application-specific integrated circuit IC1, the hundreds of bits comprise a resistor R4, an 8421 dial switch KY2, diodes D6-D9 and a port b of an application-specific integrated circuit IC1, the tens of bits comprise a resistor R5, an 8421 dial switch KY3, diodes D10-D13 and a port c of an application-specific integrated circuit IC1, and the units comprise a resistor R6, an 8421 dial switch KY4, diodes D14-D17 and a port D of an application-specific integrated circuit IC 1; the ports a-D are in a high impedance state during programming, 70K pull-down resistors are connected inside the ports a-D, 4 diodes or gate circuits are formed by 8421 dial switches KY 1-KY 4, diodes D2-D17 and resistors R3-R6, data set by a user are sent to the special integrated circuit IC1 through the ports a-D to be latched, and different delay times are set by reading the latched data through the special integrated circuit IC 1; 8421 dial switches KY 1-KY 4 respectively use ten levels of 0000-1001 to realize thousands, hundreds, tens and units of digits 0-9 of delay time, so that the delay time range which can be set by the delay time setting circuit is 0000-9999.
The resistor R2, the capacitors C5 and C6, the crystal oscillator Y1 and XTAL0 and XTAL1 ports of the special integrated circuit IC1 form an external oscillation circuit in the timing loop; the VDD port of the special integrated circuit IC1 is a power supply pin and is connected with direct current 6V voltage; the GND port of the asic IC1 is a ground pin and is connected to dc ground.
The output circuit comprises a snap relay K1A, a diode D1, a resistor R1 and a triode Q2; after the digital display time relay is electrified, an OUT port of the special integrated circuit IC1 outputs a low level, a coil of the snap relay K1A is in a release state, after the time delay reaches a set value, the OUT port outputs a high level, the triode Q2 is driven to be conducted through the resistor R1, the coil of the snap relay K1A is attracted, and the contact state is switched; the diode D1 is used for eliminating the self-excited voltage of the snap relay K1A, and the resistor R1 is the base current-limiting resistor of the triode Q2.
The display loop is composed of 1 four-position eight-segment nixie tube DS1, resistors R8-R15 and diodes D22-D25; eight segment input ports a to h of a nixie tube DS1 are respectively connected to anode output driving ports a to h of an application-specific integrated circuit IC1 through resistors R8 to R15 and are used for displaying four-bit delay time 0000 to 9999 of a digital display time relay; the bit input port of the nixie tube DS1 is connected to the D1-D4 cathode output driving ports of the special integrated circuit IC1 through diodes D22-D25 respectively and used for lighting the timing bit of the digital display time relay.
The power supply loop supplies power to the display loop, the timing loop, the delay time base setting loop, the delay time setting loop and the output loop by reducing and rectifying the input 220V alternating voltage into 15V and 6V direct voltage.
Compared with the prior art, the beneficial effects of the utility model are that:
the utility model provides a digital display time relay's timing module adopts application specific integrated circuit, comes to set for time delay time base and time delay through five dial switch, and the display part adopts the quadbit charactron. The utility model discloses a digital display time relay's internal line is simple, has increased substantially the reliability and the accuracy nature of machine, has saved manufacturer's manual work and material expense greatly, reduces production and maintenance cost, has improved production efficiency and yield.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a module of the digital display time relay of the present invention;
FIG. 2 is a schematic circuit diagram of the power supply circuit of the digital display time relay of the present invention;
FIG. 3 is a schematic circuit diagram of the timing loop of the digital display time relay of the present invention;
FIG. 4 is a schematic circuit diagram of the delay time base setting circuit and the delay time setting circuit of the digital display time relay of the present invention;
FIG. 5 is a schematic circuit diagram of the display circuit of the digital display time relay of the present invention;
FIG. 6 is a schematic circuit diagram of the output circuit of the digital display time relay of the present invention;
fig. 7 is a circuit schematic diagram of the digital display time relay of the present invention.
Detailed Description
In order to make the technical solutions in the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments.
The utility model provides a follow-on digital display time relay (hereinafter be referred to as time relay for short). The timing module of the time relay adopts a special integrated circuit, the time delay time base and the time delay time are set through five dial switches, and a display part adopts a four-digit nixie tube. The time relay has the advantages that the internal circuit is simple, the reliability and the accuracy are greatly improved, the labor and material cost of manufacturers is greatly saved, and the production efficiency is improved.
As shown in fig. 1 and 7, the digital display time relay provided by the present invention mainly comprises a power supply circuit, a timing circuit, a delay time setting circuit, a display circuit and an output circuit.
The power supply loop is used for supplying power to other subsequent loops by reducing and rectifying the input alternating voltage into required direct voltage.
The timing loop takes an application specific integrated circuit as a core, and firstly determines the delay time base and the delay time of the time relay through level signals of the delay time base setting loop and the delay time setting loop. And outputting a corresponding level trigger signal for the output loop through the output port after the delay time is over.
The delay time base setting loop realizes different delay time bases by setting different set values of a group of 8421 dial switches, and the time relay has 9 different delay time bases.
The delay time setting loop realizes specific delay time from one digit to one thousand digits by setting four groups of 8421 dial switches with different setting values.
The display loop displays the timing state of the time relay to a user in real time through a four-digit eight-segment nixie tube, so that the user can conveniently master the specific working state of the time relay.
The output circuit reads a time delay signal in the timing circuit, and if the signal of the end of the time delay is read, the internal snap relay is controlled to act.
As shown in fig. 1 and 2, the power supply circuit adopts an ac 220V input, and is stepped down to an ac 15V voltage through a transformer T1, a rectifier bridge B1 performs bridge full-wave rectification on the ac 15V voltage, and capacitors C1 and C2 filter the rectified voltage to output a 15V dc voltage. The three-terminal voltage-stabilizing integrated circuit Q1 stabilizes the 15V direct-current voltage, and outputs the 6V direct-current voltage after secondary filtering by the capacitors C3 and C4. The direct current 15V and 6V voltage supplies power for other loops.
As shown in fig. 1 and 3, the timing loop is composed of an asic IC1 and other peripheral electronic components. The resistor R2, the capacitors C5 and C6, the crystal oscillator Y1 and XTAL0 and XTAL1 ports of the special integrated circuit IC1 form an external oscillation circuit. The VDD port of the asic IC1 is the power supply pin, which is connected to a dc 6V voltage. The GND port of the asic IC1 is a ground pin and is connected to dc ground.
As shown in fig. 1 and 4, the delay time-base setting circuit is composed of resistors R7, 8421 dial switch KY5, diodes D18-D21 and a port e of an asic IC 1. The port e is in a high impedance state during programming, a pull-down resistor of about 70K is connected inside the port e, a diode or a gate circuit is formed by a dial switch KY5, diodes D18-D21 and an isolation resistor R7, and data set by a user are sent to the special integrated circuit IC1 to be latched. The asic IC1 sets the different delay time bases by reading the latched data. The dial switch KY5 uses 9 levels of 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111 and 1000 respectively to realize 0.1S, 1S, 0.1M, 1M, 0.1H, 1H, MS, HM and 0.01S of the delay time base.
As shown in fig. 1 and 4, the kilo-bit of the delay time setting circuit is composed of a resistor R3, an 8421 dial switch KY1, diodes D2-D5 and a port a of an asic IC 1; the hundred bits of the delay time setting loop consist of a resistor R4, an 8421 dial switch KY2, diodes D6-D9 and a port b of an application-specific integrated circuit IC 1; the ten bits of the delay time setting circuit consist of a resistor R5, an 8421 dial switch KY3, diodes D10-D13 and a port c of an application-specific integrated circuit IC 1; the unit of the delay time setting loop consists of a resistor R6, an 8421 dial switch KY4, diodes D14-D17 and a port D of an application-specific integrated circuit IC 1. The ports a-D are in a high impedance state during programming, a pull-down resistor of about 70K is connected inside the ports a-D, 4 diodes or gate circuits are formed through dial switches KY 1-KY 4, diodes D2-D17 and isolation resistors R3-R6, and data set by a user are sent to the special integrated circuit IC1 to be latched. The asic IC1 sets the different delay times by reading the latched data. KY1~ KY4 use 0000~1001 ten kinds of levels altogether to realize the figure 0~9 of the time delay time on one bit to thousand bits respectively. The ten levels 0000 to 1001 correspond to the numbers 0 to 9, and the ten levels 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, and 1001 correspond to 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9, respectively. Namely, the setting range of the delay time setting circuit is 0000-9999.
As shown in FIG. 1 and FIG. 5, the display loop is composed of 1 four-bit eight-segment nixie tube DS1, resistors R8-R15 and diodes D22-D25. Eight segment input ports a to h of a nixie tube DS1 are respectively connected to anode output driving ports a to h of an application-specific integrated circuit IC1 through resistors R8 to R15 and are used for displaying four-bit delay time 0000 to 9999 of a time relay; the bit input port of the nixie tube DS1 is connected to the D1-D4 cathode output driving port of the special integrated circuit IC1 through diodes D22-D25 respectively and is used for lighting the timing bit of the time relay.
As shown in fig. 1 and fig. 6, the output circuit is composed of a snap relay K1A, a diode D1, a resistor R1, a transistor Q2, and an OUT port of an asic IC 1. After the time relay is electrified, the OUT port outputs a low level, the coil of the snap relay K1A is in a release state, after the time delay reaches a set value, the OUT port outputs a high level, the triode Q2 is driven to be conducted through the resistor R1, the coil of the snap relay K1A is attracted, and the contact state is switched. The diode D1 is used for eliminating the self-excited voltage of the snap relay K1A and playing a role of protecting the relay, and the resistor R1 is the base current-limiting resistor of the triode Q2.
Because the utility model discloses digital display time relay's timing module adopts application specific integrated circuit, and consequently the internal circuit is simple, and has improved the reliability and the accuracy nature of machine by a wide margin, has saved producer's manual work and material cost greatly, reduces production and maintenance cost, has improved production efficiency and yield.
The foregoing is a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations are also considered as the protection scope of the present invention.
Claims (7)
1. A digital display time relay, comprising:
a delay time base setting circuit, which sets the delay time base by different set values of a group of 8421 dial switches, wherein 9 different delay time bases are provided;
a delay time setting loop, which sets the specific delay time from one bit to thousand bits through the different setting values of four groups of 8421 dial switches;
the timing loop comprises an application specific integrated circuit IC1, determines the delay time base and the delay time of the digital display time relay by reading the level signals of the delay time base setting loop and the delay time setting loop, and outputs a corresponding level trigger signal for the output loop after the delay time is finished;
the output loop comprises a snap relay and is used for reading a delay time signal in the timing loop, and the snap relay is controlled to act after the delay is finished;
the display loop comprises four-digit eight-segment nixie tubes and is used for displaying the timing state and the working state of the digital display time relay in real time;
and the power supply loop is used for supplying power to the display loop, the timing loop, the delay time base setting loop, the delay time setting loop and the output loop by reducing and rectifying the input alternating voltage into direct voltage.
2. The digital display time relay according to claim 1, characterized in that: the time delay time base setting loop comprises a resistor R7, an 8421 dial switch KY5 and diodes D18-D21; the port e of the special integrated circuit IC1 is in a high impedance state during programming, a 70K pull-down resistor is connected in the special integrated circuit IC1, a diode or a gate circuit is formed by an 8421 dial switch KY5, diodes D18-D21 and a resistor R7, data set by a user are sent to the special integrated circuit IC1 through the port e to be latched, and the special integrated circuit IC1 sets different delay time bases by reading the latched data; 8421 dial switch KY5 sets 0.1S, 1S, 0.1M, 1M, 0.1H, 1H, MS, HM, and 0.01S of the delay time base with 9 levels 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, and 1000, respectively.
3. The digital display time relay according to claim 1, characterized in that: the thousands of bits of the delay time setting circuit comprise a resistor R3, an 8421 dial switch KY1, diodes D2-D5 and a port a of an application-specific integrated circuit IC1, the hundreds of bits comprise a resistor R4, an 8421 dial switch KY2, diodes D6-D9 and a port b of an application-specific integrated circuit IC1, the tens of bits comprise a resistor R5, an 8421 dial switch KY3, diodes D10-D13 and a port c of an application-specific integrated circuit IC1, and the units comprise a resistor R6, an 8421 dial switch KY4, diodes D14-D17 and a port D of an application-specific integrated circuit IC 1; the ports a-D are in a high impedance state during programming, 70K pull-down resistors are connected inside the ports a-D, 4 diodes or gate circuits are formed by 8421 dial switches KY 1-KY 4, diodes D2-D17 and resistors R3-R6, data set by a user are sent to the special integrated circuit IC1 through the ports a-D to be latched, and different delay times are set by reading the latched data through the special integrated circuit IC 1; 8421 dial switches KY 1-KY 4 respectively use ten levels of 0000-1001 to realize thousands, hundreds, tens and units of digits 0-9 of delay time, so that the delay time range which can be set by the delay time setting circuit is 0000-9999.
4. The digital display time relay according to claim 1, characterized in that: the resistor R2, the capacitors C5 and C6, the crystal oscillator Y1 and XTAL0 and XTAL1 ports of the special integrated circuit IC1 form an external oscillation circuit in the timing loop; the VDD port of the special integrated circuit IC1 is a power supply pin and is connected with direct current 6V voltage; the GND port of the asic IC1 is a ground pin and is connected to dc ground.
5. The digital display time relay according to claim 1, characterized in that: the output circuit comprises a snap relay K1A, a diode D1, a resistor R1 and a triode Q2; after the digital display time relay is electrified, an OUT port of the special integrated circuit IC1 outputs a low level, a coil of the snap relay K1A is in a release state, after the time delay reaches a set value, the OUT port outputs a high level, the triode Q2 is driven to be conducted through the resistor R1, the coil of the snap relay K1A is attracted, and the contact state is switched; the diode D1 is used for eliminating the self-excited voltage of the snap relay K1A, and the resistor R1 is the base current-limiting resistor of the triode Q2.
6. The digital display time relay according to claim 1, characterized in that: the display loop is composed of 1 four-position eight-segment nixie tube DS1, resistors R8-R15 and diodes D22-D25; eight segment input ports a to h of a nixie tube DS1 are respectively connected to anode output driving ports a to h of an application-specific integrated circuit IC1 through resistors R8 to R15 and are used for displaying four-bit delay time 0000 to 9999 of a digital display time relay; the bit input port of the nixie tube DS1 is connected to the D1-D4 cathode output driving ports of the special integrated circuit IC1 through diodes D22-D25 respectively and used for lighting the timing bit of the digital display time relay.
7. The digital display time relay according to claim 1, characterized in that: the power supply loop supplies power to the display loop, the timing loop, the delay time base setting loop, the delay time setting loop and the output loop by reducing and rectifying the input 220V alternating voltage into 15V and 6V direct voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121144691.4U CN214799448U (en) | 2021-05-26 | 2021-05-26 | Digital display time relay |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121144691.4U CN214799448U (en) | 2021-05-26 | 2021-05-26 | Digital display time relay |
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| Publication Number | Publication Date |
|---|---|
| CN214799448U true CN214799448U (en) | 2021-11-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202121144691.4U Active CN214799448U (en) | 2021-05-26 | 2021-05-26 | Digital display time relay |
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| Country | Link |
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| CN (1) | CN214799448U (en) |
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2021
- 2021-05-26 CN CN202121144691.4U patent/CN214799448U/en active Active
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