CN214756330U

CN214756330U - Unmanned aerial vehicle wireless communication terminal

Info

Publication number: CN214756330U
Application number: CN202120110104.3U
Authority: CN
Inventors: 魏艺明; 朱铁林; 李洋; 黄静
Original assignee: Tianjin Aerospace Zhongwei Date Systems Technology Co Ltd
Current assignee: Tianjin Aerospace Zhongwei Date Systems Technology Co Ltd
Priority date: 2021-01-15
Filing date: 2021-01-15
Publication date: 2021-11-16
Anticipated expiration: 2031-01-15

Abstract

The invention provides an unmanned aerial vehicle wireless communication terminal, which comprises: the airborne terminal and the ground terminal are in wireless connection; the airborne terminal comprises a video coding module and a middle radio frequency module which is in bidirectional communication with the video coding module; the video coding module comprises a video coding chip and a video interface connected with the video coding chip, wherein the video interface comprises an SDI interface supporting 3Gb/s, HD, SD and SDI signal input and a CVBS interface supporting NTSC, PAL and SECAM video formats; the video coding module is also provided with a data interface, and the data interface is connected with the medium radio frequency module. The unmanned aerial vehicle wireless communication terminal is compatible with various video standards, integrates intermediate frequency and radio frequency, and is mainly applied to air-to-ground wireless communication occasions requiring miniaturization, low time delay, high video definition and good environmental adaptability.

Description

Unmanned aerial vehicle wireless communication terminal

Technical Field

The invention belongs to the technical field of unmanned aerial vehicle measurement and control communication, and particularly relates to an unmanned aerial vehicle wireless communication terminal.

Background

Real-time transmission video image is one of unmanned aerial vehicle's important effect, has all gained extensive application in fields such as electric power inspection, sea area monitoring, target reconnaissance. The aircraft carries an airborne terminal, the ground station is provided with a ground terminal, and a wireless link is established between the aircraft and the ground to realize the transmission of the video image data, the aircraft state and the control information of the task load. With the technical innovation of the industry, the unmanned system develops towards the trends of agility and diversification, data interfaces and video interfaces are gradually enriched, and stricter requirements are provided for the size, the weight and the power consumption of terminal equipment. In some industries and military fields, data interfaces are no longer limited to serial communication, and communication interfaces with standard protocols are used. According to different task requirements, video output of task loads is divided into high definition and standard definition, video interfaces and video types are not unified, and transmission equipment matched with the interfaces is often required to be replaced when different data interfaces and video types are dealt with. In order to improve the universality, the video transmission terminal has better interface compatibility and higher reliability, has various video coding and decoding capabilities, and is miniaturized as much as possible to adapt to airplanes with different loads.

Most of the existing terminal equipment can only accept high-definition or standard-definition video input, the high-definition input is an HDMI (high-definition multimedia interface), the input form is single, the HDMI interface form cannot be fastened, and the terminal equipment is not suitable for long-endurance and high-vibration industries. The standard definition video level standard is 1Vp-p, the anti-jamming capability is poor, in order to use under the complicated electromagnetic environment, some guidance and load manufacturers convert the single-ended standard definition video into difference during the design, and multiply amplify the level range, the difference video signal reduces the requirement for the transmission line, and can be transmitted through the micro rectangular connector, however, most terminals can only receive the single-ended standard definition video. The H.264 coding and decoding mode is mostly adopted after the video is sampled, the code rate after the compression is higher, and in the application of simultaneously transmitting the video by a plurality of machines, the occupied bandwidth is obviously increased by adopting the H.264 compression, which is not beneficial to long-distance transmission. In the process of transmitting video, flight tracks or loads are often adjusted, however, general video transmission equipment CAN only realize a graph transmission function, data transmission needs special equipment, data interfaces which CAN be supported are mostly serial ports without standard communication protocols, and standard protocol interfaces, such as a CAN interface, are used in some industrial applications. Structurally, the existing terminal mostly adopts a mode of separating a microwave front end from an intermediate frequency signal processor or adopts a receiving and transmitting separated antenna, so that the size is large and the wiring is complex.

The existing video transmission terminal has a simple transmission mode, cannot realize the function of data transmission at the same time, and generally cannot meet the requirements of an industrial onboard data link in the aspects of interface compatibility, volume power consumption, image quality and the like, so that a novel terminal with good expandability, miniaturization and high transmission reliability needs to be developed.

Disclosure of Invention

In view of the above, the present invention provides an unmanned aerial vehicle wireless communication terminal, so as to overcome the defects that the existing unmanned aerial vehicle wireless communication terminal has a single video input interface and cannot be compatible with high definition and standard definition input; the coding and decoding mode has low compression efficiency, large occupied link bandwidth and poor video fluency; the intermediate frequency processor is separated from the front end of the radio frequency microwave, so that the volume and the weight are large; generally, the data transmission function is not provided, or the data transmission interface is only limited to a serial port.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

an unmanned aerial vehicle wireless communication terminal comprises an airborne terminal and a ground terminal which are in wireless connection;

the ground terminal comprises a video decoding module and a middle radio frequency module which is in two-way communication with the video decoding module; the airborne terminal and the ground terminal are in wireless communication through the middle radio frequency module, and the ground terminal decodes the video and data information acquired by the airborne terminal through the video decoding module and sends the decoded video and data information to the display equipment and the processing equipment;

the video coding module comprises a video coding chip and a video interface which is connected with the video coding chip and is used for acquiring loaded video data, wherein the video interface comprises an SDI interface supporting 3Gb/s, HD, SD and SDI signal input and a CVBS interface supporting NTSC, PAL and SECAM video formats; the video coding module is also provided with a data interface used for acquiring flight control data and equipment information of flight control equipment, and the data interface is connected with the medium radio frequency module.

Furthermore, the medium radio frequency modules of the airborne terminal and the ground terminal respectively comprise an FPGA, a frequency conversion transceiver and a radio frequency switch, the FPGA is in two-way communication with the frequency conversion transceiver, the frequency conversion transceiver is provided with a transmitting circuit and a receiving circuit, the transmitting circuit and the receiving circuit are both connected with the radio frequency switch, and the FPGA is further connected with the radio frequency switch through a switch gating circuit.

Furthermore, a power amplifying circuit is arranged on the transmitting circuit;

the receiving circuit is a low-noise amplifier receiving circuit.

Furthermore, the FPGA of the airborne terminal is connected with the video coding chip through the SPI interface and the UART interface;

the data interface of the video coding module comprises an RS422 interface and a CAN interface, and the RS422 interface is connected with the FPGA through a level conversion circuit; and the CAN interface is connected with the FPGA after being converted into the SPI interface circuit by the CAN.

Furthermore, the airborne terminal is also correspondingly provided with a clock module;

the clock module comprises a crystal oscillator clock circuit used for providing clock signals for the FPGA and the frequency conversion transceiver and a crystal clock circuit used for providing clock signals for the video coding chip, the video interface chip and the data interface chip.

Furthermore, the crystal oscillator clock circuit fans out two same-frequency clock signals through the clock distributor and respectively inputs the two same-frequency clock signals to the FPGA and the frequency conversion transceiver, wherein a capacitance voltage division circuit is further arranged on the clock circuit which inputs the two same-frequency clock signals to the frequency conversion transceiver.

Further, the video decoding module comprises a video decoding chip and a video interface connected with the video decoding chip;

the video interface comprises a CVBS interface and an HDMI interface;

the video interface also comprises an SDI interface, and BT.1120 digital signals of the video decoding chip are converted into SDI interface output by an SDI interface conversion chip

The video decoding chip is connected with the FPGA;

the video decoding module is also provided with a data interface, and the data interface is connected with the FPGA.

Further, the video decoding chip is connected with the FPGA through a PCIE interface and a UART interface;

the video decoding chip is also externally connected with a network port for transmitting the video information to be decoded and the remote control and remote measuring information to the processing equipment.

Further, the data interface of the video decoding module comprises a serial port and a CAN interface, and is used for transmitting remote control, remote measurement and user data.

Furthermore, the ground terminal is also correspondingly provided with a clock module, the clock module comprises a master clock, the master clock fans out two paths of same-frequency clocks through a clock distributor, one path of same-frequency clocks is directly connected with the FPGA, the other path of same-frequency clocks is connected with a multi-path clock generator, and the FPGA is also connected with the clock generator through I²The signal output end of the clock generator is connected with the video decoding chip, the network port chip of the video interface, the frequency conversion transceiver, the data interface chip and the GTX module of the FPGA;

and a voltage division circuit is also arranged on a connecting circuit of the clock generator and the frequency conversion transceiver.

Compared with the prior art, the wireless communication terminal of the unmanned aerial vehicle has the following advantages:

(1) the wireless communication terminal of the unmanned aerial vehicle can simultaneously transmit multiple paths of videos, remote control data and remote measurement data, is compatible with multiple video standards, integrates intermediate frequency and radio frequency, and is mainly applied to air-to-ground wireless communication occasions requiring miniaturization, low time delay, high video definition and good environmental adaptability.

(2) The unmanned aerial vehicle wireless communication terminal adopts a video processing special chip, is matched with a high-definition video interface chip, a standard-definition video interface chip and a network interface chip, realizes hardware encoding and decoding, can also realize software encoding and decoding, adopts a single chip to adapt to single-ended and differential standard-definition input, and does not need a front differential to single-ended circuit; the video processing special chip adopts a new generation H.265 video coding and decoding technology, and compared with an H.264 coding and decoding mode, the code rate can be reduced by 50% at most, the video delay is lower, and the fluency is better; the time division duplex working mode and the radio frequency circuit design are adopted, and compared with the common frequency division duplex mode, the space occupation is smaller, the power consumption is lower, the integration of a digital circuit and an analog circuit is facilitated, and the equipment is more miniaturized; the high-reliability interface chip is adopted to realize serial communication, the interface chip of an automatic conversion protocol is adopted to realize CAN communication, and the chip is directly connected to the FPGA for data processing so as to reduce the interface conversion times of control and state signals and achieve the purpose of reducing time delay.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the invention without limitation. In the drawings:

fig. 1 is a schematic diagram of an application of a wireless communication terminal system according to an embodiment of the present invention;

fig. 2 is a schematic block diagram of an on-board terminal according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of an on-board terminal clock module according to an embodiment of the present invention;

fig. 4 is a schematic block diagram of a ground terminal according to an embodiment of the present invention;

fig. 5 is a schematic circuit diagram of a ground terminal clock module according to an embodiment of the present invention.

Detailed Description

It should be noted that the embodiments and features of the embodiments of the present invention may be combined with each other without conflict.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the orientation or positional relationship indicated in the drawings, which are merely for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be construed as limiting the invention. Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the invention, the meaning of "a plurality" is two or more unless otherwise specified.

In the description of the invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted", "connected" and "connected" are to be construed broadly, e.g. as being fixed or detachable or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the creation of the present invention can be understood by those of ordinary skill in the art through specific situations.

The invention will be described in detail with reference to the following embodiments with reference to the attached drawings.

The invention provides a miniaturized video transmission terminal implementation scheme with high coding compression efficiency for improving the video wireless transmission quality and interface compatibility, and is suitable for unmanned aerial vehicles and manned applications with long endurance, high vibration and high flight speed.

The invention is realized by the following scheme, and is divided into an airborne terminal and a ground terminal. The airborne terminal consists of a video coding module, a middle radio frequency transceiving module, a data interface module, a clock module and a power module; the ground terminal is composed of a video decoding module, a middle radio frequency transceiving module, a data interface module, a clock module and a power supply module. The terminal adopts a high-integration and multifunctional chip design, is compatible with common interfaces, and can achieve the purposes of high reliability and miniaturization.

When the system is used, the ground terminal and the airborne terminals realize wireless communication through the antennas, one ground terminal can be connected with one or more airborne terminals, and the single-point-to-single-point or single-point-to-multipoint image and data transmission function is realized, as shown in fig. 1, compared with a general single-point-to-single-point image transmission system, the system has the advantage that equipment is simplified.

The specific method comprises the following steps:

as shown in fig. 1, fig. 2, and fig. 4, an unmanned aerial vehicle wireless communication terminal includes an airborne terminal and a ground terminal that are wirelessly connected;

The video coding chip adopts a Haisi Hi3519 chip, which is an industry special video compression encoder adopting an advanced low-power-consumption process and a low-power-consumption architecture design, can realize real-time coding of H.265 multi-code streams, is matched with two video interface chips of high definition and standard definition, and can simultaneously compress and process two paths of videos. The airborne terminal can receive SDI and CVBS interface video input, an SDI receiving chip supports 3Gb/s, HD and SD SDI input, an internal integrated self-adaptive cable equalizer supports all formats of 1080p and 720 p. The standard-definition interface chip supports all formats of NTSC, PAL and SECAM, can realize automatic detection of input format and automatic adjustment of input signal level, the software register selects single-ended or differential input, the input range of the chip is expanded to 4Vp-p by building an input resistor 1/4 voltage division network, and the chip can automatically adapt to differential input from different manufacturers by matching with the function of automatic level adjustment. The SDI receiving chip converts high-definition input into BT.1120 code streams, the standard-definition interface chip converts standard-definition input into BT.656 code streams, and the BT.656 code streams are input into two paths of VI interfaces of Hi 3519. After Hi3519 compression coding, the single-path video code stream is about 1.6Mbps, the data volume is low, the requirement on a high-speed interface is reduced, and the single-path video code stream can be output to a middle radio frequency transceiver module through an SPI interface.

The medium radio frequency modules of the airborne terminal and the ground terminal respectively comprise an FPGA, a frequency conversion transceiver and a radio frequency switch, the FPGA is in two-way communication with the frequency conversion transceiver, the frequency conversion transceiver is provided with a transmitting circuit and a receiving circuit, the transmitting circuit and the receiving circuit are both connected with the radio frequency switch, and the FPGA is further connected with the radio frequency switch through a switch gating circuit.

The transmitting circuit is provided with a power amplifying circuit; the receiving circuit is a low-noise amplifier receiving circuit.

Frequency conversion transceivers of the medium radio frequency modules of the airborne terminal and the ground terminal adopt AD9361, and the AD9361 is a frequency agile transceiver integrating a 12-bit DAC and an ADC.

The middle radio frequency module of the airborne terminal adopts an FPGA + AD9361+ time division front end framework, the FPGA adopts an XC7A100T of Xilinx to connect with the Hi3519 and the AD9361 for data receiving and transmitting, and the functions of framing, decoding, modulation and demodulation and the like are realized. The AD9361 is a agile frequency transceiver integrating a 12-bit DAC and an ADC, realizes intermediate frequency and radio frequency signal conversion, has a channel bandwidth of 56MHz and a frequency range of 70MHz to 6GHz, is suitable for multi-band application, has a chip size of 10mm by 10mm, and has a high-integration zero intermediate frequency architecture, which is beneficial to miniaturization of the whole machine. The radio frequency front end adopts a time division structure, is divided into a receiving channel and a transmitting channel, is converged to the radio frequency switch, and adopts a single antenna for receiving and transmitting. The transmitting channel adopts a high-performance three-stage power amplifier RFPA2026, occupies small PCB area and can provide 2W output power. The radio frequency front end and the digital circuit are integrated on a board card, mutual interference of signals is easy to occur, and in order to improve the isolation degree, the following aspects are mainly considered: (1) the FPGA controls the radio frequency transceiving channel to be opened at different times so as to prevent mutual interference of transceiving, and the RFPA2026 has an enabling function, so that compared with a method of directly powering on and powering off a power amplifier chip, the requirement of time slot fast switching can be met; (2) the ground division prevents mutual interference of digital and analog signals, the FPGA and the AD9361 refer to a digital ground, the radio frequency front end refers to an analog ground, and the ground is divided from the lower part of a balun device at the output end of the AD9361, so that discontinuity of the radio frequency signal reference ground caused by random division is prevented; (3) an isolator is added at the output end of the power amplifier chip, and a multi-stage filter and an amplitude limiter are arranged on a receiving path, so that out-of-band rejection is improved.

The FPGA of the airborne terminal is connected with the video coding chip through the SPI interface and the UART interface;

The data interface of the airborne terminal CAN be connected with the RS422 and CAN interfaces, the LTC2864 realizes the conversion between the 3.3V UART level standard and the RS422 level standard, and the interfaces CAN bear 60V voltage. MCP25625 is an interface conversion chip supporting CAN 2.0B protocol, has the highest transmission rate of 1Mb/s, has an automobile-level temperature range, CAN bear transient strong interference by being matched with a TVS (transient voltage suppressor) tube, and CAN replace a scheme that a controller and a transceiver are separated. The chip CAN realize the conversion from the CAN interface to the SPI interface, and the development process of the CAN protocol at the FPGA end is omitted. The data interface chip is directly connected to the FPGA 3.3V BANK without passing through the Hi3519, interface conversion is reduced, and data transmission delay is reduced.

As shown in fig. 3, the onboard terminal is further correspondingly provided with a clock module; the clock module comprises a crystal oscillator clock circuit used for providing clock signals for the FPGA and the frequency conversion transceiver and a crystal clock circuit used for providing clock signals for the video coding chip, the video interface chip and the data interface chip.

The crystal oscillator clock circuit fans out two same-frequency clock signals through the clock distributor and respectively inputs the two same-frequency clock signals to the FPGA and the frequency conversion transceiver, wherein a capacitance voltage division circuit is further arranged on the clock circuit which inputs the two same-frequency clock signals to the frequency conversion transceiver.

In order to ensure the quality of a clock signal and prevent overlarge frequency offset, a clock module of the airborne terminal selects a TG5501CA temperature compensation crystal oscillator of EPSON company as a clock source, the temperature stability of the crystal oscillator is +/-0.28 ppm, and the clock module is matched with a phase-locked loop module of an FPGA to be used and can adapt to the flight speed of Mach. The clock distributor adopting ultra-low additional jitter fans out the same-frequency clock to the FPGA and the AD9361, and the total phase noise can meet the requirement of the AD9361 on the clock phase noise. A capacitor voltage-dividing circuit is arranged in front of the clock input of the AD9361, and the clock signal is converted into the required 1.3 Vp-p. The Hi3519 and other chips have low requirements on clock precision, and a crystal is adopted to provide a clock for improving the starting speed of an operating system.

The airborne terminal is also provided with a power supply module, wherein the first-stage power supply chip is LT8640S, the chip can bear the input of the highest 42V and can provide the output current of the maximum 6A, and a special power supply filter and a capacitor are arranged in front of the chip to play a good interference suppression effect. In order to reduce the area of the PCB occupied by the power supply chip, the multi-channel DCDC power supply chips LTM4643 and LTM4622 with high integration level are adopted to supply power for the chips such as the FPGA, the Hi3519 and the like, and the power supply chip has the advantages of small volume, few peripheral circuits and strong power supply capability and is suitable for miniaturized design. The LDO power supply chip ADP1755 is adopted to supply power for the AD9361 core, the power supply output ripple is small, the voltage is stable, and the method can adapt to the condition of rapid load change of the AD 9361.

The video decoding module comprises a video decoding chip and a video interface connected with the video decoding chip;

the video interface comprises a CVBS interface and an HDMI interface; the video interface also comprises an SDI interface, and BT.1120 digital signals of the video decoding chip are converted into SDI interface output by an SDI interface conversion chip

The video decoding chip is connected with the FPGA; the video decoding module is also provided with a data interface, and the data interface is connected with the FPGA.

The video decoding chip is connected with the FPGA through a PCIE interface and a UART interface; the video decoding chip is also externally connected with a network port for transmitting the video information to be decoded and the remote control and remote measuring information to the processing equipment.

The video decoding module of the ground terminal takes Hi3536 as a core, a chip integrates a high-performance video image processing engine with a plurality of complex image processing algorithms, and the video decoding module has double-path high-definition display output capacity, can realize the hardware decoding of a video image H.265 protocol, directly outputs CVBS and HDMI interface videos, and does not need an external interface chip. In order to realize the conversion from single end to differential of standard definition video, a high-speed differential amplifier is adopted, the chip has a-3 dB bandwidth of 350MHz, the standard definition format video frequency is covered, the output phase is matched and balanced, and the EMI can be reduced. The negative pole input of the chip is grounded in a matching mode, the positive pole input of the chip is connected with the CVBS output pin of the Hi3536, the gain can be adjusted through the feedback resistor, 75 omega parallel resistors are added to the ground at the differential output end respectively, and impedance matching of the external 75 omega is achieved. For high definition video, Hi3536 may output bt.1120 parallel digital signals in compliance with the input standard of SDI transmitting chip, in addition to HDMI direct output. The SDI transmitting chip can realize conversion of BT.1120 interface into 3Gb/s, HD and SD SDI output, supports all formats of 1080p and 720p, configures a software register thereof through a GSPI interface, and converts BT.1120 digital signals into SDI interface output. Hi3536 does not have an SPI module, and the configuration can be realized by simulating the GSPI time sequence through a chip GPIO. Video, remote control and remote measurement data are transmitted between the Hi3536 and the FPGA through PCIE and UART interfaces, the PCIE 2.0X2 interface of the Hi3536 is connected with a GTX module of the FPGA, each channel supports 500MB/s rate, and high-speed data transmission can be guaranteed. The Hi3536 can transmit the video information to be decoded and the remote control and remote measurement information to a computer end through an external network port chip, and the network port chip is realized by adopting a gigabit Ethernet chip. The gigabit Ethernet chip is connected with the RGMII interface of the Hi3536, the chip is provided with an internal level converter, the outside only needs 3.3V single power supply for power supply, the gigabit Ethernet output interface is self-adaptive to receiving and transmitting, special receiving and transmitting pins are not needed to be distinguished, the gigabit Ethernet chip can be used as gigabit connection or hundred-megabyte connection, software decoding is realized through H.265 video decoders such as VLC, hardware decoding and software decoding can be carried out simultaneously, and multiple using modes are provided for users.

The data interface of the video decoding module comprises a serial port and a CAN interface and is used for transmitting remote control, remote measurement and user data.

The ground terminal is also correspondingly provided with a clock module, the clock module comprises a master clock, the master clock fans out two paths of same-frequency clocks through a clock distributor, one path of the same-frequency clocks is directly connected with the FPGA, the other path of the same-frequency clocks is connected with a multi-path clock generator, and the FPGA is also connected with the FPGA through an I²The signal output end of the clock generator is connected with the video decoding chip, the network port chip of the video interface, the frequency conversion transceiver, the data interface chip and the GTX module of the FPGA; and a voltage division circuit is also arranged on a connecting circuit of the clock generator and the frequency conversion transceiver.

As shown in fig. 5, the clock module of the ground terminal provides a clock for the whole terminal in a clock tree manner, thereby reducing the use of excessive kinds of crystals. The crystal oscillator TG5501CA is used as a main clock, a fan-out common-frequency clock is used through a clock distributor, one circuit is connected to the FPGA to enable the FPGA to be electrified and started, the other circuit is connected to a plurality of clock generators, the phase of each clock generator is jittered by 1ps, eight clocks with the highest 700MHz and different level standards can be provided, and the output phase noise of the clocks meets the requirement of the AD 9361. After the FPGA is started, a clock generator is configured through I2C to generate clocks needed by Hi3536, a network port chip, AD9361 and the like.

The power module and the medium radio frequency transceiver module of the ground terminal are similar to an airborne terminal in the structure, and the ground terminal needs to realize more functions, so that the FPGA adopts XC7K325T with richer resources.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the invention, so that any modifications, equivalents, improvements and the like, which are within the spirit and principle of the present invention, should be included in the scope of the present invention.

Claims

1. An unmanned aerial vehicle wireless communication terminal which characterized in that: the system comprises an airborne terminal and a ground terminal which are in wireless connection;

2. The unmanned aerial vehicle wireless communication terminal of claim 1, wherein: the medium radio frequency modules of the airborne terminal and the ground terminal respectively comprise an FPGA, a frequency conversion transceiver and a radio frequency switch, the FPGA is in two-way communication with the frequency conversion transceiver, the frequency conversion transceiver is provided with a transmitting circuit and a receiving circuit, the transmitting circuit and the receiving circuit are both connected with the radio frequency switch, and the FPGA is further connected with the radio frequency switch through a switch gating circuit.

3. The unmanned aerial vehicle wireless communication terminal of claim 2, wherein: the transmitting circuit is provided with a power amplifying circuit;

the receiving circuit is a low-noise amplifier receiving circuit.

4. The unmanned aerial vehicle wireless communication terminal of claim 2, wherein: the FPGA of the airborne terminal is connected with the video coding chip through the SPI interface and the UART interface;

5. The unmanned aerial vehicle wireless communication terminal of claim 2, wherein: the airborne terminal is also correspondingly provided with a clock module;

6. The unmanned aerial vehicle wireless communication terminal of claim 5, wherein: the crystal oscillator clock circuit fans out two same-frequency clock signals through the clock distributor and respectively inputs the two same-frequency clock signals to the FPGA and the frequency conversion transceiver, wherein a capacitance voltage division circuit is further arranged on the clock circuit which inputs the two same-frequency clock signals to the frequency conversion transceiver.

7. The unmanned aerial vehicle wireless communication terminal of claim 2, wherein: the video decoding module comprises a video decoding chip and a video interface connected with the video decoding chip;

the video interface comprises a CVBS interface and an HDMI interface;

The video decoding chip is connected with the FPGA;

8. The unmanned aerial vehicle wireless communication terminal of claim 7, wherein: the video decoding chip is connected with the FPGA through a PCIE interface and a UART interface;

9. The unmanned aerial vehicle wireless communication terminal of claim 7, wherein: the data interface of the video decoding module comprises a serial port and a CAN interface and is used for transmitting remote control, remote measurement and user data.

10. The unmanned aerial vehicle wireless communication terminal of claim 7, wherein: the ground terminal is also correspondingly provided with a clock module, the clock module comprises a master clock, the master clock fans out two paths of same-frequency clocks through a clock distributor, one path of the same-frequency clocks is directly connected with the FPGA, the other path of the same-frequency clocks is connected with a multi-path clock generator, and the FPGA is also connected with the FPGA through an I²The signal output end of the clock generator is connected with the video decoding chip, the network port chip of the video interface, the frequency conversion transceiver, the data interface chip and the GTX module of the FPGA;