CN214753395U - Integrated structure of zero sequence phase sequence ceramic capacitor chip integration - Google Patents

Abstract

An integrated structure integrated by a zero sequence phase sequence ceramic capacitor chip comprises the phase sequence ceramic capacitor chip and the zero sequence ceramic capacitor chip; the end surfaces of two ends of the phase sequence ceramic capacitor chip and the zero sequence ceramic capacitor chip are respectively coated with a conductive layer, and electrodes are respectively welded on the conductive layers; conductive wafers which cover end faces and are parallel to the end faces are respectively arranged on the electrodes at the two ends of the phase sequence ceramic capacitor chip and the zero sequence ceramic capacitor chip; the phase sequence ceramic capacitor chip is connected with the zero sequence ceramic capacitor chip in series; a conductive wafer is shared between the connecting ends of the phase sequence ceramic capacitor chip and the zero sequence ceramic capacitor chip; and a conductive mounting bracket is arranged on a conductive wafer shared between the connecting ends of the phase sequence ceramic capacitor chip and the zero sequence ceramic capacitor chip. The invention has uniform electric field distribution, and avoids signal interference caused by nonuniform electric field distribution.

Description

Integrated structure of zero sequence phase sequence ceramic capacitor chip integration

Technical Field

The invention relates to the field of electronic components, in particular to a series structure of a high-voltage ceramic capacitor, a phase sequence ceramic capacitor chip and a zero sequence ceramic capacitor chip.

Background

Ceramic capacitors are generally in the form of a sheet or cylindrical structure. And (3) carrying out molding sintering by taking a ceramic material as a medium, then coating conductive layers at two ends, then arranging electrodes on the conductive layers, and then packaging by insulating resin. The electrode is used as the leading-out terminal of the ceramic capacitor and is connected with an external circuit. The high-voltage pulse ceramic capacitor is generally used in the power industry or the military industry and can play the roles of metering, voltage division, energy storage and the like. A high-voltage ceramic capacitor used in high-voltage intelligent power grid comprises a ceramic capacitor chip, wherein two ends of the ceramic capacitor chip are coated with conductive layers, and the conductive layers are generally formed by coating silver paste and then sintering. An electrode is provided at the center of the conductive layer. The electrode structure generally includes a circular base in contact with the conductive layer, and an electrode connection portion provided on the circular base and connected to an external circuit. And then, an insulating resin layer is poured outside the ceramic capacitor chip and the electrodes, and after pouring, only one end of the electrode connecting part is exposed outside the insulating resin layer so as to be conveniently connected with an external circuit. The ceramic capacitor is used in a high-voltage intelligent power grid, has stable electrical performance and reliable work, but has some defects. In the actual use process, the ceramic capacitor has large interference on the transmission signal of the smart grid, so that the transmission signal distortion is caused, and the requirement of the smart grid on the transmission signal precision cannot be met. The analysis shows that the bad phenomena causing larger interference are all caused by the uneven distribution of the power plant of the ceramic capacitor. Therefore, how to make the electric field generated by the ceramic capacitor uniformly distributed in the using process becomes a technical problem to be solved urgently.

Disclosure of Invention

The technical problem to be solved by the invention is to provide an integrated structure of a zero sequence ceramic capacitor and a phase sequence ceramic capacitor chip which are connected in series, when the integrated structure is used in a high-voltage smart grid, electric fields at two ends of electrodes of a ceramic capacitor can be uniformly distributed, and the interference on transmission signals is reduced under a working state.

In order to solve the technical problems, the technical scheme provided by the invention is an integrated structure integrated by a zero sequence phase sequence ceramic capacitor chip, which is characterized by comprising a phase sequence ceramic capacitor chip and a zero sequence ceramic capacitor chip; the end surfaces of two ends of the phase sequence ceramic capacitor chip and the zero sequence ceramic capacitor chip are respectively coated with a conductive layer, and electrodes are respectively welded on the conductive layers; conductive wafers which cover end faces and are parallel to the end faces are respectively arranged on the electrodes at the two ends of the phase sequence ceramic capacitor chip and the zero sequence ceramic capacitor chip; the phase sequence ceramic capacitor chip is connected with the zero sequence ceramic capacitor chip in series; a conductive wafer is shared between the connecting ends of the phase sequence ceramic capacitor chip and the zero sequence ceramic capacitor chip; and a conductive mounting bracket is arranged on a conductive wafer shared between the connecting ends of the phase sequence ceramic capacitor chip and the zero sequence ceramic capacitor chip.

The distance between the conductive wafer and the end faces of the two ends of the phase sequence ceramic capacitor chip and the zero sequence ceramic capacitor chip is 0.3-0.6 mm.

The mounting bracket is fixedly mounted on the conductive wafer through screws, and the mounting connecting end of the mounting bracket is positioned on the outer side of the edge of the conductive wafer.

The conductive wafer is provided with at least one circle of exhaust through holes which are uniformly distributed at intervals around the electrode.

And leading-out wires are welded on the electrodes at the ends, connected with the outside, of the phase sequence ceramic capacitor chip and the zero sequence ceramic capacitor chip, and a connecting plug is arranged at the end, connected with the outside, of the leading-out wires.

And a connecting hole provided with an internal thread is formed in the connecting plug.

And coating a high-temperature glass glaze layer on the peripheral surfaces of the zero-sequence ceramic capacitor chip and the phase-sequence ceramic capacitor chip.

In practical use, the integrated zero sequence phase sequence ceramic capacitor chip is connected with an external high-voltage input end through a conductive mounting bracket, the zero sequence capacitor is connected with a protection circuit, and the phase sequence capacitor is connected with a working circuit.

The phase sequence ceramic capacitor chip and the zero sequence ceramic capacitor chip are connected in series, the conductive layer is completely covered by adding the conductive wafer on the end surface, and the opposite area of the conductive wafer is the area of the conductive layer at the two ends of the ceramic capacitor chip. Because ceramic capacitor chip is cylindric structure, the conducting layer at its both ends also is just to setting up, so, can avoid the inhomogeneous phenomenon of electric field distribution that the dislocation of both ends electrode arouses through the setting of electrically conductive disk, the electric field passes through the just right electrically conductive disk edge evenly distributed at both ends, realizes ceramic capacitor electric field evenly distributed to avoid the signal interference because of ceramic capacitor electric field maldistribution leads to the fact high-voltage smart power grids.

Drawings

Fig. 1 is a schematic diagram of the explosive structure of the present invention.

FIG. 2 is a schematic view of an assembly structure of the present invention.

Detailed Description

With respect to the above technical solutions, preferred embodiments are described in detail with reference to the drawings.

The ceramic capacitor chip 1 is a phase-sequence capacitor ceramic capacitor chip, has a cylindrical shape, and is formed by molding and sintering a ceramic material. The conducting layer of even coating certain thickness on ceramic capacitor chip's both ends terminal surface, the material of conducting layer generally is silver, generally can form the conducting layer by carrying out the sintering again on ceramic capacitor chip's both ends terminal surface with silver thick liquid coating. And an electrode 3 fixedly arranged on the central part of the conductive layer by welding. In this embodiment, the electrode 3 is a columnar structure, and the outer diameter of the end welded with the conductive layer is larger than the outer diameter of the end connected with the external circuit, so that the welding contact area between the electrode 3 and the conductive layer is increased, and the electrode is firmly fixed.

And the conductive wafers 4 are respectively fixedly installed on the electrodes at the two ends of the ceramic capacitor chip 1, are arranged in parallel with the end faces at the two ends of the ceramic capacitor chip at intervals, and have a gap spacing of about 0.3-0.6 mm with the conductive layer, and usually have a gap spacing of 0.5 mm. In this embodiment, the voltage equalizing device is a conductive wafer, and the outer diameter of the conductive wafer is slightly larger than the diameter of the ceramic capacitor chip. The conductive wafers arranged on the electrodes at the two ends of the ceramic capacitor chip are the same in material and size, and the distances from the conductive layers of the ceramic capacitor chip after the conductive wafers are arranged are the same. The outer threads are arranged on the periphery of the electrode, and the conductive wafer is fixed on the electrode through threaded connection, so that the conductive wafer is convenient to mount and fix.

At least one circle of through holes 41 which are uniformly distributed at intervals are arranged on the conductive wafer around the electrodes. During pouring, air bubbles in the pouring material between the conductive wafer and the conductive layer of the ceramic capacitor chip can be discharged outwards through the through holes in the conductive wafer, so that the bad phenomenon that the gap is not filled by the pouring material or the bubbles in the pouring material between the conductive wafer and the conductive layer of the ceramic capacitor chip are generated is avoided. Through the voltage-sharing device, the electrode dead areas at the two ends of the ceramic capacitor chip are the areas of the complete conducting layers, and the phenomenon that the electrodes at the two ends of the ceramic capacitor chip are uneven due to dislocation when the electrodes are used only is avoided. By adding the voltage-sharing device, the actual opposite area of the electrode is the area of the conducting layer, and the electric fields at the two ends of the ceramic capacitor chip are uniformly distributed. The bad phenomenon that the electric field of the ceramic capacitor is unevenly distributed to cause signal interference and transmission in the use of a high-voltage smart power grid is avoided, and the working reliability is improved.

The ceramic capacitor chip 1 is connected with a ceramic capacitor chip 5 in series. The ceramic capacitor chip 5 is a zero sequence capacitor ceramic capacitor chip, and is a cylindrical ceramic chip, conductive layers are coated at two ends of the ceramic capacitor chip, electrodes 6 are welded on the conductive layers at two ends of the ceramic capacitor chip 5, and the ceramic capacitor chip 5 is connected in series on the conductive wafer at one end of the ceramic capacitor chip 1 through the electrodes 6. The electrode 6 at the other end of the ceramic capacitor chip 5 is connected with a conductive wafer 7, the conductive wafer 7 is arranged in parallel with the end faces of the two ends of the ceramic capacitor chip 5, the conductive wafer covers the end face of the ceramic capacitor chip 5, the gap between the conductive wafer 7 and the conductive layer of the ceramic capacitor chip 5 is about 0.3-0.6 mm, and the gap spacing is usually 0.5 mm.

A screw 31 and a screw 61 are screwed to the electrode 3 and the electrode 6 at the end of the ceramic capacitor chip 1 to which the ceramic capacitor chip 5 is not connected, and a lead wire 32 and a lead wire 62 are fixedly connected to the screw 31 and the screw 61, respectively. A connection plug 33 and a connection plug 63 are fixedly connected to one end of the lead wire 32 and the lead wire 62, respectively, which are connected to the outside. The connecting plug 33 and the connecting plug 63 have the same structure, and a connecting hole is formed in the connecting plug and internally provided with an internal thread. When the leading-out wire is connected with the outside, the external connecting part is only required to be connected to the connecting plug of the leading-out wire through threads.

A conductive mounting bracket 8 is fixed on the conductive wafer 4 connected with the ceramic capacitor chip 1 and the ceramic capacitor chip 5 through a screw 81. The installation connecting end of the installation support 8 is positioned at the outer side of the conductive wafer 4, and the installation support connecting end is provided with an installation hole. When the phase-sequence capacitor is used, the phase-sequence capacitor is connected with the working circuit.

In order to enhance the insulating property, a high-temperature glass glaze layer is coated on the outer peripheral surfaces of the zero-sequence ceramic capacitor chip and the phase-sequence ceramic capacitor chip to prevent the creepage of the edges.

Claims (7)

1. An integrated structure integrated by zero sequence phase sequence ceramic capacitor chips is characterized by comprising phase sequence ceramic capacitor chips and zero sequence ceramic capacitor chips; the end surfaces of two ends of the phase sequence ceramic capacitor chip and the zero sequence ceramic capacitor chip are respectively coated with a conductive layer, and electrodes are respectively welded on the conductive layers; conductive wafers which cover end faces and are parallel to the end faces are respectively arranged on the electrodes at the two ends of the phase sequence ceramic capacitor chip and the zero sequence ceramic capacitor chip; the phase sequence ceramic capacitor chip is connected with the zero sequence ceramic capacitor chip in series; a conductive wafer is shared between the connecting ends of the phase sequence ceramic capacitor chip and the zero sequence ceramic capacitor chip; and a conductive mounting bracket is arranged on a conductive wafer shared between the connecting ends of the phase sequence ceramic capacitor chip and the zero sequence ceramic capacitor chip.

2. The integrated structure of the zero sequence phase sequence ceramic capacitor chip assembly according to claim 1, wherein the distance between the conductive wafer and the end surfaces of the two ends of the phase sequence ceramic capacitor chip and the zero sequence ceramic capacitor chip is 0.3-0.6 mm.

3. The integrated structure of the zero sequence phase sequence ceramic capacitor chip assembly according to claim 2, wherein the mounting bracket is fixedly mounted on the conductive wafer by screws, and the mounting connection end of the mounting bracket is located outside the edge of the conductive wafer.

4. The integrated structure of zero sequence phase sequence ceramic capacitor chip assembly according to claim 1, wherein the conductive wafer has at least one circle of a plurality of exhaust through holes uniformly distributed at intervals around the electrodes.

5. The integrated structure of the zero sequence phase sequence ceramic capacitor chip assembly according to claim 1, wherein the outgoing lines are welded to the electrodes at the ends of the phase sequence ceramic capacitor chip and the zero sequence ceramic capacitor chip connected to the outside, and the connecting plug is disposed at the end of the outgoing line connected to the outside.

6. The integrated structure of zero sequence phase sequence ceramic capacitor chip assembly of claim 5, wherein the connecting plug is provided with a connecting hole with internal threads.

7. The integrated structure of zero sequence phase sequence ceramic capacitor chip assembly according to claim 1, wherein a high temperature glass glaze layer is coated on the outer peripheral surfaces of the zero sequence ceramic capacitor chip and the phase sequence ceramic capacitor chip.

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