CN214670194U - Multichannel signal acquisition display device - Google Patents
Multichannel signal acquisition display device Download PDFInfo
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- CN214670194U CN214670194U CN202121275495.0U CN202121275495U CN214670194U CN 214670194 U CN214670194 U CN 214670194U CN 202121275495 U CN202121275495 U CN 202121275495U CN 214670194 U CN214670194 U CN 214670194U
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Abstract
The utility model discloses a multi-channel signal acquisition display device, which comprises at least one signal acquisition terminal, a signal receiving terminal and a display device; one end of the signal acquisition terminal is connected with an Ethernet port of the experiment table, and the other end of the signal acquisition terminal is connected with a signal to be tested of the experiment table through a BNC test wire, so that an analog input signal is obtained; the signal acquisition terminal converts the analog input signal into a digital signal; the digital signal is transmitted to a signal receiving terminal through the Ethernet; the signal receiving terminal converts the digital signal into a data waveform; the signal receiving terminal is connected with a display device for displaying data waveforms. The utility model discloses utilize distributed multinode analog-to-digital conversion and VGA display technology based on ethernet, solved and need carry out synchronous high-speed collection and the problem that shows to a plurality of analog signal that distribute in the different positions in space among the electronic technology experiment teaching.
Description
Technical Field
The utility model relates to a controller field especially relates to a multichannel signal acquisition display device.
Background
In the course of experiment teaching of electronic technology class course, the analog signal that student used distributed experiment bench output often needs to be gathered and observed, generally adopts the mode that every experiment bench is equipped with an oscilloscope at present to carry out the waveform observation. Output signals of one or more bench positions distributed in different spaces are required to be synchronously acquired and displayed in the experimental process, an oscilloscope data acquisition line for a laboratory at present is generally about 1 meter, remote data acquisition is not supported generally, and signals of the bench positions distributed in different spaces cannot be synchronously acquired, displayed and compared and analyzed.
The multi-channel signal acquisition is widely applied to a video monitoring system, but the system needs a plurality of terminal cameras for information acquisition and is not suitable for analog signal acquisition and display of a multi-station experiment table.
In the field of distributed control systems, analog signals of a plurality of test points need to be monitored simultaneously, an analog-to-digital (AD) converter is generally adopted to collect the analog signals and convert the analog signals into digital signals, the digital signals are transmitted to a control end by adopting 485 buses and the like, the control end generally needs special data receiving equipment to receive data, and needs a computer and special human-computer interaction software to process and display the data; in addition, the 485 transmission rate is low, so that the high-speed data acquisition and real-time synchronous display of a plurality of stations in a laboratory are not facilitated.
Disclosure of Invention
The utility model provides a multichannel signal acquisition display device to overcome the problem of electronic technology experiment teaching in-process to the synchronous acquisition and the real-time demonstration of a plurality of station output signal of spatial distribution formula.
In order to realize the purpose, the technical scheme of the utility model is that:
a multi-channel signal acquisition display device, comprising: the system comprises at least one signal acquisition terminal, a signal receiving terminal and a display device;
the signal acquisition terminal is connected with an analog signal to be tested of the experiment table position through a BNC test wire so as to obtain an analog input signal;
the signal acquisition terminal converts the analog input signal into a digital signal;
the digital signal is transmitted to the signal receiving terminal through the Ethernet;
the signal receiving terminal converts the digital signal into a data waveform;
the signal receiving terminal is connected with a display device for displaying the data waveform;
the signal acquisition terminal comprises a signal conditioning circuit, an analog-to-digital conversion circuit, a first FPGA unit, a first Ethernet adaptation circuit, at least two first working indicator lamps, a first control key and a first power supply circuit;
the signal receiving terminal comprises a second Ethernet adaptive circuit, a second FPGA unit, a VGA driving circuit, at least two second control keys, at least one second working indicator lamp and a second power supply circuit.
Further, the signal conditioning circuit conditions the analog input signal within the range of-5 v to 5v into the analog output signal of 0v to 1 v;
the analog-to-digital conversion circuit converts the 0 v-1 v analog output signal into an 8-bit digital signal;
the first FPGA unit receives a data acquisition instruction transmitted by an Ethernet network so as to control the signal conversion of the digital-to-analog conversion circuit, and stores the 8-bit digital signal in the first FPGA unit to form a data packet.
Further, the data packet in the first FPGA unit is stored in the second FPGA unit through the second ethernet adapter circuit;
the VGA driving circuit converts the digital signals in the data packet into data waveforms.
Further, the data acquisition instruction comprises a start acquisition instruction and a sampling clock rate instruction.
Further, the input interface of the signal acquisition terminal is a 2-path BNC interface and can be connected with a BNC test pen; the output interface of the signal acquisition terminal is a 1-path gigabit Ethernet port and can be connected with the network port of the experiment table through a network cable.
Further, the input port of the signal receiving terminal is a 1-path gigabit Ethernet port; and the output port of the signal receiving terminal is a VGA interface and can be connected with a display device.
Further, the first work indicator lamp comprises at least one sampling rate indicator lamp and a sampling instruction indicator lamp.
Further, the first control key is a manual acquisition key;
the second control key comprises an acquisition control key and a sampling rate selection key which correspond to the sampling rate indicator lamp.
Further, the display device is a projector or a display.
Has the advantages that: the utility model discloses utilize distributed multinode analog-to-digital conversion and VGA display technology based on ethernet, the problem that needs to carry out synchronous high-speed collection and demonstration to a plurality of analog signal that distribute in the different positions in space among the electronic technology experiment teaching of having solved. Synchronous starting of data acquisition instructions and data collection are achieved through the Ethernet, data sampling of distributed nodes is achieved through high-speed analog-to-digital conversion, discrete data quantity uploaded by a plurality of spatial sampling points is synchronously displayed through waveforms through the VGA display technology, and high-speed synchronous acquisition and synchronous display of spatial multi-node analog data are achieved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.
FIG. 1 is a general schematic diagram of the system of the present invention;
fig. 2 is a structural diagram of the signal acquisition terminal of the utility model;
fig. 3 is a structure diagram of the signal receiving terminal of the present invention.
Wherein, 1, BNC test line.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
The embodiment provides a multi-channel signal acquisition and display device, as shown in fig. 1-3, including: the system comprises at least one signal acquisition terminal, a signal receiving terminal and a display device;
the signal acquisition terminal is connected with an analog signal to be tested of the experiment table position through a BNC test wire so as to obtain an analog input signal;
the signal acquisition terminal converts the analog input signal into a digital signal;
the digital signal is transmitted to the signal receiving terminal through the Ethernet;
the signal receiving terminal converts the digital signal into a data waveform;
and the signal receiving terminal is connected with a display device for displaying the data waveform.
In a specific embodiment, the number of the signal acquisition terminals is 4.
In a specific embodiment, the signal acquisition terminal comprises a signal conditioning circuit, an analog-to-digital conversion circuit, a first FPGA unit, a first Ethernet adaptation circuit, at least two first working indicator lamps, a first control key and a first power circuit; the signal acquisition terminal has two working modes of instruction response sampling transmission and manual sampling transmission. The first FPGA unit receives 8-bit binary digital signals and stores the 8-bit binary digital signals in an RAM (random access memory) in the first FPGA unit, each sampling clock in the first FPGA unit stores 1 bit of 8-bit data, 512 sampling data are one frame, a first data packet is formed under the control of the first FPGA unit and is uploaded to an Ethernet through an Ethernet adaptive circuit, and instruction response type sampling transmission is realized. The first control key of the signal acquisition terminal adopts a non-self-locking structure, and when the sampling instruction from the Ethernet is not available, the signal acquisition terminal starts to execute sampling and transmission operation for 1 time, namely manual sampling transmission, after 1 control key is pressed every time the signal acquisition terminal equivalently receives 1 sampling instruction.
The signal conditioning circuit conditions the analog input signal in the range of-5 v into the analog output signal of 0 v-1 v;
the analog-to-digital conversion circuit converts the 0 v-1 v analog output signal into an 8-bit digital signal, and the sampling clock of the analog-to-digital conversion circuit is 1M-100M;
the first FPGA unit receives a data acquisition instruction transmitted by an Ethernet network so as to control the signal conversion of the digital-to-analog conversion circuit, and stores the 8-bit digital signal in the first FPGA unit to form a first data packet.
In a specific embodiment, the signal receiving terminal comprises a second ethernet adapter circuit, a second FPGA unit, a VGA driver circuit, at least two second control keys, at least one second working indicator light and a second power circuit;
the first data packet in the first FPGA unit is stored in the second FPGA unit through the second Ethernet adapting circuit;
and meanwhile, the second FPGA unit packs the acquisition starting signal and the sampling rate parameter into a second data packet according to the control information input by the second control key and sends the second data packet to the Ethernet through the Ethernet adaptive circuit.
The VGA driving circuit converts the digital signals in the data packet into data waveforms.
In a specific embodiment, the data acquisition instruction comprises an acquisition start instruction and a sampling clock rate instruction, and is used for controlling signal conversion of the digital-to-analog conversion circuit.
In a specific embodiment, the input interface of the signal acquisition terminal is a 2-way BNC interface and can be connected with a BNC test pen; the output interface of the signal acquisition terminal is a 1-path gigabit Ethernet port and can be connected with the network port of the experiment table through a network cable.
In a specific embodiment, the input port of the signal receiving terminal is a 1-way gigabit ethernet port; the output port of the signal receiving terminal is a VGA interface and can be connected with a display device, so that the synchronous presentation of the collected data of a plurality of test nodes is realized.
In a specific embodiment, the first operation indicator light comprises at least one sampling rate indicator light and one sampling command indicator light. Specifically, the number of the sampling rate indicator lamps is 5, and the sampling rate indicator lamps respectively correspond to the sampling rates of 1M, 10M, 20M, 50M and 100M. And the sampling instruction indicator lamp flickers for 1 time when receiving the sampling instruction for 1 time and finishing sampling uploading.
In a specific embodiment, the first control key is a manual acquisition key;
the second control key comprises an acquisition control key and a sampling rate selection key which correspond to the sampling rate indicator lamp. And (3) acquiring the control key, circularly switching according to 1M- >10M- >20M- >50M- >100M at a sampling rate every time, and synchronously lighting a corresponding indicator lamp when a certain frequency is selected. The acquisition rate selection key sends an acquisition instruction for 1 time when pressing 1 time.
Further, the display device is a projector or a display.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.
Claims (9)
1. A multi-channel signal acquisition display device, comprising: the system comprises at least one signal acquisition terminal, a signal receiving terminal and a display device;
the signal acquisition terminal is connected with an analog signal to be tested of the experiment table position through a BNC test wire so as to obtain an analog input signal;
the signal acquisition terminal converts the analog input signal into a digital signal;
the digital signal is transmitted to the signal receiving terminal through the Ethernet;
the signal receiving terminal converts the digital signal into a data waveform;
the signal receiving terminal is connected with a display device for displaying the data waveform;
the signal acquisition terminal comprises a signal conditioning circuit, an analog-to-digital conversion circuit, a first FPGA unit, a first Ethernet adaptation circuit, at least two first working indicator lamps, a first control key and a first power supply circuit;
the signal receiving terminal comprises a second Ethernet adaptive circuit, a second FPGA unit, a VGA driving circuit, at least two second control keys, at least one second working indicator lamp and a second power supply circuit.
2. A multi-channel signal acquisition display device as claimed in claim 1, wherein: the signal conditioning circuit conditions the analog input signal in the range of-5 v into the analog output signal of 0 v-1 v;
the analog-to-digital conversion circuit converts the 0 v-1 v analog output signal into an 8-bit digital signal;
the first FPGA unit receives a data acquisition instruction transmitted by an Ethernet network so as to control the signal conversion of the digital-to-analog conversion circuit, and stores the 8-bit digital signal in the first FPGA unit to form a data packet.
3. A multi-channel signal acquisition display apparatus as claimed in claim 2, wherein: the data packet in the first FPGA unit is stored in the second FPGA unit through the second Ethernet adapting circuit;
the VGA driving circuit converts the digital signals in the data packet into data waveforms.
4. A multi-channel signal acquisition display device as claimed in claim 3, wherein: the data acquisition instructions include a start acquisition instruction and a sampling clock rate instruction.
5. A multi-channel signal acquisition display device as claimed in claim 4, wherein: the signal acquisition terminal input interface is a 2-path BNC interface and can be connected with a BNC test pen; the output interface of the signal acquisition terminal is a 1-path gigabit Ethernet port and can be connected with the network port of the experiment table through a network cable.
6. A multi-channel signal acquisition display device as claimed in claim 5, wherein: the input port of the signal receiving terminal is a 1-path kilomega Ethernet port; and the output port of the signal receiving terminal is a VGA interface and can be connected with a display device.
7. A multi-channel signal acquisition display device as claimed in claim 6, wherein: the first work indicator lamp comprises at least one sampling rate indicator lamp and a sampling instruction indicator lamp.
8. A multi-channel signal acquisition display device as claimed in claim 7, wherein:
the first control key is a manual acquisition key;
the second control key comprises an acquisition control key and a sampling rate selection key which correspond to the sampling rate indicator lamp.
9. A multi-channel signal acquisition display device as claimed in claim 8, wherein: the display device is a projector or a display.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121275495.0U CN214670194U (en) | 2021-06-08 | 2021-06-08 | Multichannel signal acquisition display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121275495.0U CN214670194U (en) | 2021-06-08 | 2021-06-08 | Multichannel signal acquisition display device |
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| Publication Number | Publication Date |
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| CN214670194U true CN214670194U (en) | 2021-11-09 |
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| CN202121275495.0U Active CN214670194U (en) | 2021-06-08 | 2021-06-08 | Multichannel signal acquisition display device |
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2021
- 2021-06-08 CN CN202121275495.0U patent/CN214670194U/en active Active
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