CN214626351U - Power grid protection circuit - Google Patents

Power grid protection circuit Download PDF

Info

Publication number
CN214626351U
CN214626351U CN202120941800.9U CN202120941800U CN214626351U CN 214626351 U CN214626351 U CN 214626351U CN 202120941800 U CN202120941800 U CN 202120941800U CN 214626351 U CN214626351 U CN 214626351U
Authority
CN
China
Prior art keywords
signal
voltage
module
protection circuit
detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202120941800.9U
Other languages
Chinese (zh)
Inventor
陈彦刚
龚峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hangzhou Youwang Electronics Co ltd
Original Assignee
Hangzhou Youwang Electronics Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hangzhou Youwang Electronics Co ltd filed Critical Hangzhou Youwang Electronics Co ltd
Priority to CN202120941800.9U priority Critical patent/CN214626351U/en
Application granted granted Critical
Publication of CN214626351U publication Critical patent/CN214626351U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Emergency Protection Circuit Devices (AREA)

Abstract

The utility model provides a power grid protection circuit, an overvoltage and undervoltage detection circuit can realize the functions of overvoltage detection and undervoltage detection, the overvoltage detection and undervoltage detection multiplex pins, and the whole circuit only needs one input port, thereby reducing the scale and complexity of the circuit and being convenient for maintenance; in addition, m periods of the first comparison signal and the second comparison signal are respectively detected when the first enabling signal is effective, and then classification signals representing whether the power grid is overvoltage or undervoltage can be generated by using the obtained first characteristic signal and the second characteristic signal, so that overvoltage and undervoltage detection is realized to control the on-off of the power grid; the power grid protection circuit can resist the interference of discontinuous time, prevent misoperation caused by the interference, improve the detection precision and the anti-interference capability, further integrate the over-voltage and under-voltage detection circuit with the leakage protection circuit, enable the power grid protection circuit to have the functions of leakage protection and over-voltage and under-voltage detection, and is simple to apply, high in precision and strong in anti-interference capability.

Description

Power grid protection circuit
Technical Field
The utility model relates to a power electronic technology field especially relates to a power grid protection circuit.
Background
With the improvement of living standard of people and the increasing emphasis on electricity safety, many electrical products are equipped with leakage protectors. The leakage protector uses a special leakage protection circuit, but the additional protection function of the existing leakage protection circuit is not perfect.
At present, the load difference of a power grid at different time is large, the voltage fluctuation of the power grid is large, in addition, the voltage fluctuation of the power grid can be caused by line faults, and the over-high or over-low voltage of the power grid can cause that part of electric appliances can not work normally, even be damaged. The existing solution is to design an overvoltage and undervoltage protection circuit separately, which is generally built by discrete components, and the circuit has large and complex scale, difficult maintenance, high cost, low precision and poor anti-interference capability.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a power grid protection circuit to lack excessive pressure and undervoltage protection, electric leakage protection circuit function singleness scheduling problem in solving the electrical products.
In order to achieve the above object, the utility model provides a power grid protection circuit, include: an over-voltage and under-voltage detection circuit, the over-voltage and under-voltage detection circuit comprising:
the signal acquisition module is used for sampling the alternating voltage of the power grid to obtain a sampling voltage signal;
the basic signal generating module is used for generating undervoltage threshold voltage and overvoltage threshold voltage;
the first voltage comparison module is connected with the signal acquisition module and the basic signal generation module and is used for comparing the sampling voltage signal with the undervoltage threshold voltage and the overvoltage threshold voltage respectively to obtain a first comparison signal and a second comparison signal; and the number of the first and second groups,
and the control circuit is connected with the first voltage comparison module and used for respectively detecting m periods of the first comparison signal and the second comparison signal when the first enable signal is effective to obtain a first characteristic signal and a second characteristic signal, and generating a classification signal for representing whether the power grid is overvoltage or undervoltage according to the first characteristic signal and the second characteristic signal, wherein m is more than or equal to 1.
Optionally, the first enable signal is a periodic signal, each period of the first enable signal includes a detection time and a zero clearing time, the first enable signal is valid within the detection time and invalid within the zero clearing time, and the detection time is greater than m periods of the first comparison signal and m periods of the second comparison signal.
Optionally, the valid levels of the first characteristic signal and the second characteristic signal are latched to the end of the detection time of each period of the first enable signal, and the valid levels of the first characteristic signal and the second characteristic signal are cleared at the clearing time of each period of the first enable signal.
Optionally, the control circuit includes:
the periodic anti-interference detection module is connected with the first voltage comparison module and is used for respectively detecting m periods of the first comparison signal and the second comparison signal when a first enabling signal is effective to obtain a first characteristic signal and a second characteristic signal;
the edge detection module is connected with the periodic anti-interference detection module and is used for respectively carrying out edge detection on the first characteristic signal and the second characteristic signal so as to obtain a first classification signal representing whether the first characteristic signal has a rising edge/a falling edge and a second classification signal representing whether the second characteristic signal has a rising edge/a falling edge; and the number of the first and second groups,
and the classification module is connected with the edge detection module and used for carrying out logic operation on the first classification signal and the second classification signal so as to obtain the classification signal.
Optionally, the periodic anti-interference detection module performs edge detection on m periods of the first comparison signal and the second comparison signal respectively when the first enable signal is valid, to obtain the first characteristic signal indicating whether the first comparison signal has a rising edge/a falling edge in each of the m periods and obtain the second characteristic signal indicating whether the second comparison signal has a rising edge/a falling edge in each of the m periods.
Optionally, the first voltage comparison module further compares the sampled voltage signal with a power frequency threshold voltage to obtain a power frequency signal representing a magnitude relationship between the sampled voltage signal and the power frequency threshold voltage;
and, the control circuit further comprises:
and the counter module is connected with the periodic anti-interference detection module and the first voltage comparison module and is used for generating the first enabling signal according to the power frequency signal.
Optionally, the counter module includes:
the frequency division unit is connected with the first voltage comparison module and is used for executing p frequency division for n times on the power frequency signal to obtain n-level frequency division signals, wherein n and p are more than or equal to 2; and the number of the first and second groups,
and the logic operation unit is connected with the frequency dividing unit and is used for performing logic operation on the 2 nd-level frequency dividing signal to the nth-level frequency dividing signal to obtain the first enabling signal.
Optionally, a pulse width of the first enable signal is equal to a sum of pulse widths of the 2 nd-level frequency division signal to the nth-level frequency division signal.
Optionally, the control circuit further includes:
and the power-on self-test module is connected with the first voltage comparison module, the counter module and the periodic anti-interference detection module, and is used for performing edge detection on q periods of the power frequency signal according to a power-on reset signal, generating an effective second enabling signal when each period has a rising edge/a falling edge in the q periods of the power frequency signal, and controlling the counter module and the periodic anti-interference detection module to start working, wherein q is more than or equal to 1.
Optionally, the rising edges of the second enable signal and the nth-level frequency-division signal are spaced by g cycles of the power frequency signal, where g and n satisfy the following relationship:
g＝2(n-1)。
optionally, the power-on self-test module has s triggers, where s is greater than or equal to 1, and q and s satisfy the following relationship:
q＝2(s-1)。
optionally, the classifying module is further connected to the counter module, and is configured to receive the nth level frequency division signal, perform logic operation on the first classification signal and the second classification signal, and perform logic operation on a result of the logic operation and the nth level frequency division signal to obtain the classifying signal.
Optionally, the classifying module includes:
the exclusive-nor gate is connected with the edge detection module and is used for carrying out exclusive-nor operation on the first classification signal and the second classification signal; and the number of the first and second groups,
and the AND gate is connected with the counter module and the XNOR gate and is used for performing AND operation on the result of the XNOR operation and the nth-level frequency division signal to obtain the classification signal.
Optionally, the periodic anti-interference detection module has r triggers, where r is greater than 1 and equal to or less than n-1, and m and r satisfy the following relationship:
m＝2(r-1)。
optionally, the signal acquisition module includes:
the rectification unit is used for rectifying the alternating voltage of the power grid to obtain a rectification signal; and the number of the first and second groups,
and the voltage division unit is connected with the rectification unit and used for dividing the voltage of the rectification signal to obtain the sampling voltage signal.
Optionally, the basic signal generating module includes:
a reference voltage generating unit for generating a reference voltage; and the number of the first and second groups,
the voltage stabilizing unit is connected with the reference voltage generating unit and is used for generating the undervoltage threshold voltage, the overvoltage threshold voltage and the power frequency threshold voltage according to the reference voltage;
and the stabilized voltage power supply is connected with the reference voltage generation unit and used for generating constant power supply voltage according to the reference voltage.
Optionally, the basic signal generating module further includes:
and the power-on reset unit is used for generating the power-on reset signal.
Optionally, the power grid protection circuit further includes an electric leakage protection circuit, and the electric leakage protection circuit is configured to detect whether the power grid leaks electricity, and control the on/off of the power grid according to the electric leakage detection result and the classification signal.
Optionally, the leakage protection circuit includes:
the signal amplification module is connected with the power grid and used for amplifying the leakage voltage of the power grid to obtain a voltage amplification signal;
the second voltage comparison module is connected with the signal amplification module and used for comparing the voltage amplification signal with a reference voltage to obtain a third comparison signal; and the number of the first and second groups,
and the logic processing module is connected with the over-voltage and under-voltage detection circuit and the second voltage comparison module and is used for carrying out logic operation on the third comparison signal and the classification signal to obtain a control signal for controlling the on-off of the power grid.
Optionally, the leakage protection circuit further includes:
the delay module is connected with the logic processing module and is used for delaying the control signal and then outputting the delayed control signal; and the number of the first and second groups,
and the driving module is connected with the time delay module and used for enhancing the driving capability of the delayed control signal and then outputting the enhanced control signal.
Optionally, the leakage protection circuit, the basic signal generation module, the first voltage comparison module, and the control circuit are integrated in the same chip.
Optionally, the leakage protection circuit and the under-voltage detection circuit are integrated in the same chip.
The utility model provides a power grid protection circuit has following beneficial effect:
1) the overvoltage and undervoltage detection circuit can realize the functions of overvoltage detection and undervoltage detection, the overvoltage detection and undervoltage detection multiplex pins, and the whole circuit only needs one input port, so that the scale and the complexity of the circuit are reduced, and the circuit is convenient to maintain.
2) When the first enabling signal is effective, m periods of the first comparison signal and the second comparison signal are detected respectively, and at the moment, classification signals representing whether the power grid is overvoltage or undervoltage can be generated by using the obtained first characteristic signal and the second characteristic signal, so that overvoltage and undervoltage detection is realized; and because m periods of the first comparison signal and the second comparison signal are detected, the interference of discontinuous time can be resisted, misoperation caused by the interference is prevented, tripping is avoided when the power grid is subjected to instantaneous overvoltage and instantaneous undervoltage fluctuation, and the detection precision and the anti-interference capability are improved.
3) Latching the effective levels of the first characteristic signal and the second characteristic signal to the end of the detection time of each period of the first enabling signal, and resetting the effective levels of the first characteristic signal and the second characteristic signal at the reset time of each period of the first enabling signal without influencing the detection of the next period;
4) the over-voltage and under-voltage detection circuit and the leakage protection circuit are integrated together, so that the power grid protection circuit has the functions of leakage protection and over-voltage and under-voltage detection, and is simple to apply, high in precision and strong in anti-interference capability; and the leakage protection circuit and the over-voltage and under-voltage detection circuit can be integrated in the same chip, so that the complexity of the system is reduced, the system is more friendly to application technicians, and meanwhile, the system test and operation maintenance are facilitated.
Drawings
Fig. 1 is a flowchart of a power grid protection method according to an embodiment of the present invention;
fig. 2a is a circuit diagram of a power grid protection circuit according to a first embodiment of the present invention;
fig. 2b is a circuit diagram of an over-voltage and under-voltage detection circuit according to an embodiment of the present invention;
fig. 3a is a circuit timing diagram of the overvoltage/undervoltage detection circuit according to the first embodiment of the present invention when the power grid is at normal voltage;
fig. 3b is a circuit timing diagram of the overvoltage/undervoltage detection circuit according to the first embodiment of the present invention when the power grid is in overvoltage;
fig. 3c is a circuit timing diagram of the overvoltage/undervoltage detection circuit according to the first embodiment of the present invention when the power grid is under-voltage;
fig. 4 is an application diagram of a power grid protection circuit according to a first embodiment of the present invention;
fig. 5a is a circuit timing diagram of the overvoltage/undervoltage detection circuit provided by the second embodiment of the present invention when the power grid is at normal voltage;
fig. 5b is a circuit timing diagram of the overvoltage/undervoltage detection circuit provided by the second embodiment of the present invention when the power grid is in overvoltage;
fig. 5c is a circuit timing diagram of the under-voltage detection circuit provided by the embodiment of the present invention when the power grid is under-voltage.
Wherein the reference numerals are:
10-a signal acquisition module; 20-a base signal generation module; 21-a power-on reset unit; 22-a reference voltage generating unit; 23-a voltage stabilizing unit; 24-a regulated power supply; 30-a first voltage comparison module; 40-a power-on self-test module; 50-a counter module; 60-periodic anti-interference detection module; 70-an edge detection module; 80-a classification module; 90-a signal amplification module; 100-a delay module; 110-a drive module; 120-a power supply module; 130-a sensing module; 140-trip module;
d1-diode; r1 — first divider resistance; r2-second voltage dividing resistor; comp 1-first comparator; comp 2-second comparator; comp 3-third comparator; comp 4-fourth comparator; vsamp-sample voltage signal; POR-Power on reset signal; POST-second enable signal; vref-reference voltage; vunder-undervoltage threshold voltage; vover — over voltage threshold voltage; vth-power frequency threshold voltage; phase-power frequency signal; clear-first enable signal; validation-third enable signal; VA — first comparison signal; VB-second comparison signal; VERA-first characteristic signal; VERB-second characteristic signal; QA — first classification signal; QB-second classification signal; ocheck-classification signal; AmpOut-voltage amplified signal; ctrl — control signal; output-drive signal; the line of the L-power grid; n-zero line of the grid; input-leakage voltage.
Detailed Description
The following description of the embodiments of the present invention will be described in more detail with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.
Example one
Fig. 1 is a flowchart of a power grid protection method provided in this embodiment. As shown in fig. 1, the power grid protection method includes:
step S100: sampling an alternating voltage of a power grid to obtain a sampled voltage signal Vsamp;
step S200: comparing the sampling voltage signal Vsamp with the undervoltage threshold voltage Vunder and the overvoltage threshold voltage Vover respectively to obtain a first comparison signal VA and a second comparison signal VB; and the number of the first and second groups,
step S300: respectively detecting m periods of the first comparison signal VA and the second comparison signal VB when a first enable signal Clear is effective to obtain a first characteristic signal VERA and a second characteristic signal VERB, and generating a classification signal Ocheck representing whether the power grid is overvoltage or undervoltage according to the first characteristic signal VERA and the second characteristic signal VERB, wherein m is more than or equal to 1.
Based on this, the present embodiment further provides a power grid protection circuit, configured to execute the power grid protection method. Fig. 2a is a circuit diagram of a power grid protection circuit provided in this embodiment, and fig. 2b is a circuit diagram of an overvoltage/undervoltage detection circuit provided in this embodiment, as shown in fig. 2a and fig. 2b, the power grid protection circuit is characterized by including: an over-voltage and under-voltage detection circuit, the over-voltage and under-voltage detection circuit comprising:
the signal acquisition module 10 is used for sampling the alternating voltage of the power grid to obtain a sampled voltage signal Vsamp;
a basic signal generating module 20, configured to generate an undervoltage threshold voltage Vunder and an overvoltage threshold voltage Vover;
the first voltage comparison module 30 is connected to the signal acquisition module 10 and the basic signal generation module 20, and configured to compare the sampling voltage signal Vsamp with the undervoltage threshold voltage Vunder and the overvoltage threshold voltage Vover, respectively, to obtain a first comparison signal VA and a second comparison signal VB; and the number of the first and second groups,
the control circuit is connected with the first voltage comparison module 30 and is configured to detect m periods of the first comparison signal VA and the second comparison signal VB when the first enable signal Clear is valid, obtain a first characteristic signal VERA and a second characteristic signal VERB, and generate a classification signal Ocheck representing whether the power grid is overvoltage or undervoltage according to the first characteristic signal VERA and the second characteristic signal VERB, where m is greater than or equal to 1.
It can be seen that the signal acquisition module 10 in this embodiment is configured to execute step S100 of the power grid protection method, the basic signal generation module 20 and the first voltage comparison module 30 are configured to execute step S200 of the power grid protection method, and the control circuit is configured to execute step S300 of the power grid protection method. This embodiment is integrated in a circuit with overvoltage protection and undervoltage protection function for overvoltage detection and undervoltage detection's function can be realized to a circuit, and overvoltage detection and undervoltage detection multiplex pin, whole circuit only need an input port, reduce the scale and the complexity of circuit, are convenient for maintain.
Next, the power grid protection method and the power grid protection circuit provided in this embodiment will be described in detail with reference to fig. 2a and 2 b. It should be understood that the present embodiment provides only one power grid protection circuit for executing the power grid protection method, and in other embodiments, other circuits may also be used for executing the power grid protection method, and redundant description is not repeated here.
Firstly, step S100 is executed to sample the ac voltage of the power grid, so as to obtain the sampled voltage signal Vsamp.
Specifically, the signal acquisition module 10 includes a rectification unit and a voltage division unit. The rectification unit is connected with the power grid and used for receiving the alternating voltage of the power grid and rectifying the alternating voltage of the power grid so as to output a rectification signal. The voltage division unit is connected with the rectification unit and used for receiving the rectification signal and dividing the voltage of the rectification signal to obtain the sampling voltage signal Vsamp.
In this embodiment, when the alternating-current voltage of the power grid is rectified to obtain the rectified signal, the alternating-current voltage of the power grid is half-wave rectified. Based on this, the rectifying unit is a diode D1, and the anode of the diode D1 is used as the input end of the rectifying unit and is connected with the power grid; and the cathode of the diode D1 is used as the output end of the rectifying unit and is connected with the voltage dividing unit. It should be understood that half-wave rectification can be realized by using the diode D1, the circuit is simplified, the cost is saved, a large capacitance value capacitor is not needed in the signal acquisition process, the characteristics of the alternating current signal of the power grid are reserved, and the detection precision can be remarkably improved.
In this embodiment, the rectified signal is divided by a resistor divider to obtain the sampling voltage signal Vsamp. Based on this, the voltage dividing unit includes a first voltage dividing resistor R1 and a second voltage dividing resistor R2, the first voltage dividing resistor R1 and the second voltage dividing resistor R2 are connected in series and then connected between the output end of the rectifying unit and the ground end, and a node between the first voltage dividing resistor R1 and the second voltage dividing resistor R2 serves as the output end of the voltage dividing unit to output the sampling voltage signal Vsamp.
Further, step S200 is executed to compare the sampling voltage signal Vsamp with the under-voltage threshold voltage Vunder and the over-voltage threshold voltage Vover, respectively, so as to obtain a first comparison signal VA and a second comparison signal VB.
Specifically, the basic signal generating module 20 includes a power-on reset unit 21, a reference voltage generating unit 22, a voltage stabilizing unit 23, and a voltage stabilizing power supply 24. When the overvoltage/undervoltage detection circuit is powered on, the power-on reset unit 21 generates a power-on reset signal POR, which is used to control the modules in the overvoltage/undervoltage detection circuit to perform power-on reset, which will be described below. The reference voltage generating unit 22 is configured to generate a reference voltage Vref. The voltage stabilizing unit 23 is connected to the reference voltage generating unit 22, and configured to generate the undervoltage threshold voltage Vunder, the overvoltage threshold voltage Vover, and the power frequency threshold voltage Vth according to the reference voltage Vref. The voltage-stabilizing power supply 24 is connected to the reference voltage generating unit 22, and configured to generate a constant power supply voltage VDD according to the reference voltage Vref, so as to supply power to each module in the overvoltage/undervoltage detection circuit, for example, the reference voltage generating unit 22 is provided with the power supply voltage VDD, so that the reference voltage Vref output by the reference voltage generating unit 22 is ensured to be stable, and further, the undervoltage threshold voltage Vunder, the overvoltage threshold voltage Vover, and the power frequency threshold voltage Vth are ensured to be stable, and the reference voltage Vref is used to provide a reference value of the power supply voltage VDD to control the size of the power supply voltage VDD.
Further, the first voltage comparison module 30 includes a first comparator Comp1, a second comparator Comp2 and a third comparator Comp 3. The negative input end of the first comparator Comp1 is configured to receive the brown-out threshold voltage Vunder, the positive input end of the first comparator Comp1 is connected to the voltage dividing unit and configured to receive the sampling voltage signal Vsamp, and the first comparator Comp1 compares the brown-out threshold voltage Vunder with the sampling voltage signal Vsamp and outputs a first comparison signal VA representing a magnitude relationship between the brown-out threshold voltage Vunder and the sampling voltage signal Vsamp. Similarly, the negative input terminal of the second comparator Comp2 is used for receiving the overvoltage threshold voltage Vover, the positive input terminal of the second comparator Comp2 is connected to the voltage dividing unit and is used for receiving the sampled voltage signal Vsamp, and the second comparator Comp2 compares the overvoltage threshold voltage Vover with the sampled voltage signal Vsamp and outputs a second comparison signal VB representing the magnitude relationship between the overvoltage threshold voltage Vover and the sampled voltage signal Vsamp. The negative input end of the third comparator Comp3 is configured to receive the power frequency threshold voltage Vth, the positive input end of the third comparator Comp3 is connected to the output end of the voltage dividing unit and configured to receive the sampled voltage signal Vsamp, the third comparator Comp3 compares the power frequency threshold voltage Vth with the sampled voltage signal Vsamp and outputs a power frequency signal Phase representing the magnitude relationship between the power frequency threshold voltage Vth and the sampled voltage signal Vsamp, and the frequency of the power frequency signal Phase may represent the frequency of the sampled voltage signal Vsamp at the same time.
In this embodiment, the sampled voltage signal Vsamp is provided to the positive input terminals of the first comparator Comp1, the second comparator Comp2 and the third comparator Comp3, and the under-voltage threshold voltage Vunder, the over-voltage threshold voltage Vover and the power frequency threshold voltage Vth are provided to the negative input terminals of the first comparator Comp1, the second comparator Comp2 and the third comparator Comp3, respectively; when the sampling voltage signal Vsamp is greater than the brown-out threshold voltage Vunder, the first comparison signal VA output by the first comparator Comp1 is at a high level, whereas when the sampling voltage signal Vsamp is less than the brown-out threshold voltage Vunder, the first comparison signal VA output by the first comparator Comp1 is at a low level. Similarly, when the sampled voltage signal Vsamp is greater than the over-voltage threshold voltage Vover, the second comparison signal VB output by the second comparator Comp2 is at a high level, whereas when the sampled voltage signal Vsamp is less than the over-voltage threshold voltage Vover, the second comparison signal VB output by the second comparator Comp2 is at a low level. Similarly, when the sampled voltage signal Vsamp is greater than the power frequency threshold voltage Vth, the power frequency signal Phase output by the third comparator Comp3 is at a high level, and conversely, when the sampled voltage signal Vsamp is less than the power frequency threshold voltage Vth, the power frequency signal Phase output by the third comparator Comp3 is at a low level.
It should be understood that, as an alternative embodiment, the sampling voltage signal Vsamp may also be provided to the negative inputs of the first comparator Comp1, the second comparator Comp2 and the third comparator Comp3, and the brown-out threshold voltage Vunder, the brown-in threshold voltage Vover and the power frequency threshold voltage Vth are provided to the positive inputs of the first comparator Comp1, the second comparator Comp2 and the third comparator Comp3, respectively, which will not be explained one by one here.
Next, step S300 is executed, when the first enable signal Clear is valid, m periods of the first comparison signal VA and the second comparison signal VB are detected respectively, so as to obtain a first characteristic signal VERA and a second characteristic signal VERB, and a classification signal Ocheck representing whether the power grid is overvoltage or undervoltage is generated according to the first characteristic signal VERA and the second characteristic signal VERB, where m is greater than or equal to 1.
Specifically, the control circuit includes a power-on self-test module 40, a counter module 50, a periodic anti-interference detection module 60, an edge detection module 70, and a classification module 80.
The power-on self-test module 40 is configured to perform edge detection on q cycles of the power frequency signal Phase according to the power-on reset signal POR, and generate an effective second enable signal POST when each cycle has a rising edge/a falling edge in the q cycles of the power frequency signal, and control the counter module 50 and the periodic anti-interference test module 60 to start working, where q is greater than or equal to 1.
Specifically, the power-on self test module 40 is connected to the third comparator Comp3 and the power-on reset unit 21, and is configured to receive the power frequency signal Phase and the power-on reset signal POR. The power-on self-test module 40 performs power-on reset when receiving the power-on reset signal POR, performs edge detection on q periods of the power frequency signal Phase under the control of the power-on reset signal POR, and outputs a second enable signal POST that indicates whether each period has a rising edge/a falling edge within the q periods of the power frequency signal Phase. In this embodiment, when whether each of q cycles of the power frequency signal Phase has a rising edge/a falling edge indicates that the power grid starts to operate, at this time, the second enable signal POST is at a high level, and the second enable signal POST is valid; on the contrary, when any one of the q periods of the power frequency signal Phase does not have a rising edge/a falling edge, it indicates that the power grid does not start to operate, at this time, the second enable signal POST is at a low level, and the second enable signal POST is inactive, but the invention is not limited thereto.
The power-on self-test module 40 may improve the reliability of the overall circuit, and in some embodiments, the power-on self-test module 40 may be omitted.
The power-on self-test module 40 comprises s triggers, and edge detection is performed on q periods of the power frequency signal Phase by using the s triggers, wherein s is greater than or equal to 1, and q and s satisfy the following relation:
q＝2(s-1)。
in this embodiment, s is 3, that is, the power-on self-test module 40 detects 4 consecutive periods of the power frequency signal Phase, and if each of the 4 periods of the power-on self-test module 40 has a rising edge/a falling edge (in the manner of determining the falling edge in this embodiment), the second enable signal POST jumps to a high level.
Further, the counter module 50 is configured to generate the first enable signal Clear according to the power frequency signal Phase.
Specifically, the counter module 50 is connected to the power-on self test module 40 and the third comparator Comp3, and configured to receive the second enable signal POST and the power frequency signal Phase, respectively, start counting when the counter module 50 receives the valid second enable signal POST, so as to obtain g periods of the power frequency signal Phase, and output a valid third enable signal valid after g periods of the power frequency signal Phase, that is, the power frequency signal Phase with g periods of the rising edge interval between the second enable signal POST and the third enable signal valid. .
Specifically, the counter module 50 includes a frequency dividing unit and a logic operation unit. The frequency dividing unit is connected to the third comparator Comp3 and the power-on self-test module 40, and is configured to receive the power frequency signal Phase and the second enable signal POST. When the second enable signal POST is at a high level (active), the counter module 50 starts to operate, and performs p-frequency division on the power frequency signal Phase n times to obtain n-level frequency division signals, where n and p are greater than or equal to 2. The logic operation unit is connected with the frequency dividing unit and used for performing logic operation on the 2 nd-order frequency dividing signal to the nth-order frequency dividing signal and outputting the first enable signal Clear.
The first enable signal Clear is a periodic signal, each period of the first enable signal Clear includes a detection time and a clearing time, the first enable signal Clear is valid within the detection time and invalid within the clearing time, and the first and second feature signals VERA and VERB are cleared when the first enable signal Clear is invalid.
In this embodiment, g and n satisfy the following relationship:
g＝2(n-1)。
optionally, the counter module 50 starts counting when receiving the valid second enable signal POST to obtain g periods of the power frequency signal Phase, and outputs an nth-level frequency-divided signal after g periods of the power frequency signal Phase, and outputs the nth-level frequency-divided signal as a third enable signal validity, which will be described below.
Further, the logic operation unit is an or gate, and the first enable signal Clear is obtained by performing an or operation on the level 2 frequency division signal to the level n frequency division signal through the or gate, where the first enable signal Clear is a periodic signal, and a pulse width of the first enable signal Clear is a sum of pulse widths of the level 2 frequency division signal to the level n frequency division signal. Therefore, after the power frequency signal Phase is divided and the divided signal is logically operated, the pulse width of the first enable signal Clear is increased, so that the detection time of each period of the first enable signal Clear is longer than m periods of the first comparison signal VA and m periods of the second comparison signal VB.
In this embodiment, p is 2 and n is 4, that is, the frequency dividing unit divides the power frequency signal Phase by 24 times to obtain a 1 st-order frequency-divided signal (2)1) Class 2 frequency division signal (2)2) Class 3 frequency division signal (2)3) And a 4 th order frequency division signal (2)4) The first enable signal Clear is the 2 nd order frequency division signal (2)2) Class 3 frequency division signal (2)3) And a 4 th order frequency division signal (2)4) Is carried out byThe third enable signal valid is the 4-level frequency division signal (2)4)。
It should be understood that in some embodiments, the counter module 50 may be omitted and the first enable signal Clear may be designed and input into the periodic tamper detection immunity module 60 from the outside.
Further, the periodic anti-interference detection module 60 is configured to detect m periods of the first comparison signal VA and the second comparison signal VB when the first enable signal Clear is valid, obtain a first feature signal VERA and a second feature signal VERB, and Clear the first feature signal VERA and the second feature signal VERB when the first enable signal Clear is invalid. It should be appreciated that, since the pulse width of each period of the first enable signal Clear is greater than m periods of the first comparison signal VA and m periods of the second comparison signal VB, when the periodic anti-interference detection module 60 performs edge detection on m periods of the first comparison signal VA and the second comparison signal VB in each period of the first enable signal Clear, the situation of insufficient detection time can be avoided.
Specifically, the periodic interference immunity detecting module 60 performs edge detection on m periods of the first comparison signal VA and the second comparison signal VB when the first enable signal Clear is valid, obtains the first characteristic signal VERA representing whether the first comparison signal VA has a rising edge/falling edge in each period in m periods and the second characteristic signal VERB representing whether the second comparison signal VB has a rising edge/falling edge in each period in m periods, and determines whether the power grid is overvoltage or undervoltage by using the first characteristic signal VERA and the second characteristic signal VERB.
Specifically, the periodic anti-interference detection module 60 is connected to the counter module 50, the first comparator Comp1, the second comparator Comp2 and the power-on self-test module 40, and is configured to receive the first enable signal Clear, the first comparison signal VA, the second comparison signal VB and the second enable signal POST respectively. When the second enable signal POST is high (active), the periodic tamper-resistant detection module 60 starts to operate, and edge detection is performed on m periods of the first comparison signal VA and the second comparison signal VB in each period of the first enable signal Clear, so as to obtain a first characteristic signal VERA representing whether the first comparison signal VA has a rising/falling edge in each period of m periods and a second characteristic signal VERA representing whether the second comparison signal VB has a rising/falling edge in each period of m periods.
After obtaining the first feature signal VERA and the second feature signal VERB, the periodic anti-interference detection module 60 latches the valid levels of the first feature signal VERA and the second feature signal VERB to the end of the detection time of each period of the first enable signal Clear, and clears (can also be understood as resetting) the valid levels of the first feature signal VERA and the second feature signal VERB at the clearing time of each period of the first enable signal Clear, so that the detection of the next period is not affected by the valid levels of the first feature signal VERA and the second feature signal VERB detected in the previous period.
It should be understood, because periodic anti-interference detection module 60 is right first comparison signal VA with m periods of second comparison signal VB carry out the border and detect, at this moment according to first characteristic signal VERA reaches second characteristic signal VERB generates categorised signal Ocheck can accurately be judged whether the electric wire netting is excessive pressure or under-voltage, owing to all detected m periods to first comparison signal VA and second comparison signal VB, can resist discontinuous time's interference, prevent to lead to the malfunction because of the interference, do not trip when guaranteeing electric wire netting instantaneous excessive pressure, instantaneous fluctuation, improved detection precision and interference killing feature.
In this embodiment, falling edge detection is performed on m periods of the first comparison signal VA and the second comparison signal VB in each period of the first enable signal Clear. When the first comparison signal VA has a falling edge in each of m periods, the first feature signal VERA is at a high level; conversely, when the first comparison signal VA does not have a falling edge in any one of the m periods, the first feature signal VERA is low. Similarly, when the second comparison signal VB has a falling edge in each of m periods, the second feature signal VERB is at a high level; conversely, when the second comparison signal VB has no falling edge in any period of the m periods, the second feature signal VERB is at a low level, but this should not be taken as a limitation.
It should be understood that increasing the number of cycles (i.e., m) of edge detection for each of the first comparison signal VA and the second comparison signal VB can increase the detection accuracy, and in this embodiment, m is 4.
Further, the edge detection module 70 is included for edge detecting the first and second feature signals VERA and VERB, respectively, to obtain a first classification signal characterizing whether the first feature signal VERA has rising/falling edges and a second classification signal characterizing whether the second feature signal VERB has rising/falling edges.
Further, the edge detection module 70 is configured to perform edge detection on the first feature signal VERA and the second feature signal VERB respectively to obtain a first classification signal QA characterizing whether the first feature signal VERA has a rising/falling edge and a second classification signal QB characterizing whether the second feature signal VERB has a rising/falling edge.
Specifically, the edge detection module 70 is connected to the periodic anti-interference detection module 60, and configured to receive the first characteristic signal VERA and the second characteristic signal VERB, and perform edge detection on the first characteristic signal VERA and the second characteristic signal VERB, so as to obtain a first classification signal QA representing whether the first characteristic signal VERA has a rising edge/a falling edge and a second classification signal QB representing whether the second characteristic signal VERB has a rising edge/a falling edge. The first classification signal QA may follow a level characteristic of the first characteristic signal VERA, the second classification signal QB may follow a characteristic of the second characteristic signal VERB, and the first classification signal QA and the second classification signal QB may be maintained when the first characteristic signal VERA and the second characteristic signal VERB are cleared.
In this embodiment, the edge detection module 70 is configured to perform rising edge detection on the first characteristic signal VERA and the second characteristic signal VERB. When the first feature signal VERA jumps to a high level, the edge detection module 70 detects a rising edge of the first feature signal VERA, at which time the first classification signal QA jumps to a high level; on the contrary, when the rising edge of the first feature signal VERA is not detected by the edge detecting module 70, the first classification signal QA is at a low level. Similarly, when the second feature signal VERB transitions to a high level, the edge detection module 70 detects a rising edge of the second feature signal VERB, at which time the second classification signal QB transitions to a high level; on the contrary, when the edge detecting module 70 does not detect the rising edge of the second feature signal VERB, the second classification signal QB is at a low level.
The classifying module 80 is configured to perform a logic operation on the first classification signal QA and the second classification signal QB to obtain the classification signal Ocheck.
Specifically, the classifying module 80 is respectively connected to the edge detecting module 70, and configured to perform a logic operation on the first classification signal QA and the second classification signal QB to obtain a classification signal Ocheck representing whether the power grid is overvoltage or undervoltage, and determine whether the power grid is overvoltage or undervoltage by using the classification signal Ocheck. In this embodiment, when the classification signal Ocheck is at a high level, it indicates that the power grid generates overvoltage or undervoltage, and when the classification signal Ocheck is at a low level, it indicates that the power grid is normal.
In this embodiment, when the edge detection module 70 does not detect the rising edges of the first and second feature signals VERA and VERB, the first and second classification signals QA and QB are at a low level, and when the edge detection module 70 detects the rising edges of the first and second feature signals VERA and VERB, the first and second classification signals QA and QB are transitioned to a high level, but a time difference may be generated at the transition time of the first and second classification signals QA and QB, so that a result of a logic operation performed on the first and second classification signals QA and QB is erroneous (for example, when one of the first and second classification signals QA and QB is transitioned to a high level, the other is still at a low level, and a result of a logic operation is erroneous), resulting in a functional anomaly of the over-under voltage detection. Moreover, when the edge detection module 70 does not detect the rising edges of the first and second feature signals VERA and VERB, or does not start the under-voltage detection, the first classification signal QA and the second classification signal QB are at low levels, and the two low levels are logically operated, which may also cause the classification signal Ocheck to be at high level, thereby causing the function of the under-voltage detection to be abnormal.
Based on this, in order to ensure the correct output of the classification signal Ocheck, the classification signal Ocheck needs to be delayed for a period of time to be output. In this embodiment, the output of the classification signal Ocheck is controlled by the third enable signal valid. Specifically, the classifying module 80 is further connected to the counter module 50, and after the classifying module 80 performs a logic operation on the first classification signal QA and the second classification signal QB, the result of the logic operation is further performed with the third enable signal Validation to obtain the classification signal Ocheck.
In this embodiment, the classifying module 80 includes an exclusive nor gate and an and gate, the exclusive nor gate is connected to the edge detecting module 70 and configured to perform exclusive nor operation on the first classifying signal QA and the second classifying signal QB, and the and gate is connected to the counter module 50 and the exclusive nor gate and configured to receive the third enable signal validations and the operation result of the exclusive nor gate and perform and operation on the operation result and the third enable signal validations to obtain the classifying signal Ocheck. Thus, the output time of the classification signal Ocheck may follow the transition time of the third enable signal validity.
Further, in order to ensure the output of the classification signal Ocheck is delayed, the periodic anti-interference detection module 60 has r flip-flops, where r is greater than 1 and less than or equal to n-1, where m and r satisfy the following relationship:
m＝2(r-1)。
at this time, it may be ensured that the third enable signal validity starts later than the first classification signal QA and the second classification signal QB.
Next, the circuit timing of the brown-out detection circuit in this embodiment will be described in detail with reference to table 1 and fig. 3a to 3 c. Table 1 shows characteristics of key signals of the overvoltage and undervoltage detection circuit when the power grid is at normal voltage, overvoltage and undervoltage, and fig. 3a to 3c are circuit timing diagrams of the overvoltage and undervoltage detection circuit when the power grid is at normal voltage, overvoltage and undervoltage, respectively.
Table 1: characteristics of key signals of over-voltage and under-voltage detection circuit when power grid is under normal pressure, over-voltage and under-voltage
Figure BDA0003049812040000171
Referring to fig. 2a, 2b, and 3a, when the over-voltage and under-voltage detection circuit is powered on, the power-on reset unit 21 outputs a power-on reset signal POR, the power-on self-test module 40 is powered on and reset under the control of the power-on reset signal POR, and starts to perform edge detection on the power frequency signal Phase, and each of q periods of the power frequency signal Phase is detected to have a rising edge/falling edge at time T0, and at this time, the second enable signal POST jumps to a high level. Meanwhile, the first voltage comparison module 30 starts to work, as shown in fig. 3a and table 1, when the power grid is at normal voltage, the sampling voltage signal Vsamp is greater than the under-voltage threshold voltage Vunder and smaller than the over-voltage threshold voltage Vover, and the first comparison signal VA may periodically appear at high and low levels (after half-wave rectification, the sampling voltage signal Vsamp only retains a half period of the ac signal of the power grid), which is a rectangular wave signal. The second comparison signal VB is low.
When the second enable signal POST jumps to a high level, the counter module 50 outputs the first enable signal Clear and the third enable signal valid under the control of the second enable signal POST. T1 to T5 are the detection time of one cycle of the first enable signal Clear, and at the time T1, the periodic anti-interference detection module 60 starts to perform edge detection on 4 cycles of the first comparison signal VA and the second comparison signal VB. Since the first comparison signal VA is periodically high and low, there is a continuous rising edge, and at time T2a, the first feature signal VERA jumps to a high level; the second comparison signal VB has no continuous rising edge, and the second feature signal VERB is always kept at a low level.
The edge detection module 70 performs edge detection on the first feature signal VERA and the second feature signal VERB to obtain the first classification signal QA and the second classification signal QB. Since the first characteristic signal VERA is high after the time T2a, there is a rising edge, and at the time T2a the first classification signal QA transitions high; since the second feature signal VERB is always kept low, there is no rising edge, and the second classification signal QB is kept low.
The classifying module 80 performs an exclusive or operation on the first classifying signal QA and the second classifying signal QB, and then performs an and operation on the operation result and the third enable signal validations, and outputs the classifying signal Ocheck at a time point from T4 to T5. At this time, the classification signal Ocheck is at a low level, which indicates that the power grid is in a normal state.
At time T5, the detection time of one period of the first enable signal Clear ends, and after time T5, the zero clearing time is entered, the first feature signal VERA and the second feature signal VERB are cleared, and the detection is restarted after waiting for the next period, and the first classification signal QA and the second classification signal QB may be maintained.
With reference to table 1 and fig. 3b, when the power grid is in overvoltage, the sampling voltage signal Vsamp is greater than the undervoltage threshold voltage Vunder and the overvoltage threshold voltage Vover, and both the first comparison signal VA and the second comparison signal VB periodically have high and low levels (after half-wave rectification, the sampling voltage signal Vsamp only retains a half period of the ac signal of the power grid).
T1 to T5 are the detection time of one cycle of the first enable signal Clear, and at the time T1, the periodic anti-interference detection module 60 starts to perform edge detection on 4 cycles of the first comparison signal VA and the second comparison signal VB. Since the first comparison signal VA and the second comparison signal VB both have high and low levels periodically and have continuous rising edges, the first feature signal VERA jumps to high level at time T2a, and the second feature signal VERB jumps to high level at time T2b (usually, there is a slight time difference between T2a and T2 b).
The edge detection module 70 performs edge detection on the first feature signal VERA and the second feature signal VERB to obtain the first classification signal QA and the second classification signal QB. Since the first and second characteristic signals VERA and VERB are high after time T2a and time T2b, respectively, there are both rising edges, at time T2a, the first classification signal QA transitions to high, and at time T2b, the second classification signal QB transitions to high.
The classifying module 80 performs an exclusive or operation on the first classifying signal QA and the second classifying signal QB, and then performs an and operation on the operation result and the third enable signal validations, and outputs the classifying signal Ocheck at a time point from T4 to T5. At this time, the classification signal Ocheck is at a high level, which indicates that the power grid is in an overvoltage or undervoltage state.
With reference to table 1 and fig. 3c, when the power grid is under voltage, the sampling voltage signal Vsamp is smaller than the under-voltage threshold voltage Vunder and the overvoltage threshold voltage Vover, and the first comparison signal VA and the second comparison signal VB are always kept at a low level.
T1 to T5 are the detection time of one cycle of the first enable signal Clear, and at the time T1, the periodic anti-interference detection module 60 starts to perform edge detection on 4 cycles of the first comparison signal VA and the second comparison signal VB. Since the first comparison signal VA and the second comparison signal VB are both low level, there is no continuous rising edge, and the first feature signal VERA and the second comparison signal VB are also always kept low level.
The edge detection module 70 performs edge detection on the first feature signal VERA and the second feature signal VERB to obtain the first classification signal QA and the second classification signal QB. Since the first and second feature signals VERA and VERB are always kept at a low level, there is no rising edge, and the first and second classification signals QA and QB are also kept at a low level.
The classifying module 80 performs an exclusive or operation on the first classifying signal QA and the second classifying signal QB, and then performs an and operation on the operation result and the third enable signal validations, so as to output the classifying signal Ocheck at the time points T4 to T5. At this time, the classification signal Ocheck is at a high level, which indicates that the power grid is in an overvoltage or undervoltage state.
Therefore, whether the power grid is overvoltage or undervoltage can be judged by using the overvoltage and undervoltage detection circuit in the embodiment.
Further, the power grid protection circuit further comprises a leakage protection circuit, wherein the overvoltage and undervoltage detection circuit is connected with the live wire L of the power grid to sample the alternating voltage of the power grid, and the leakage protection circuit receives the leakage voltage Input of the power grid.
The power grid protection circuit integrates the overvoltage and undervoltage detection circuit and the leakage protection circuit, so that the power grid protection circuit has the functions of leakage protection and overvoltage and undervoltage detection, and is simple to apply, high in precision and strong in anti-interference capability.
In this embodiment, the leakage protection circuit, the basic signal generating module 20 of the over-voltage and under-voltage protection circuit, the first voltage comparing module 30 and the control circuit are integrated in the same chip, and the over-detection and under-voltage detection multiplex receives pins of the sampling voltage signal Vsamp. In an optional embodiment, the leakage protection circuit and the overvoltage and undervoltage detection circuit can be integrated in the same chip by adopting a high-voltage process, so that the complexity of the system is reduced, the system is more friendly to application technicians, and meanwhile, the system test and the operation maintenance are facilitated.
Referring to fig. 2a, the leakage protection circuit includes a signal amplifying module 90, a second voltage comparing module, a logic processing module, a delay module 100, and a driving module 110. The power-on reset unit 21 also provides the power-on reset signal POR to the signal amplifying block 90, the delay block 100 and the driving block 110.
Specifically, the signal amplification module 90 is configured to receive a leakage voltage Input of the power grid, and perform signal amplification on the leakage voltage to obtain a voltage amplification signal AmpOut. The second voltage comparison module comprises a fourth comparator Comp4, a positive input terminal of the fourth comparator Comp4 is connected to the signal amplification module 90 for receiving the voltage amplified signal AmpOut, and a positive input terminal of the fourth comparator Comp4 is connected to the reference voltage generation unit 22 for receiving the reference voltage Vref; the fourth comparator Comp4 compares the voltage amplified signal AmpOut with the reference voltage Vref, and then outputs a third comparison signal representing the magnitude relationship between the voltage amplified signal AmpOut and the reference voltage Vref.
The third comparison signal may be used to characterize whether the leakage voltage Input meets the control requirement. Designing the reference voltage Vref as the maximum leakage voltage which can be contained by a system, and when the voltage amplification signal AmpOut is greater than the reference voltage Vref, indicating that the power grid leaks electricity; otherwise, the power grid is normal.
And further, the detection results of the leakage protection circuit and the overvoltage and undervoltage detection circuit are used for controlling the on-off of the power grid together. The logic processing module is connected with the over-voltage and under-voltage detection circuit and the second voltage comparison module, and is configured to receive the third comparison signal and the classification signal Ocheck, and perform logic operation on the third comparison signal and the classification signal Ocheck output by the over-voltage and under-voltage detection circuit to obtain a control signal Ctrl used for controlling the power grid to be switched on and off.
In this embodiment, the logic processing module is an or gate, and the third comparison signal and the classification signal Ocheck are ored to obtain the control signal Ctrl, but not limited thereto.
Further, the delay module 100 is connected to the logic processing module and the reference voltage Vref generating module, and configured to receive a control signal Ctrl and the reference voltage Vref, and perform delay output on the control signal Ctrl, so as to prevent malfunction due to interference in the leakage protection; the driving module 110 is connected to the delay module 100, and configured to receive the delayed control signal Ctrl, enhance the driving capability of the control signal Ctrl, and finally Output the driving signal Output.
Optionally, the driving module 110 is connected to a trip module of the power grid, and controls the trip module through the driving signal Output, so as to control on/off of the power grid.
Fig. 4 is an application diagram of the power grid protection circuit provided in this embodiment. As shown in fig. 4, the signal acquisition module 10 is connected to the live line L of the power grid to acquire the sampling voltage signal Vsamp, and an induction module 130 is connected between the live line L and the zero line N of the power grid and is configured to acquire a leakage voltage Input of the power grid, integrate the leakage protection circuit, the basic signal generation module 20 of the overvoltage/undervoltage protection circuit, the first voltage comparison module 30, and the control circuit on a same chip, and connect a signal Input end of the chip to an output end of the signal acquisition module 10 and an output end of the induction module 130; a tripping module 140 is connected between the live line L and the zero line N of the power grid, the output end of the chip is connected with the tripping module 140, and the on-off of the power grid is controlled by controlling the tripping module 140. Meanwhile, the power grid supplies power to the chip through the power supply module 120.
Example two
The difference from the first embodiment is that, in the present embodiment, when the ac voltage of the power grid is rectified to obtain the rectified signal, the ac voltage of the power grid is full-wave rectified.
Fig. 5a to 5c are circuit timing diagrams of the overvoltage and undervoltage detection circuit when the power grid is at normal voltage, overvoltage and undervoltage, respectively. As can be seen from comparing fig. 3a and 5a, fig. 3b and 5b, and fig. 3c and 5c, when the ac voltage of the power grid is full-wave rectified, the sampling voltage signal Vsamp may reflect the entire period of the ac voltage of the power grid, but the timing of the under-voltage detection circuit does not change, and therefore, the rectification unit may be a full-wave rectification unit for full-wave rectifying the ac voltage of the power grid.
To sum up, in the utility model provides an among the electric wire netting protection circuit, cross the function that undervoltage detection circuitry can realize overvoltage detection and undervoltage detection, overvoltage detection and undervoltage detection multiplex pin, and whole circuit only needs an input port, reduces the scale and the complexity of circuit, is convenient for maintain. Furthermore, m periods of the first comparison signal and the second comparison signal are respectively detected when the first enabling signal is effective, and at the moment, classification signals representing whether the power grid is overvoltage or undervoltage can be generated by using the obtained first characteristic signal and the second characteristic signal, so that overvoltage and undervoltage detection is realized; and because m periods of the first comparison signal and the second comparison signal are detected, the interference of discontinuous time can be resisted, misoperation caused by the interference is prevented, tripping is avoided when the power grid is subjected to instantaneous overvoltage and instantaneous undervoltage fluctuation, and the detection precision and the anti-interference capability are improved. Further, the effective levels of the first characteristic signal and the second characteristic signal are latched to the end of the detection time of each period of the first enable signal, and the effective levels of the first characteristic signal and the second characteristic signal are cleared at the clearing time of each period of the first enable signal, so that the detection of the next period is not influenced. Furthermore, the over-voltage and under-voltage detection circuit and the leakage protection circuit are integrated together, so that the power grid protection circuit has the functions of leakage protection and over-voltage and under-voltage detection, and is simple to apply, high in precision and strong in anti-interference capability; and the leakage protection circuit and the over-voltage and under-voltage detection circuit can be integrated in the same chip, so that the complexity of the system is reduced, the system is more friendly to application technicians, and meanwhile, the system test and operation maintenance are facilitated.
The above description is only for the preferred embodiment of the present invention, and does not limit the present invention. Any technical personnel who belongs to the technical field, in the scope that does not deviate from the technical scheme of the utility model, to the technical scheme and the technical content that the utility model discloses expose do the change such as the equivalent replacement of any form or modification, all belong to the content that does not break away from the technical scheme of the utility model, still belong to within the scope of protection of the utility model.

Claims (22)

1. A power grid protection circuit, comprising: an over-voltage and under-voltage detection circuit, the over-voltage and under-voltage detection circuit comprising:
the signal acquisition module is used for sampling the alternating voltage of the power grid to obtain a sampling voltage signal;
the basic signal generating module is used for generating undervoltage threshold voltage and overvoltage threshold voltage;
the first voltage comparison module is connected with the signal acquisition module and the basic signal generation module and is used for comparing the sampling voltage signal with the undervoltage threshold voltage and the overvoltage threshold voltage respectively to obtain a first comparison signal and a second comparison signal; and the number of the first and second groups,
and the control circuit is connected with the first voltage comparison module and used for respectively detecting m periods of the first comparison signal and the second comparison signal when the first enable signal is effective to obtain a first characteristic signal and a second characteristic signal, and generating a classification signal for representing whether the power grid is overvoltage or undervoltage according to the first characteristic signal and the second characteristic signal, wherein m is more than or equal to 1.
2. The grid protection circuit according to claim 1, wherein the first enable signal is a periodic signal, each period of the first enable signal includes a detection time and a clear time, the first enable signal is active during the detection time and inactive during the clear time, and the detection time is greater than m periods of the first comparison signal and m periods of the second comparison signal.
3. The grid protection circuit according to claim 2, wherein the active levels of the first and second signature signals are latched to the end of the detection time of each cycle of the first enable signal, and the active levels of the first and second signature signals are cleared at the clearing time of each cycle of the first enable signal.
4. A power grid protection circuit according to any of claims 1-3, wherein the control circuit comprises:
the periodic anti-interference detection module is connected with the first voltage comparison module and is used for respectively detecting m periods of the first comparison signal and the second comparison signal when a first enabling signal is effective to obtain a first characteristic signal and a second characteristic signal;
the edge detection module is connected with the periodic anti-interference detection module and is used for respectively carrying out edge detection on the first characteristic signal and the second characteristic signal so as to obtain a first classification signal representing whether the first characteristic signal has a rising edge/a falling edge and a second classification signal representing whether the second characteristic signal has a rising edge/a falling edge; and the number of the first and second groups,
and the classification module is connected with the edge detection module and used for carrying out logic operation on the first classification signal and the second classification signal so as to obtain the classification signal.
5. The grid protection circuit of claim 4, wherein the periodic tamper-resistant detection module performs edge detection on m periods of the first comparison signal and the second comparison signal, respectively, when the first enable signal is active, to obtain the first characteristic signal indicative of whether the first comparison signal has a rising/falling edge per m periods and to obtain the second characteristic signal indicative of whether the second comparison signal has a rising/falling edge per m periods.
6. The power grid protection circuit of claim 4, wherein the first voltage comparison module further compares the sampled voltage signal with a power frequency threshold voltage to obtain a power frequency signal representing a magnitude relationship between the sampled voltage signal and the power frequency threshold voltage;
and, the control circuit further comprises:
and the counter module is connected with the periodic anti-interference detection module and the first voltage comparison module and is used for generating the first enabling signal according to the power frequency signal.
7. The grid protection circuit of claim 6, wherein the counter module comprises:
the frequency division unit is connected with the first voltage comparison module and is used for executing p frequency division for n times on the power frequency signal to obtain n-level frequency division signals, wherein n and p are more than or equal to 2; and the number of the first and second groups,
and the logic operation unit is connected with the frequency dividing unit and is used for performing logic operation on the 2 nd-level frequency dividing signal to the nth-level frequency dividing signal to obtain the first enabling signal.
8. The grid protection circuit of claim 7, wherein a pulse width of the first enable signal is equal to a sum of pulse widths of the level 2 frequency divided signal through the level n frequency divided signal.
9. The grid protection circuit of claim 7, wherein the control circuit further comprises:
and the power-on self-test module is connected with the first voltage comparison module, the counter module and the periodic anti-interference detection module, and is used for performing edge detection on q periods of the power frequency signal according to a power-on reset signal, generating an effective second enabling signal when each period has a rising edge/a falling edge in the q periods of the power frequency signal, and controlling the counter module and the periodic anti-interference detection module to start working, wherein q is more than or equal to 1.
10. The grid protection circuit of claim 9, wherein the rising edges of the second enable signal and the nth level frequency divided signal are separated by g cycles of the power frequency signal, wherein g and n satisfy the following relationship:
g＝2(n-1)。
11. the grid protection circuit of claim 9, wherein the power-on self-test module has s flip-flops, wherein s ≧ 1, q and s satisfy the following relationship:
q＝2(s-1)。
12. the grid protection circuit according to claim 7, wherein the classifying module is further connected to the counter module, and configured to receive the nth-level frequency-divided signal, perform a logic operation on the first classified signal and the second classified signal, and perform a logic operation on a result of the logic operation and the nth-level frequency-divided signal to obtain the classified signal.
13. The grid protection circuit of claim 12, wherein the classification module comprises:
the exclusive-nor gate is connected with the edge detection module and is used for carrying out exclusive-nor operation on the first classification signal and the second classification signal; and the number of the first and second groups,
and the AND gate is connected with the counter module and the XNOR gate and is used for performing AND operation on the result of the XNOR operation and the nth-level frequency division signal to obtain the classification signal.
14. The grid protection circuit according to claim 7, wherein said periodic anti-jamming detection module has r flip-flops, where 1 < r ≦ n-1, and m and r satisfy the following relationship:
m＝2(r-1)。
15. the grid protection circuit of claim 1, wherein the signal acquisition module comprises:
the rectification unit is used for rectifying the alternating voltage of the power grid to obtain a rectification signal; and the number of the first and second groups,
and the voltage division unit is connected with the rectification unit and used for dividing the voltage of the rectification signal to obtain the sampling voltage signal.
16. The grid protection circuit of claim 1, wherein the base signal generation module comprises:
a reference voltage generating unit for generating a reference voltage; and the number of the first and second groups,
the voltage stabilizing unit is connected with the reference voltage generating unit and is used for generating the undervoltage threshold voltage, the overvoltage threshold voltage and the power frequency threshold voltage according to the reference voltage;
and the stabilized voltage power supply is connected with the reference voltage generation unit and used for generating constant power supply voltage according to the reference voltage.
17. The grid protection circuit of claim 9, wherein the base signal generation module further comprises:
and the power-on reset unit is used for generating the power-on reset signal.
18. The power grid protection circuit according to claim 1, further comprising a leakage protection circuit, wherein the leakage protection circuit is configured to detect whether the power grid leaks electricity, and control the power grid to be turned on or off according to a leakage detection result and the classification signal.
19. The grid protection circuit of claim 18, wherein the leakage protection circuit comprises:
the signal amplification module is connected with the power grid and used for amplifying the leakage voltage of the power grid to obtain a voltage amplification signal;
the second voltage comparison module is connected with the signal amplification module and used for comparing the voltage amplification signal with a reference voltage to obtain a third comparison signal; and the number of the first and second groups,
and the logic processing module is connected with the over-voltage and under-voltage detection circuit and the second voltage comparison module and is used for carrying out logic operation on the third comparison signal and the classification signal to obtain a control signal for controlling the on-off of the power grid.
20. The grid protection circuit of claim 19, wherein the leakage protection circuit further comprises:
the delay module is connected with the logic processing module and is used for delaying the control signal and then outputting the delayed control signal; and the number of the first and second groups,
and the driving module is connected with the time delay module and used for enhancing the driving capability of the delayed control signal and then outputting the enhanced control signal.
21. A power grid protection circuit as claimed in any of claims 18 to 20, wherein the leakage protection circuit is integrated on the same chip as the base signal generation module, the first voltage comparison module and the control circuit.
22. A power grid protection circuit as claimed in any of claims 18 to 20, wherein the leakage protection circuit and the under-voltage detection circuit are integrated in the same chip.
CN202120941800.9U 2021-04-30 2021-04-30 Power grid protection circuit Active CN214626351U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202120941800.9U CN214626351U (en) 2021-04-30 2021-04-30 Power grid protection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202120941800.9U CN214626351U (en) 2021-04-30 2021-04-30 Power grid protection circuit

Publications (1)

Publication Number Publication Date
CN214626351U true CN214626351U (en) 2021-11-05

Family

ID=78406466

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202120941800.9U Active CN214626351U (en) 2021-04-30 2021-04-30 Power grid protection circuit

Country Status (1)

Country Link
CN (1) CN214626351U (en)

Similar Documents

Publication Publication Date Title
CN111934403B (en) Sampling resistor short-circuit protection circuit and method, and quick-charging charger
CN107276025B (en) Electric leakage detection device
CN112068040A (en) Connection detection circuit and method and electric equipment
CN103050932A (en) Electronic switch circuit for power over Ethernet
CN103257272A (en) Power failure detection circuit and detection method for alternating current (AC) power supply
CN214626351U (en) Power grid protection circuit
CN110957698A (en) Protective circuit for electrical equipment
US5587916A (en) Low voltage sensing circuits for battery powered devices having a micro-processor
CN202870156U (en) Full decompression detection circuit
CN105467333A (en) Switching power supply no-load detection circuit and detection method
CN105675977B (en) A kind of electric energy meter and method with front stage detection of power loss
CN113131451A (en) Power grid protection circuit and method
CN113075534B (en) Power chip detection circuit, power chip detection method and device and electronic equipment
CN112448370A (en) Primary side control circuit and control method and isolated power supply conversion circuit
CN103472354A (en) Switching-closing judging circuit of electric leakage reclosure breaker
CN203502529U (en) Switching on/of judging circuit of electric leakage reclosure breaker
CN109586363B (en) Charging circuit
EP3375083B1 (en) Overvoltage protection circuit for a power converter
CN211878084U (en) Power failure warning circuit and electronic equipment
CN110971226A (en) Standby mode control method and control system
CN203722482U (en) Over-current detection circuit of frequency converter, frequency converter and microwave oven
US20230106017A1 (en) Buck Circuit, Buck Apparatus, and Circuit Control Method
CN204258771U (en) AC/DC logic input. interface circuit and comprise its integrated circuit
US11343887B2 (en) Adaptive bleeder control method and circuit
CN217847075U (en) MCU power-on control circuit

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant