CN214623378U - Input and output integrated design circuit with two bus controls - Google Patents

Abstract

The utility model provides a design circuit integrating the input and output of two-bus control, which comprises an ARM processor chip, an active or passive input interface circuit, a switching value output control interface circuit, a rectifier bridge chip, a power conversion chip, a two-bus communication conversion chip, two-bus communication indicator lamps, a two-bus transceiving control chip, a communication and operation indicator lamp circuit, a program downloading and debugging circuit, a dial switch circuit and an external interface circuit; the two buses can be effectively used for detecting the active or passive input of external equipment and controlling switching value output equipment, and when the detection is abnormal, a client can be timely notified to maintain through the host.

Description

Input and output integrated design circuit with two bus controls

Technical Field

The utility model relates to a circuit detection area, concretely relates to collect two bus control's input and output in the design circuit of an organic whole.

Background

Two buses use very extensively in fields such as our fire control, gas, instrument and meter, sensor, industrial control, the utility model discloses an use two buses to detect the active or passive input of external equipment, the output of control switching value equipment. Whether the equipment is normally detected or controlled is directly closely related to production and life safety. However, at present, no good communication mode is available for detecting the input or control of the equipment, and the equipment cannot be used universally in the field of industry, and is not fast and efficient.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to solve above-mentioned problem, provide the input and the output of collection two bus controls in the design circuit of an organic whole, can carry out the detection of the active or passive input of external equipment, the control of switching value output device through the input that adopts collection two bus controls and output in the design circuit of an organic whole by two buses, when detecting unusually, can in time inform the customer through the host computer and maintain.

In order to achieve the purpose, the utility model adopts the following technical scheme.

The design circuit integrates input and output controlled by two buses, and comprises an ARM processor chip, an active or passive input interface circuit, a switching value output control interface circuit, a rectifier bridge chip, a power supply conversion chip, two bus communication conversion chips, a communication indicator lamp circuit, two bus transceiving control circuits, an operation indicator lamp circuit, a program downloading and debugging circuit, a dial switch circuit and an external interface circuit.

Further, the ARM processor chip N6; the active or passive input interface circuit N2, the switching value output control interface circuits K1 and K2; the rectifier bridge chip N1; the power supply conversion chip N4; the two-bus communication conversion chip N5; the communication indicator lamp circuits VD4, VD5 and VD 10; the two bus transceiving control circuits VT1, R1 and R2; the running indicator lamp circuit VD 11; the program download debugging circuit XS 1; the dial switch S1; the external interface circuit XS 2.

Further, the ARM processor chip N6 is connected with the active or passive input interface circuit N2, the switching value output control interface circuits K1 and K2, the power conversion chip N4, the two-bus communication conversion chip N5, the communication indicator lamp circuits VD4, VD5, and VD10, the operation indicator lamp circuit VD11, the program download debugging circuit XS1, and the dial switch S1, respectively, for controlling the operation of each part of the circuit.

Further, the active or passive input interface circuit N2 is connected to the external interface circuit XS2 for detecting an active or passive input of an external device; the switching value output control interface circuits K1 and K2 are connected with the external interface circuit XS2 and are used for controlling the output of the switching value equipment; the two bus transceiver control circuits VT1, R1 and R2 are connected to the external interface circuit XS2, and are used for receiving and transmitting data with two bus masters.

Further, the power conversion chip N4 is used for converting an input power voltage into a voltage that can be normally used by the circuit and then supplying power to each part of the control circuit; the two-bus communication conversion chip N5, the communication indicator lamp circuits VD4, VD5 and VD10 are used for a communication indicator lamp when data communication is carried out with a two-bus master station; the program download debug circuitry XS3 is used for programming and debugging of firmware.

Further, the rectifier bridge chip N1 is used for the non-polar input of the two buses; the operation indicator lamp circuit VD11 is used for indicating the normal operation of the system; the program downloading debugging circuit XS1 is used for programming and debugging the firmware; the dial switch circuit S1 is used for addressing the substation equipment when communicating with the two bus master stations; the external interface circuit XS2 is connected to the rectifier bridge chip N1, is used for not distinguishing input polarity of a bus, is connected to the active or passive input interface circuit N2, is used for detecting active or passive input of an external device, and is connected to the switching value output control interface circuits K1 and K2, and is used for controlling output of the switching value device.

The detection method integrating the input and the output of the two-bus control is characterized in that a design circuit integrating the input and the output of the two-bus control is adopted, and the steps are as follows: the 21 pin of the ARM processor chip N6 outputs high and low level with a period of 0.5 Hz; the ARM processing chip N6 reads the set address state of the dial switch S1; the switching value output control interface circuits K1 and K2 are disconnected; the data communication with the two bus master stations is carried out, so that the active or passive detection of the input of the external equipment is carried out, and the control of the switching value output equipment is carried out.

Further, when the two buses detect external input, the 32 pins of the ARM processor chip N6 set an input mode; the active or passive input interface circuit N2 detects an external device input; the active or passive input interface circuit N2, when detecting an anomaly, transmits a fault message to both bus masters. The ARM processor chip N6 is connected with the two bus communication conversion chip N5 to carry out data communication with the two bus master stations; the ARM processor chip N6 is connected with the communication indicator lamps VD4, VD5 and VD10 to carry out LED display during data communication.

Further, when the two buses control the output of the switching value device, pin 39 of the ARM processor chip N6 outputs a high level; the switching value output controls the level output of an interface circuit K1; the 10 pins of the ARM processor chip N6 output pulse levels; the switching value output controls the pulse output of the interface circuit K2; the ARM processor chip N6 is connected with the two bus communication conversion chip N5 to carry out data communication with the two bus master stations; the ARM processor chip N6 is connected with the communication indicator lamps VD4, VD5 and VD10 to carry out LED display during data communication.

The utility model discloses collect two bus control's input and output in the positive effect of design circuit and detection method of an organic whole are:

the utility model discloses an input and output that adopt two bus control of collection can carry out the detection of the active or passive input of external equipment, the control of switching value output device by two buses of effectual use in the design circuit of an organic whole, when detecting unusually, can in time inform the customer in time to maintain through the host computer.

Drawings

FIG. 1 is a block diagram of the circuit connection of the present invention;

FIG. 2 is a circuit diagram of the power conversion part of the present invention;

fig. 3 is a circuit diagram of the active or passive input interface portion of the present invention;

fig. 4 is a circuit diagram of the switching value output control interface part of the present invention;

FIG. 5 is a circuit diagram of the rectifier bridge part and the two-bus transceiver control part of the present invention;

fig. 6 is a circuit diagram of the external interface portion of the present invention;

fig. 7 is a circuit diagram of the two-bus communication conversion part of the present invention;

fig. 8 is a circuit diagram of the communication indicator light part of the present invention;

fig. 9 is a circuit diagram of the operation indicating lamp part of the present invention;

fig. 10 is a circuit diagram of a program downloading section of the present invention;

FIG. 11 is a circuit diagram of the addressing portion of the apparatus of the present invention;

fig. 12 is a circuit diagram of the ARM processor portion of the present invention.

Detailed Description

The following detailed description of the design circuit integrating the input and output of the two-bus control according to the present invention is provided with the accompanying drawings, but it should be noted that: the described embodiments are not intended to limit the practice of the invention. All adopt the utility model discloses a similar structure and similar change all should go into the utility model discloses a protection scope. The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced.

See fig. 1-12. The design circuit integrates input and output controlled by two buses, and is characterized by comprising an ARM processor chip, an active or passive input interface circuit, a switching value output control interface circuit, a rectifier bridge chip, a power conversion chip, a two-bus communication conversion chip, a communication indicator lamp circuit, a two-bus transceiving control circuit, an operation indicator lamp circuit, a program downloading and debugging circuit, a dial switch circuit and an external interface circuit.

The ARM processor chip N6; the active or passive input interface circuit N2, the switching value output control interface circuits K1 and K2; the rectifier bridge chip N1; the power supply conversion chip N4; the two-bus communication conversion chip N5; the communication indicator lamp circuits VD4, VD5 and VD 10; the two bus transceiving control circuits VT1, R1 and R2; the running indicator lamp circuit VD 11; the program download debugging circuit XS 1; the dial switch S1; the external interface circuit XS 2.

The ARM processor chip N6 is respectively connected with the active or passive input interface circuit N2, the switching value output control interface circuits K1 and K2, the power conversion chip N4, the two-bus communication conversion chip N5, the communication indicator lamp circuits VD4, VD5 and VD10, the operation indicator lamp circuit VD11, the program downloading and debugging circuit XS1 and the dial switch S1, and is used for controlling the work of each part of the circuit.

The active or passive input interface circuit N2 is connected with the external interface circuit XS2 and is used for detecting active or passive input of an external device; the switching value output control interface circuits K1 and K2 are connected with the external interface circuit XS2 and are used for controlling the output of the switching value equipment; the two bus transceiver control circuits VT1, R1 and R2 are connected to the external interface circuit XS2, and are used for receiving and transmitting data with two bus masters.

The power supply conversion chip N4 is used for converting the input power supply voltage into the voltage which can be normally used by the circuit and then supplying power to all parts of the control circuit; the two-bus communication conversion chip N5, the communication indicator lamp circuits VD4, VD5 and VD10 are used for a communication indicator lamp when data communication is carried out with a two-bus master station; the program download debug circuitry XS3 is used for programming and debugging of firmware.

The rectifier bridge chip N1 is used for the non-polar input of a two-bus; the operation indicator lamp circuit VD11 is used for indicating the normal operation of the system; the program downloading debugging circuit XS1 is used for programming and debugging the firmware; the dial switch circuit S1 is used for addressing the substation equipment when communicating with the two bus master stations; the external interface circuit XS2 is connected to the rectifier bridge chip N1, is used for not distinguishing input polarity of a bus, is connected to the active or passive input interface circuit N2, is used for detecting active or passive input of an external device, and is connected to the switching value output control interface circuits K1 and K2, and is used for controlling output of the switching value device.

The detection method integrating the input and the output of the two-bus control is characterized in that a design circuit integrating the input and the output of the two-bus control is adopted, and the steps are as follows: the 21 pin of the ARM processor chip N6 outputs high and low level with a period of 0.5 Hz; the ARM processing chip N6 reads the set address state of the dial switch S1; the switching value output control interface circuits K1 and K2 are disconnected; the data communication with the two bus master stations is carried out, so that the active or passive detection of the input of the external equipment is carried out, and the control of the switching value output equipment is carried out.

When the two buses detect external input, the 32 pins of the ARM processor chip N6 set an input mode; the active or passive input interface circuit N2 detects an external device input; the active or passive input interface circuit N2, when detecting an anomaly, transmits a fault message to both bus masters. The ARM processor chip N6 is connected with the two bus communication conversion chip N5 to carry out data communication with the two bus master stations; the ARM processor chip N6 is connected with the communication indicator lamps VD4, VD5 and VD10 to carry out LED display during data communication.

When the two buses control the output of the switching value equipment, the pin 39 of the ARM processor chip N6 outputs high level; the switching value output controls the level output of an interface circuit K1; the 10 pins of the ARM processor chip N6 output pulse levels; the switching value output controls the pulse output of the interface circuit K2; the ARM processor chip N6 is connected with the two bus communication conversion chip N5 to carry out data communication with the two bus master stations; the ARM processor chip N6 is connected with the communication indicator lamps VD4, VD5 and VD10 to carry out LED display during data communication.

The model of the ARM processor chip N6 is GD32E230C8T 6; the model of the rectifier bridge chip N1 is ABS 210; the model of the power management chip N4 is JW 5026; the model of the two-bus communication conversion chip N5 is PB331, and the models of the communication indicator lamp VD4, the communication indicator lamp VD5 and the communication indicator lamp VD10 are NCD0603G 2; the model numbers of the two-bus transceiving control chips VT1, R1 and R2 are MMBTA06LT3G, 0603WAF2703T5E and 0603WAF2002T 5E; the running indicator lamp VD11 is NCD0603G 2; the active or passive input interface circuit N2 is MB 6S; the switching value output control interface circuits K1 and K2 are model SRA-24VDC-CL (20A); the model of the program downloading debugging circuit XS1 is PZ 254V-11-04P; the model numbers of the chips VT2 and VT3 for driving the relay are DTC143 ZCA; the type of the dial switch S1 is TM-06; the external interface circuit XS2 is model number WJ2 EDGRC-5.08-12P.

The power conversion chip N4 converts the input voltage V _ BUS into 3.3V which can be used by the circuit, and then supplies power to the circuit; 30 pins and 31 pins of the ARM processor chip N6 are connected with 3 pins and 2 pins of the two-bus communication conversion chip N5 and the negative electrodes of the communication indicator lamps VD4 and VD5, and 20 pins of the ARM processor chip N6 are connected with the negative electrode of the communication indicator lamp VD10 and used for data communication with the two-bus master station and displaying the communication indicator lamp through an LED lamp; pins 34 and 37 of the ARM processor chip N6 are respectively connected with pins 2 and 1 of the program downloading debugging circuit XS1, and are used for programming and debugging the firmware. The 39 feet and the 40 feet of the ARM processor chip N6 are connected with the base electrodes of the driving relay chips VT2 and VT3 and are used for disconnection and pull-in of the output control of the switching value equipment; the 32 pins of the ARM processor chip N6 are connected with the 2 pins of the R39 of the detection input, and are used for detecting the active or passive input of an external device. The 10 pins, 11 pins, 12 pins, 13 pins, 14 pins and 15 pins of the ARM processor chip N6 are respectively connected with the 1 pin, 2 pins, 3 pins, 4 pins, 5 pins and 6 pins of the dial switch S1 and used for addressing and setting the substation equipment when the substation communicates with the bus master station. Pins 1 and 2 of the external interface circuit XS2 are respectively connected with pins 1 and 2 of the rectifier bridge chip N1 and are used for not distinguishing the input polarity of the bus; pins 3 and 4 of the external interface circuit XS2 are respectively connected with pin 1 and pin 2 of the rectifier bridge chip N2 and used for detecting the active input of external equipment; pins 5 and 6 of the external interface circuit XS2 are respectively connected with a pin 1 of the rectifier bridge chip N2 and a GND network identifier and used for detecting the passive input of external equipment; pins 7, 8 and 9 of the external interface circuit XS2 are respectively connected with pins 1, 5 and 2 of the relay K1 and are used for controlling the level output of the switching value; pins 10, 11 and 12 of the external interface circuit XS2 are respectively connected with pins 1, 5 and 2 of the relay K2 and are used for controlling the output of the switching value pulse. The 5 feet of the two-bus communication conversion chip N5 are connected with the base electrode of the two-bus transceiving control chip VT 1; the system is used for uploading data of the master station; the 6 feet of the two-bus communication conversion chip N5 are connected between the two-bus transceiving control circuit R1 and the two-bus transceiving control resistor R2, and are used for the communication of master station data. The 21 feet of the ARM processor chip N6 are connected with the cathode of a running indicator lamp VD11 and used for flash indication when the system runs.

Claims (6)

1. The design circuit integrates input and output controlled by two buses, and is characterized by comprising an ARM processor chip, an active or passive input interface circuit, a switching value output control interface circuit, a rectifier bridge chip, a power conversion chip, a two-bus communication conversion chip, a communication indicator lamp circuit, a two-bus transceiving control circuit, an operation indicator lamp circuit, a program downloading and debugging circuit, a dial switch circuit and an external interface circuit.

2. The two-bus controlled input and output integrated design circuit of claim 1, wherein said ARM processor chip N6; the active or passive input interface circuit N2, the switching value output control interface circuits K1 and K2; the rectifier bridge chip N1; the power supply conversion chip N4; the two-bus communication conversion chip N5; the communication indicator lamp circuits VD4, VD5 and VD 10; the two bus transceiving control circuits VT1, R1 and R2; the running indicator lamp circuit VD 11; the program download debugging circuit XS 1; the dial switch S1; the external interface circuit XS 2.

3. The design circuit integrating two-bus controlled input and output according to claim 2, wherein said ARM processor chip N6 is connected to said active or passive input interface circuit N2, said switching value output control interface circuits K1 and K2, said power conversion chip N4, said two-bus communication conversion chip N5, said communication indicator light circuits VD4, VD5 and VD10, said operation indicator light circuit VD11, said program download debugging circuit XS1 and said dial switch S1 respectively, for controlling the operation of each unit of the circuit.

4. The two-bus controlled input and output integrated design circuit of claim 2, wherein the active or passive input interface circuit N2 is connected to the external interface circuit XS2 for detection of external device active or passive inputs; the switching value output control interface circuits K1 and K2 are connected with the external interface circuit XS2 and are used for controlling the output of the switching value equipment; the two bus transceiver control circuits VT1, R1 and R2 are connected to the external interface circuit XS2, and are used for receiving and transmitting data with two bus masters.

5. The design circuit integrating two-bus control input and output according to claim 2, wherein the power conversion chip N4 is used for converting an input power voltage into a voltage which can be normally used by the circuit and then supplying power to each part of the control circuit; the two-bus communication conversion chip N5, the communication indicator lamp circuits VD4, VD5 and VD10 are used for a communication indicator lamp when data communication is carried out with a two-bus master station; the program download debug circuitry XS3 is used for programming and debugging of firmware.

6. The design circuit integrating two-bus controlled input and output according to claim 2, wherein the rectifier bridge chip N1 is used for non-polar input of two buses; the operation indicator lamp circuit VD11 is used for indicating the normal operation of the system; the program downloading debugging circuit XS1 is used for programming and debugging the firmware; the dial switch circuit S1 is used for addressing the substation equipment when communicating with the two bus master stations; the external interface circuit XS2 is connected to the rectifier bridge chip N1, is used for not distinguishing input polarity of a bus, is connected to the active or passive input interface circuit N2, is used for detecting active or passive input of an external device, and is connected to the switching value output control interface circuits K1 and K2, and is used for controlling output of the switching value device.

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