CN214586615U - High PSRR low dropout regulator circuit with high output voltage - Google Patents
High PSRR low dropout regulator circuit with high output voltage Download PDFInfo
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- CN214586615U CN214586615U CN202120802566.1U CN202120802566U CN214586615U CN 214586615 U CN214586615 U CN 214586615U CN 202120802566 U CN202120802566 U CN 202120802566U CN 214586615 U CN214586615 U CN 214586615U
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Abstract
The utility model relates to a high PSRR low dropout linear regulator circuit with high output voltage, through setting up a charge pump, be connected with the error amplifier electricity and supply power for the partial structure of error amplifier, and set up the voltage value that the charge pump produced the size and be second voltage value VDDH, and second voltage value is greater than first voltage value VDD that first voltage value and second voltage source produced voltage, make the charge pump can be under the condition that first voltage value VDD supplied power, produce the second voltage value VDDH that is greater than first voltage value VDD, make the voltage value of a point rise, can not again first voltage value VDD subtract an overdrive voltage Vov, thereby make the voltage of output point vout rise, newly increased components and parts are few, with low costs easy operation.
Description
Technical Field
The present invention relates to a low dropout regulator, and more particularly to a high PSRR low dropout regulator circuit with high output voltage.
Background
The power supply rejection ratio, known in english as PSSR, mainly describes the effect of the operational amplifier on suppressing the power supply voltage variation. The power supply rejection ratio is defined as the degree of offset per volt of supply voltage variation, typically in microvolts per volt (uV/V). In a conventional low dropout regulator (LDO) circuit with a high PSRR, as shown in fig. 3, an NMOS transistor is generally provided as a regulating transistor N1 to reduce the influence of the fluctuation of the power supply voltage on the output voltage.
However, the conventional high PSRR ldo regulator circuit has a problem in that it is difficult to obtain a high output voltage. Since the voltage at the point a is smaller than VDD by at least one overdrive voltage Vov, the threshold voltage Vth of the regulating transistor N1 is reduced from the point a to the output point vout, and the maximum value of the voltage at the output point vout reaches VDD-Vov-Vth without considering other voltage losses.
SUMMERY OF THE UTILITY MODEL
Therefore, it is necessary to provide a high PSRR low dropout regulator circuit with a high output voltage to solve the problem that the conventional high PSRR low dropout regulator circuit is difficult to obtain a high output voltage.
The application provides a high PSRR low dropout regulator circuit with high output voltage includes: a DC voltage source, the negative pole of which is grounded;
the non-inverting input end of the error amplifier is electrically connected with the positive electrode of the direct-current voltage source;
a first voltage source electrically connected to the error amplifier;
the grid electrode of the first NMOS tube is electrically connected with the output end of the error amplifier;
the second voltage source is electrically connected with the drain electrode of the first NMOS tube; the voltage values of the voltages generated by the first voltage source and the second voltage source are equal and are first voltage values;
the NMOS transistor comprises a first resistor and a second resistor which are connected in series, wherein one end of the first resistor is electrically connected with a source electrode of the first NMOS transistor, and the other end of the first resistor is electrically connected with the second resistor; one end of the second resistor is electrically connected with the first resistor, and the other end of the second resistor is grounded; the inverting input end of the error amplifier is electrically connected to a connection link between the first resistor and the second resistor;
the charge pump is electrically connected with the error amplifier and is used for generating voltage with a second voltage value; the second voltage value is greater than the first voltage value.
The utility model relates to a high PSRR low dropout linear regulator circuit with high output voltage, through setting up a charge pump, be connected with the error amplifier electricity and supply power for the partial structure of error amplifier, and set up the voltage value that the charge pump produced the size and be second voltage value VDDH, and second voltage value is greater than first voltage value VDD that first voltage value and second voltage source produced voltage, make the charge pump can be under the condition that first voltage value VDD supplied power, produce the second voltage value VDDH that is greater than first voltage value VDD, make the voltage value of a point rise, can not again first voltage value VDD subtract an overdrive voltage Vov, thereby make the voltage of output point vout rise, newly increased components and parts are few, with low costs easy operation.
Drawings
Fig. 1 is a schematic diagram of a high PSRR low dropout regulator circuit with a high output voltage according to an embodiment of the present application;
fig. 2 is a schematic diagram of a high PSRR low dropout regulator circuit with a high output voltage according to another embodiment of the present application;
fig. 3 is a schematic diagram of a conventional high PSRR low dropout regulator circuit.
Reference numerals:
10-a direct current voltage source; 20-an error amplifier; 210-a first PMOS tube;
211-source of the first PMOS transistor; 212-drain of first PMOS tube;
213-grid of the first PMOS tube; 220-a second PMOS tube; 221-a gate of a second PMOS transistor;
222-a source of a second PMOS transistor; 223-the drain electrode of the second PMOS tube; 230-third PMOS tube;
231-source of third PMOS transistor; 232-grid electrode of third PMOS tube;
233-drain of third PMOS transistor; 240-fourth PMOS tube; 241-source of the fourth PMOS tube;
242-the gate of the fourth PMOS transistor; 243-drain electrode of fourth PMOS tube; 250-fifth PMOS tube;
251-a source electrode of a fifth PMOS tube; 252-the grid electrode of the fifth PMOS tube;
253-drain electrode of fifth PMOS tube; 260-second NMOS tube; 261-drain of second NMOS transistor;
262-gate of second NMOS transistor; 263-drain of the second NMOS transistor; 270-a third NMOS transistor;
271-drain electrode of the third NMOS tube; 272-the gate of the third NMOS transistor;
273-source electrode of the third NMOS tube; 280-fourth NMOS transistor; 281-drain electrode of the fourth NMOS tube;
282-source of fourth NMOS transistor; 283-the grid electrode of the fourth NMOS tube; 290-fifth NMOS transistor;
291-drain electrode of a fifth NMOS tube; 292-the source electrode of the fifth NMOS tube;
293-grid electrode of a fifth NMOS tube; 21-the non-inverting input of the error amplifier;
22-the inverting input of the error amplifier; 23-the output of the error amplifier; 30-a first voltage source;
40-first NMOS tube; 410-the gate of the first NMOS transistor; 420-drain electrode of the first NMOS tube;
430-source of the first NMOS transistor; 50-a second voltage source; 60-a first resistance; 70-a second resistance;
80-a charge pump; 90-bias voltage generating circuit
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The application provides a control method of a high PSRR low dropout linear regulator circuit with high output voltage.
As shown in fig. 1, in an embodiment of the present application, the high PSRR low dropout regulator circuit with a high output voltage includes a dc voltage source 10, an error amplifier 20, a first voltage source 30, a first NMOS transistor 40, a second voltage source 50, a first resistor 60, a second resistor 70, and a charge pump 80.
The negative terminal of the dc voltage source 10 is grounded. The positive electrode of the dc voltage source 10 is electrically connected to the non-inverting input terminal 21 of the error amplifier 20. The first voltage source 30 is electrically connected to the error amplifier 20. The gate 410 of the first NMOS transistor 40 is electrically connected to the output 23 of the error amplifier 20. The second voltage source 50 is electrically connected to the drain 420 of the first NMOS transistor 40.
The first resistor 60 and the second resistor 70 are connected in series. One end of the first resistor 60 is electrically connected to the source 430 of the first NMOS transistor 40. The other end of the first resistor 60 is electrically connected to the second resistor 70. One end of the second resistor 70 is electrically connected to the first resistor 60. The other end of the second resistor 70 is grounded. The inverting input 22 of the error amplifier 20 is electrically connected to the connection between the first resistor 60 and the second resistor 70. The charge pump 80 is electrically connected to the error amplifier 20.
The voltage values of the voltages generated by the first voltage source 30 and the second voltage source 50 are equal and are both the first voltage value. The charge pump 80 generates a voltage with a second voltage value. The second voltage value is greater than the first voltage value.
Specifically, in the present application, a new voltage source, i.e., a charge pump 80(charge pump), is connected to a side of the error amplifier 20 close to the output branch (i.e., a side where the second voltage source 50, the first resistor 60, and the second resistor 70 are distributed). The charge pump 80 can generate a second voltage value VDDH greater than the first voltage value VDD while the first voltage source 30 supplies the error amplifier 20 with the voltage of the first voltage value VDD. In this way, the voltage at point a is increased, and is no longer the first voltage value VDD minus the overdrive voltage Vov, and the voltage at point a may even be larger than the first voltage value VDD. The voltage value at the point a becomes the voltage value at the output point vout after the voltage drop of the first NMOS transistor 40. The voltage value at the output point vout is greatly increased compared with the conventional scheme.
In this embodiment, a charge pump is provided, and is electrically connected to the error amplifier to supply power to a partial structure of the error amplifier, and the charge pump is configured to generate a voltage value of VDDH, where the voltage value is greater than the first voltage value VDD generated by the first voltage source and the second voltage source, so that the charge pump can generate VDDH greater than the first voltage value VDD under the condition that the first voltage value VDD supplies power, so that the voltage value at the point a is raised, and an overdrive voltage Vov is not subtracted from the first voltage value VDD any more, so that the voltage at the output point vout is raised, and the charge pump has fewer newly added components, is low in cost, and is easy to operate.
As shown in fig. 2, in an embodiment of the present application, the error amplifier 20 includes a first PMOS transistor 210. The source 211 of the first PMOS transistor 210 is electrically connected to the first voltage source 30.
Referring to fig. 2, in an embodiment of the present application, the error amplifier 20 further includes a second PMOS transistor 220. The gate 221 of the second PMOS transistor 220 is electrically connected to the dc voltage source 10. The source 222 of the second PMOS transistor 220 is electrically connected to the drain 212 of the first PMOS transistor 210.
Referring to fig. 2, in an embodiment of the present application, the error amplifier 20 further includes a third PMOS transistor 230. The source 231 of the third PMOS transistor 230 is electrically connected to the drain 212 of the first PMOS transistor 210. The source 231 of the third PMOS transistor 230 is also electrically connected to the source 222 of the second PMOS transistor 220. The gate 232 of the third PMOS transistor 230 is electrically connected to the connection link between the first resistor 60 and the second resistor 70.
The drain 212 of the first PMOS transistor 210 is electrically connected to the connection link between the source 222 of the second PMOS transistor 220 and the source 231 of the third PMOS transistor 230.
Referring to fig. 2, in an embodiment of the present application, the error amplifier 20 further includes a fourth PMOS transistor 240. The source 241 of the fourth PMOS transistor 240 is electrically connected to the charge pump 80. The gate 242 of the fourth PMOS transistor 240 is electrically connected to the drain 243 of the fourth PMOS transistor 240.
Referring to fig. 2, in an embodiment of the present application, the error amplifier 20 further includes a fifth PMOS transistor 250. The source 251 of the fifth PMOS transistor 250 is electrically connected to the charge pump 80. The source 251 of the fifth PMOS transistor 250 is also electrically connected to the source 241 of the fourth PMOS transistor 240. The gate 252 of the fifth PMOS transistor 250 is electrically connected to the gate 242 of the fourth PMOS transistor 240. The drain 253 of the fifth PMOS transistor 250 is electrically connected to the gate 410 of the first NMOS transistor 40.
Referring to fig. 2, in an embodiment of the present application, the error amplifier 20 further includes a second NMOS transistor 260 and a third NMOS transistor 270.
The drain electrode 261 of the second NMOS tube 260 is electrically connected to the drain electrode 243 of the fourth PMOS tube 240. The drain 271 of the third NMOS transistor 270 is electrically connected to the drain 253 of the fifth PMOS transistor 250. The gate 272 of the third NMOS transistor 270 is electrically connected to the gate 262 of the second NMOS transistor 260.
Referring to fig. 2, in an embodiment of the present application, the error amplifier 20 further includes a fourth NMOS transistor 280 and a fifth NMOS transistor 290. The drain electrode 281 of the fourth NMOS transistor 280 is electrically connected to the source electrode 263 of the second NMOS transistor 260. The source 282 of the fourth NMOS transistor 280 is grounded. The drain 291 of the fifth NMOS transistor 290 is electrically connected to the source 273 of the third NMOS transistor 270. The source 292 of the fifth NMOS transistor 290 is grounded. The gate 283 of the fourth NMOS transistor 280 is electrically connected to the gate 293 of the fifth NMOS transistor 290.
The drain electrode 223 of the second PMOS transistor 220 is electrically connected to the connection link between the source electrode 263 of the second NMOS transistor 260 and the drain electrode 281 of the fourth NMOS transistor 280. The drain 233 of the third PMOS transistor 230 is electrically connected to the connection link between the source 273 of the third NMOS transistor 270 and the drain 291 of the fifth NMOS transistor 290.
Specifically, the above embodiment mainly introduces the specific structure of the error amplifier 20.
With reference to fig. 2, in an embodiment of the present application, the high PSRR low dropout regulator circuit with high output voltage further includes a bias voltage generating circuit 90. The bias voltage generating circuit 90 is electrically connected to the gate 213 of the first PMOS transistor 210. The bias voltage generating circuit 90 is also electrically connected to a connection link between the gate 262 of the second NMOS transistor 260 and the gate 272 of the third NMOS transistor 270. The bias voltage generating circuit 90 is further electrically connected to a connection link between the gate electrode 283 of the fourth NMOS transistor 280 and the gate electrode 293 of the fifth NMOS transistor 290.
Specifically, the bias voltage generating circuit 90 may generate bias voltages with different magnitudes, so as to bias the first PMOS transistor 210, the second NMOS transistor 260, the third NMOS transistor 270, the fourth NMOS transistor 280, and the fifth NMOS transistor 290, so that these transistors are in the appropriate saturation regions, respectively, so that the error amplifier 20 can operate normally. As shown in fig. 2, the gate bias voltage of the first PMOS transistor 210 is vbias _ p. The gate bias voltages of the second NMOS transistor 260 and the third NMOS transistor 270 are vbias _ n 2. The gate bias voltages of the fourth NMOS transistor 280 and the fifth NMOS transistor 290 are vbias _ n 1.
In an embodiment of the present application, the second voltage value is less than or equal to a voltage sum of the first voltage value and a threshold voltage of the first NMOS transistor 40.
Specifically, in the present embodiment, the second voltage value VDDH is greater than the first voltage value VDD, but cannot be greater than the sum of the first voltage value VDD and the threshold voltage Vth of the first NMOS transistor 40, that is, cannot be greater than VDD + Vth. This is not desirable because if the second voltage VDDH is greater than VDD + Vth, the first NMOS transistor 40 is in a linear region, which affects the performance of the first NMOS transistor 40. Therefore, the maximum value of the second voltage value VDDH is VDD + Vth, the maximum value of the voltage value at the point a is VDD + Vth-Vov, and the maximum value of the voltage value at the output point vout is VDD + Vth-Vov-Vth equal to VDD-Vov (because a voltage drop occurs from the point a to the output point vout, and the voltage drops by a threshold voltage Vth).
In this embodiment, the maximum value of the voltage value of the final output point vout is obtained by subtracting an overdrive voltage Vov from the first voltage value VDD, and compared with the maximum value VDD-Vov-Vth of the voltage value of the output point vout in the conventional high PSRR low dropout linear regulator circuit, a threshold voltage Vth is raised.
The technical features of the embodiments described above may be arbitrarily combined, the order of execution of the method steps is not limited, and for simplicity of description, all possible combinations of the technical features in the embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, the combinations of the technical features should be considered as the scope of the present description.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.
Claims (10)
1. A high PSRR low dropout regulator circuit having a high output voltage, comprising:
a direct current voltage source (10), wherein the negative electrode of the direct current voltage source (10) is grounded;
an error amplifier (20), wherein a non-inverting input end (21) of the error amplifier (20) is electrically connected with a positive electrode of the direct current voltage source (10);
a first voltage source (30) electrically connected to the error amplifier (20);
a first NMOS transistor (40), wherein a grid electrode (410) of the first NMOS transistor (40) is electrically connected with an output end (23) of the error amplifier (20);
the second voltage source (50) is electrically connected with the drain electrode (420) of the first NMOS tube (40); the voltage values of the voltages generated by the first voltage source (30) and the second voltage source (50) are equal and are first voltage values;
the NMOS transistor comprises a first resistor (60) and a second resistor (70) which are connected in series, wherein one end of the first resistor (60) is electrically connected with a source electrode (430) of the first NMOS transistor (40), and the other end of the first resistor (60) is electrically connected with the second resistor (70); one end of the second resistor (70) is electrically connected with the first resistor (60), and the other end of the second resistor is grounded; the inverting input end (22) of the error amplifier (20) is electrically connected to a connection link between the first resistor (60) and the second resistor (70);
a charge pump (80) electrically connected to the error amplifier (20) for generating a voltage having a second voltage value; the second voltage value is greater than the first voltage value.
2. The high PSRR low dropout regulator circuit according to claim 1, wherein the error amplifier (20) comprises:
a first PMOS tube (210), wherein the source electrode (211) of the first PMOS tube (210) is electrically connected with the first voltage source (30).
3. The high PSRR low dropout regulator circuit according to claim 2, wherein the error amplifier (20) further comprises:
a second PMOS tube (220), wherein a grid electrode (221) of the second PMOS tube (220) is electrically connected with the direct current voltage source (10), and a source electrode (222) of the second PMOS tube (220) is electrically connected with a drain electrode (212) of the first PMOS tube (210).
4. The high PSRR low dropout regulator circuit according to claim 3, wherein the error amplifier (20) further comprises:
a third PMOS transistor (230), a source (231) of the third PMOS transistor (230) is electrically connected to the drain (212) of the first PMOS transistor (210), a source (231) of the third PMOS transistor (230) is also electrically connected to the source (222) of the second PMOS transistor (220), and a gate (232) of the third PMOS transistor (230) is electrically connected to a connection link between the first resistor (60) and the second resistor (70);
the drain (212) of the first PMOS tube (210) is electrically connected to a connection link between the source (222) of the second PMOS tube (220) and the source (231) of the third PMOS tube (230).
5. The high PSRR low dropout regulator circuit according to claim 4, wherein the error amplifier (20) further comprises:
a fourth PMOS tube (240), wherein a source electrode (241) of the fourth PMOS tube (240) is electrically connected with the charge pump (80), and a grid electrode (242) of the fourth PMOS tube (240) is electrically connected with a drain electrode (243) of the fourth PMOS tube (240).
6. The high PSRR low dropout regulator circuit according to claim 5 having a high output voltage, wherein the error amplifier (20) further comprises:
a fifth PMOS tube (250), wherein a source electrode (251) of the fifth PMOS tube (250) is electrically connected with the charge pump (80), the source electrode (251) of the fifth PMOS tube (250) is also electrically connected with a source electrode (241) of the fourth PMOS tube (240), a gate electrode (252) of the fifth PMOS tube (250) is electrically connected with a gate electrode (242) of the fourth PMOS tube (240), and a drain electrode (253) of the fifth PMOS tube (250) is electrically connected with a gate electrode (410) of the first NMOS tube (40).
7. The high PSRR low dropout regulator circuit according to claim 6, wherein the error amplifier (20) further comprises:
a second NMOS tube (260), wherein a drain electrode (261) of the second NMOS tube (260) is electrically connected with a drain electrode (243) of the fourth PMOS tube (240);
a drain (271) of the third NMOS transistor (270) is electrically connected with the drain (253) of the fifth PMOS transistor (250), and a gate (272) of the third NMOS transistor (270) is electrically connected with the gate (262) of the second NMOS transistor (260).
8. The high PSRR low dropout regulator circuit according to claim 7, wherein the error amplifier (20) further comprises:
a fourth NMOS transistor (280), wherein a drain electrode (281) of the fourth NMOS transistor (280) is electrically connected with a source electrode (263) of the second NMOS transistor (260), and a source electrode (282) of the fourth NMOS transistor (280) is grounded;
a fifth NMOS transistor (290), wherein the drain electrode (291) of the fifth NMOS transistor (290) is electrically connected with the source electrode (273) of the third NMOS transistor (270), and the source electrode (292) of the fifth NMOS transistor (290) is grounded; the grid electrode (283) of the fourth NMOS tube (280) is electrically connected with the grid electrode (293) of the fifth NMOS tube (290);
the drain electrode (223) of the second PMOS tube (220) is electrically connected to a connection link between the source electrode (263) of the second NMOS tube (260) and the drain electrode (281) of the fourth NMOS tube (280); the drain electrode (233) of the third PMOS tube (230) is electrically connected to a connection link between the source electrode (273) of the third NMOS tube (270) and the drain electrode (291) of the fifth NMOS tube (290).
9. The high PSRR low dropout regulator circuit according to claim 8, further comprising:
a bias voltage generating circuit (90) electrically connected to the gate (213) of the first PMOS transistor (210); the bias voltage generating circuit (90) is also electrically connected to a connection link between the grid electrode (262) of the second NMOS tube (260) and the grid electrode (272) of the third NMOS tube (270); the bias voltage generating circuit (90) is also electrically connected to a connection link between the gate (283) of the fourth NMOS transistor (280) and the gate (293) of the fifth NMOS transistor (290).
10. The high PSRR low dropout regulator circuit according to claim 9, wherein the second voltage value is less than or equal to the sum of the first voltage value and the threshold voltage of the first NMOS transistor (40).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120802566.1U CN214586615U (en) | 2021-04-19 | 2021-04-19 | High PSRR low dropout regulator circuit with high output voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120802566.1U CN214586615U (en) | 2021-04-19 | 2021-04-19 | High PSRR low dropout regulator circuit with high output voltage |
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| Publication Number | Publication Date |
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| CN214586615U true CN214586615U (en) | 2021-11-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202120802566.1U Active CN214586615U (en) | 2021-04-19 | 2021-04-19 | High PSRR low dropout regulator circuit with high output voltage |
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| CN (1) | CN214586615U (en) |
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- 2021-04-19 CN CN202120802566.1U patent/CN214586615U/en active Active
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Address after: 311422 4th floor, building 9, Yinhu innovation center, 9 Fuxian Road, Yinhu street, Fuyang District, Hangzhou City, Zhejiang Province Patentee after: Zhejiang Xinmai Microelectronics Co.,Ltd. Address before: 311400 4th floor, building 9, Yinhu innovation center, No.9 Fuxian Road, Yinhu street, Fuyang District, Hangzhou City, Zhejiang Province Patentee before: Hangzhou xiongmai integrated circuit technology Co.,Ltd. |
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