CN214586431U - Intelligent timer based on single chip microcomputer - Google Patents

Abstract

The utility model provides an intelligent timer based on singlechip, the utility model discloses an intelligent timer based on singlechip is provided with single chip module, button module, charactron display module, circuit protection module, falls the electric protection module, calibrates functional display module and bee calling organ module, and button module, charactron display module, circuit protection module, fall the electric protection module, calibrate functional display module and bee calling organ module all are connected with single chip module. The single chip microcomputer module is used for receiving information input by the key module, controlling the nixie tube display module to display data according to the input information, controlling the calibration function module to display functions, and controlling the buzzer module to give an alarm. This intelligent timer based on singlechip, with low costs, circuit structure is simple, can keep the timing data last time, reduces user's work load.

Description

Intelligent timer based on single chip microcomputer

Technical Field

The utility model relates to a timer technical field, in particular to intelligence timer based on singlechip.

Background

The timer is a mechanical or electronic device for timing, the existence of the timer greatly changes the life of people, the timer is widely applied to family life and various public occasions, becomes an essential important device in the life of people, and even influences the development of high-tech electronic products.

The timer can be used for a controller and a detection system of industrial automatic control, an automatic screen locking function of a computer and a mobile phone, a timing key function of an air conditioner, delayed power failure of a washing machine and an electric cooker, delayed photographing and timed exposure functions of a camera, a timing key of a street lamp, flashing and timing of various marks of an automobile instrument panel, a water level timing alarm and the like, and the effects of reducing energy consumption waste and warning are achieved. The precision of the timer directly determines the quality of the electronic device and indirectly influences the life of people. With the development of single-chip microcomputers, timers are also developed towards high performance and diversification. For embedded operating systems, timers are the most essential and essential part of the foundation. However, the existing timer circuit has complex structure and high cost, and is unfavorable for the development of the timer.

Therefore, aiming at the defects of the prior art, the intelligent timer based on the single chip microcomputer is necessary to overcome the defects of the prior art.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to avoid prior art's weak point and provide an intelligent timer based on singlechip, it is accurate, with low costs and circuit structure simple to time.

The purpose of the utility model is realized through the following technical measures.

The intelligent timer based on the single chip microcomputer is provided with a single chip microcomputer module, a key module, a nixie tube display module, a circuit protection module, a power failure protection module, a calibration function display module and a buzzer module;

the key module, the nixie tube display module, the circuit protection module, the power failure protection module, the calibration function display module and the buzzer module are all connected with the single chip microcomputer module.

Preferably, the single chip microcomputer module is provided with a chip U1 with the model number of AT89C51, a capacitor C1, a capacitor C2, a capacitor C3, a resistor R6, a crystal oscillator X1, a reset key SR1, a reset key SR2 and a diode D6;

the pin 31 of the chip U1, one end of the capacitor C1, one end of the capacitor C2, one end of the capacitor C3, one end of the resistor R6, one end of the diode D6, one end of the reset key SR1 and one end of the reset key SR2 are all grounded, the other end of the capacitor C1 is connected to the pin 18 of the chip U1, the other end of the capacitor C2 is connected to the pin 19 of the chip U1, one end of the crystal oscillator X1 is connected to the pin 19 of the chip U1, the other end of the crystal oscillator X1 is connected to the pin 18 of the chip U1, the other end of the capacitor C3 is connected to the pin 9 of the chip U1, the other end of the resistor R6 is connected to the pin 9 of the chip U1, the other end of the diode D6 is connected to the pin 6 of the chip U1, the other end of the reset key SR1 is connected to the pin 9 of the chip U1, and the other end of the reset key SR2 is connected to the pin 16 of the chip U1.

Preferably, the key module is provided with a key K1, a key K2, a key K3, a key K4, a key K5 and a key K6, one end of the key K1 is connected to the 10 pin of the chip U1, one end of the key K2 is connected to the 11 pin of the chip U1, one end of the key K3 is connected to the 12 pin of the chip U1, one end of the key K4 is connected to the 13 pin of the chip U1, one end of the key K5 is connected to the 14 pin of the chip U1, one end of the key K6 is connected to the 15 pin of the chip U1, and the other ends of the key K1, the key K2, the key K3, the key K4, the key K5 and the key K6 are all grounded.

Preferably, the nixie tube display module is provided with a first common anode nixie tube and a second common anode nixie tube with the model number of 7SEG-MPX8-CA-RED, and chips U2 and U3 with the model number of 74LS 373;

the pin 3 of the chip U2 is connected with the pin 39 of the chip U1, the pin 4 of the chip U2 is connected with the pin 38 of the chip U1, the pin 7 of the chip U2 is connected with the pin 37 of the chip U1, the pin 8 of the chip U2 is connected with the pin 36 of the chip U1, the pin 13 of the chip U2 is connected with the pin 35 of the chip U1, the pin 14 of the chip U2 is connected with the pin 34 of the chip U1, the pin 17 of the chip U2 is connected with the pin 33 of the chip U1, the pin 18 of the chip U2 is connected with the pin 32 of the chip U1, the pin A of the first common anode nixie tube and the pin A of the second common anode nixie tube are both connected with the pin 2 of the chip U2, the pin B of the first common anode nixie tube and the pin B of the second common anode nixie tube are both connected with the pin 5 of the chip U2, the pin C of the first common anode nixie tube and the pin D of the second common anode nixie tube are both connected with the pin 2 of the chip U2, the pin E of the first common anode nixie tube and the pin E of the second common anode nixie tube are both connected with the pin 12 of the chip U2, the pin F of the first common anode nixie tube and the pin F of the second common anode nixie tube are both connected with the pin 15 of the chip U2, the pin G of the first common anode nixie tube and the pin G of the second common anode nixie tube are both connected with the pin 16 of the chip U2, and the pin DP of the first common anode nixie tube and the pin DP of the second common anode nixie tube are both connected with the pin 19 of the chip U2;

the 3 pin of the chip U3 is connected to the 21 pin of the chip U1, the 4 pin of the chip U3 is connected to the 22 pin of the chip U1, the 7 pin of the chip U3 is connected to the 23 pin of the chip U1, the 8 pin of the chip U3 is connected to the 24 pin of the chip U1, the 13 pin of the chip U3 is connected to the 25 pin of the chip U1, the 14 pin of the chip U3 is connected to the 26 pin of the chip U1, the 17 pin of the chip U3 is connected to the 27 pin of the chip U1, the 18 pin of the chip U3 is connected to the 28 pin of the chip U1, the 1 pin of the first common anode nixie tube is connected to the 2 pin of the chip U3, the 2 pin of the first common anode nixie tube is connected to the 5 pin of the chip U3, the 3 pin of the first common anode nixie tube is connected to the 6 pin of the chip U3, the 4 pin of the first common anode nixie tube is connected to the 9 pin of the chip U3, the 1 pin of the second common anode nixie tube is connected to the 12 pin of the chip U3, the second pin of the chip U3 is connected to the chip U3, the 4 pins of the second common anode nixie tube are connected to the 19 pins of the chip U3.

Preferably, the circuit protection module is provided with a resistor RP1 with a model number of RESPACK-8, a pin 1 of the resistor RP1 is grounded, a pin 2 of the resistor RP1 is connected with a pin 32 of the chip U1, a pin 3 of the resistor RP1 is connected with a pin 33 of the chip U1, a pin 4 of the resistor RP1 is connected with a pin 34 of the chip U1, a pin 5 of the resistor RP1 is connected with a pin 35 of the chip U1, a pin 6 of the resistor RP1 is connected with a pin 36 of the chip U1, a pin 7 of the resistor RP1 is connected with a pin 37 of the chip U1, a pin 8 of the resistor RP1 is connected with a pin 38 of the chip U1, and a pin 9 of the resistor RP1 is connected with a pin 39 of the chip U1.

Preferably, the power-down protection module is provided with a chip U4, a resistor R9 and a resistor R10 of which the model is AT24C02, one end of the resistor R9 and one end of the resistor R10 are all grounded, the other end of the resistor R9 and the other end of the resistor R10 are all connected with 5 pins of the chip U4, 6 pins of the chip U4 are connected with 7 pins of the chip U1, 6 pins of the chip U4 are connected with 7 pins of the chip U1, 5 pins of the chip U4 are connected with 8 pins of the chip U1, and 1 pin, 2 pins, 3 pins and 7 pins of the chip U4 are all grounded.

Preferably, the calibration function display module is provided with a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a diode D1, a diode D2, a diode D3, a diode D4 and a diode D5;

one end of the resistor R1, one end of the resistor R2, one end of the resistor R3, one end of the resistor R4 and one end of the resistor R5 are all grounded, the other end of the resistor R1 is connected with one end of the diode D1, the other end of the resistor R2 is connected with one end of the diode D2, the other end of the resistor R3 is connected with one end of the diode D3, the other end of the resistor R4 is connected with one end of the diode D4, the other end of the resistor R5 is connected with one end of the diode D5, the other end of the diode D1 is connected with a pin 1 of the chip U1, the other end of the diode D2 is connected with a pin 2 of the chip U1, the other end of the diode D3 is connected with a pin 3 of the chip U1, the other end of the diode D4 is connected with a pin 4 of the chip U1, and the other end of the diode D5 is connected with a pin 5 of the chip U1.

Preferably, the buzzer module is provided with a resistor R7, a resistor R8, a triode Q1 and a buzzer LS 1;

one end of the resistor R7 is connected with a pin 17 of the chip U4, the other end of the resistor R7 is connected with a pole B of the triode Q1, one end of the resistor R8 is grounded, the other end of the resistor R8 is connected with a pole E of the triode Q1, one end of the buzzer LS1 is connected with a pole C of the triode Q1, and the other end of the buzzer LS1 is grounded.

The utility model discloses an intelligence timer based on singlechip is provided with single chip module, button module, charactron display module, circuit protection module, power down protection module, calibration function display module and bee calling organ module, and button module, charactron display module, circuit protection module, power down protection module, calibration function display module and bee calling organ module all are connected with single chip module. The singlechip module provides basic functions including generating periodic signals and providing a reset function to enable the singlechip core control chip U1 to normally work, receives external signals through an instruction program in the singlechip module for timing and outputs corresponding data to the density display module for data display, and simultaneously the singlechip module controls the buzzer module to enable the buzzer to work when the timing is finished. The circuit protection module is used for protecting the circuit of the whole intelligent timer. The key module is used for inputting an external signal to the single chip microcomputer module, and the calibration function display module is used for displaying the working state of the single chip microcomputer module at the moment. The power-down protection module is used for clock timing data and data addresses, so that the timing data of the last clock timer is still reserved when the single chip microcomputer is started next time. The utility model discloses an intelligent timer based on singlechip, circuit structure is simple, and is regularly accurate, and can remain the timing data of the clock timer last time.

Drawings

The present invention will be further described with reference to the accompanying drawings, but the contents in the drawings do not constitute any limitation to the present invention.

Fig. 1 is the utility model relates to an each module connection structure sketch map of intelligent timer based on singlechip.

Fig. 2 is the utility model relates to an intelligence timer single chip module circuit diagram based on singlechip.

Fig. 3 is the utility model relates to an intelligence timer button module circuit diagram based on singlechip.

Fig. 4 is the utility model relates to an intelligence timer charactron display module circuit diagram based on singlechip.

Fig. 5 is the utility model relates to an intelligence timer circuit protection module circuit diagram based on singlechip.

Fig. 6 is the utility model relates to an intelligence timer power down protection module circuit diagram based on singlechip.

Fig. 7 is the utility model relates to an intelligence timer calibration function display module circuit diagram based on singlechip.

Figure 8 is the utility model relates to an intelligence timer and buzzer module circuit diagram based on singlechip.

In fig. 1 to 8, there are included:

the device comprises a singlechip module 100, a key module 200, a nixie tube display module 300, a circuit protection module 400, a power failure protection module 500, a calibration function display module 600 and a buzzer module 700.

Detailed Description

The present invention will be further illustrated with reference to the following examples.

Example 1.

An intelligent timer based on a single chip microcomputer is provided with a single chip microcomputer module 100, a key module 200, a nixie tube display module 300, a circuit protection module 400, a power down protection module 500, a calibration function display module 600 and a buzzer module 700, wherein the key module 200, the nixie tube display module 300, the circuit protection module 400, the power down protection module 500, the calibration function display module 600 and the buzzer module 700 are all connected with the single chip microcomputer module 100, as shown in fig. 1. The single chip microcomputer module 100 can cooperatively control other modules to work together, can receive external signals and control the nixie tube to display data, and when the data reaches a timing moment, alarms through the buzzer to realize timing reminding. And the power down protection module 500 can enable the timing data before the shutdown of the single chip microcomputer.

As shown in fig. 2, the single chip microcomputer module 100 is provided with a chip U1 with a model number of AT89C51, a capacitor C1, a capacitor C2, a capacitor C3, a resistor R6, a crystal oscillator X1, a reset key SR1, a reset key SR2 and a diode D6. The pin 31 of the chip U1, one end of the capacitor C1, one end of the capacitor C2, one end of the capacitor C3, one end of the resistor R6, one end of the diode D6, one end of the reset key SR1 and one end of the reset key SR2 are all grounded, the other end of the capacitor C1 is connected to the pin 18 of the chip U1, the other end of the capacitor C2 is connected to the pin 19 of the chip U1, one end of the crystal oscillator X1 is connected to the pin 19 of the chip U1, the other end of the crystal oscillator X1 is connected to the pin 18 of the chip U1, the other end of the capacitor C3 is connected to the pin 9 of the chip U1, the other end of the resistor R6 is connected to the pin 9 of the chip U1, the other end of the diode D6 is connected to the pin 6 of the chip U1, the other end of the reset key SR1 is connected to the pin 9 of the chip U1, and the other end of the reset key SR2 is connected to the pin 16 of the chip U1. The single chip microcomputer module 100 is used for generating a periodic signal and providing basic functions including a reset function so that the chip U1 can work normally. It should be noted that the model of the chip U1 is not limited to AT89C51 in this embodiment, and may be STC89C52 or the like.

As shown in fig. 3, the key module 200 is provided with a key K1, a key K2, a key K3, a key K4, a key K5 and a key K6, one end of the key K1 is connected to the 10 pin of the chip U1, one end of the key K2 is connected to the 11 pin of the chip U1, one end of the key K3 is connected to the 12 pin of the chip U1, one end of the key K4 is connected to the 13 pin of the chip U1, one end of the key K5 is connected to the 14 pin of the chip U1, one end of the key K6 is connected to the 15 pin of the chip U1, and the other end of the key K1, the other end of the key K2, the other end of the key K3, the other end of the key K4, the other end of the key K5 and the other end of the key K6 are all grounded. The key module 200 adopts an independent key structure, and is a structural scheme that keys and I/O ports of the chip U1 are directly connected to form a key circuit, wherein one key is correspondingly connected with one I/O port, and the keys are opposite to each other, so that the state of the I/O ports cannot be influenced by key operation, and a stable effect is achieved. The scheme can make the circuit structure more concise and flexible. In this embodiment, the key function allocation is specifically as follows: the key K1 is a function selection key, and specifically comprises three function selections of a clock timer, an alarm clock and a timer, the key K2 is a clock timer calibration key, when the calibration key is pressed down, the calibration time is divided into minutes or seconds, the key K3 is a self-increasing key, the key K4 is a self-decreasing key, the key K5 is a timer start/pause key, and the key K6 is a timer zero setting key. It should be noted that the manner of assigning the functions of the keys in the present embodiment is not limited to this.

As shown in fig. 4, the nixie tube display module 300 is provided with a first common anode nixie tube and a second common anode nixie tube with model number 7SEG-MPX8-CA-RED, and chips U2 and U3 with model number 74LS 373. The common anode nixie tube with the model number of 7SEG-MPX8-CA-RED, the ABCDEFG DP at the left side of the common anode nixie tube is a segment selection signal which represents the introduction connected with the I/O port of an LED nixie tube display. And the right side 1234 is a bit selection signal, which controls the lighting of the corresponding position of the nixie tube. The LED nixie tube is used as the display module during data display, the program of the LED nixie tube is simple and direct, the number of peripheral devices is large, wiring is simple and clear, the service life is long, and the environment-friendly material is not easy to cause pollution. And the LED nixie tube is driven by direct current, so that the problem of flash frequency is solved. The price of the LED nixie tube is cheaper, and the cost can be saved. Chips U2 and U3 of type 74LS373 are implemented as digitally controlled buffers that not only boost current, but also improve hysteresis due to interference inputs, amplify current, and boost drive.

Wherein, the pin 3 of the chip U2 is connected to the pin 39 of the chip U1, the pin 4 of the chip U2 is connected to the pin 38 of the chip U1, the pin 7 of the chip U2 is connected to the pin 37 of the chip U1, the pin 8 of the chip U2 is connected to the pin 36 of the chip U1, the pin 13 of the chip U2 is connected to the pin 35 of the chip U1, the pin 14 of the chip U2 is connected to the pin 34 of the chip U1, the pin 17 of the chip U2 is connected to the pin 33 of the chip U1, the pin 18 of the chip U2 is connected to the pin 32 of the chip U1, the pin A of the first common anode nixie tube and the pin A of the second common anode nixie tube are both connected to the pin 2 of the chip U2, the pin B of the first common anode nixie tube and the pin B of the second common anode nixie tube are both connected to the pin 5 of the chip U2, the pin C of the first common anode nixie tube and the pin D9 of the second common anode nixie tube 2, the pin E of the first common anode nixie tube and the pin E of the second common anode nixie tube are both connected with the pin 12 of the chip U2, the pin F of the first common anode nixie tube and the pin F of the second common anode nixie tube are both connected with the pin 15 of the chip U2, the pin G of the first common anode nixie tube and the pin G of the second common anode nixie tube are both connected with the pin 16 of the chip U2, and the pin DP of the first common anode nixie tube and the pin DP of the second common anode nixie tube are both connected with the pin 19 of the chip U2. Pin 3 of chip U3 is connected to pin 21 of chip U1, pin 4 of chip U3 is connected to pin 22 of chip U1, pin 7 of chip U3 is connected to pin 23 of chip U1, pin 8 of chip U3 is connected to pin 24 of chip U1, pin 13 of chip U3 is connected to pin 25 of chip U1, pin 14 of chip U3 is connected to pin 26 of chip U1, pin 17 of chip U3 is connected to pin 27 of chip U1, pin 18 of chip U3 is connected to pin 28 of chip U1, pin 1 of first common anode nixie tube is connected to pin 2 of chip U3, pin 2 of first common anode nixie tube is connected to pin 5 of chip U3, pin 3 of first common anode nixie tube is connected to pin 6 of chip U3, pin 4 of first common anode nixie tube is connected to pin 9 of chip U3, pin 1 of second common anode nixie tube is connected to pin 12 of chip U3, pin 2 of second common anode nixie tube is connected to pin 3 of chip U3, the 4 pins of the second common anode nixie tube are connected to the 19 pins of the chip U3.

As shown in fig. 5, the circuit protection module 400 is provided with a resistor RP1 of a model number RESPACK-8, a pin 1 of the resistor RP1 is grounded, a pin 2 of the resistor RP1 is connected with a pin 32 of the chip U1, a pin 3 of the resistor RP1 is connected with a pin 33 of the chip U1, a pin 4 of the resistor RP1 is connected with a pin 34 of the chip U1, a pin 5 of the resistor RP1 is connected with a pin 35 of the chip U1, a pin 6 of the resistor RP1 is connected with a pin 36 of the chip U1, a pin 7 of the resistor RP1 is connected with a pin 37 of the chip U1, a pin 8 of the resistor RP1 is connected with a pin 38 of the chip U1, and a pin 9 of the resistor RP1 is connected with a pin 39 of the chip U1. The resistor RP1 is a pull-up resistor and is mainly used for protecting the circuit.

As shown in fig. 6, the power down protection module 500 is provided with a chip U4, a resistor R9 and a resistor R10 of which the model is AT24C02, one end of the resistor R9 and one end of the resistor R10 are all grounded, the other end of the resistor R9 and the other end of the resistor R10 are both connected to the 5-pin of the chip U4, the 6-pin of the chip U4 is connected to the 7-pin of the chip U1, the 6-pin of the chip U4 is connected to the 7-pin of the chip U1, the 5-pin of the chip U4 is connected to the 8-pin of the chip U1, and the 1-pin, 2-pin, 3-pin and 7-pin of the chip U4 are all grounded. The chip U4 can write data into the single chip microcomputer 100 when the single chip microcomputer 100 is powered off, and then return the data to the single chip microcomputer 100 when the single chip microcomputer 100 is powered on next time, so as to ensure that the data is not lost.

As shown in fig. 7, the calibration function display module 600 is provided with a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a diode D1, a diode D2, a diode D3, a diode D4, and a diode D5. One end of a resistor R1, one end of a resistor R2, one end of a resistor R3, one end of a resistor R4 and one end of a resistor R5 are all grounded, the other end of the resistor R1 is connected with one end of a diode D1, the other end of the resistor R2 is connected with one end of a diode D2, the other end of a resistor R3 is connected with one end of a diode D3, the other end of a resistor R4 is connected with one end of a diode D4, the other end of a resistor R5 is connected with one end of a diode D5, the other end of a diode D1 is connected with a pin 1 of a chip U1, the other end of a diode D2 is connected with a pin 2 of a chip U1, the other end of a diode D3 is connected with a pin 3 of a chip U1, the other end of a diode D4 is connected with a pin 4 of a chip U1, and the other end of a diode D5 is connected with a pin 5 of a chip U1. In this embodiment, the diodes D1-D5 sequentially represent the time, minute and second positions of the calibration function and the time and minute positions of the alarm clock setting function, and the brightness of the diodes is controlled by the single chip microcomputer module 100.

As shown in fig. 8, the buzzer module 700 is provided with a resistor R7, a resistor R8, a transistor Q1, and a buzzer LS 1. One end of a resistor R7 is connected with a pin 17 of a chip U4, the other end of the resistor R7 is connected with a pole B of a triode Q1, one end of a resistor R8 is grounded, the other end of a resistor R8 is connected with a pole E of a triode Q1, one end of a buzzer LS1 is connected with a pole C of the triode Q1, and the other end of the buzzer LS1 is grounded.

The working principle of the intelligent timer based on the single chip microcomputer of the embodiment is as follows: according to the required function information, timing information and the like, a proper K1-K5 key in the key module 200 is selected to be pressed, and the key module 200 sends the function information, the timing information and the like to the singlechip module 100 through a P3.0-3.5 interface of the chip U4. The single chip module 100 recognizes the corresponding function information, then controls five LED lamps of the calibration function display module 600 to display the corresponding function information with different lighting information through the P1.0-1.4 interface of the chip U1, and sends corresponding timing data to the nixie tube display module 300 to display through the P0.0-0.7 interface and the P2.0-2.7 interface of the chip U1, and when the timing moment is reached, the P3.1 interface of the chip U1 sends a signal to the buzzer module 700 to control the buzzer to work. Meanwhile, the singlechip module 100 sends the timing data information and the data address to the power failure protection module 500 for storage through P1.6 and P1.7 interfaces of the chip U1, and the intelligent timer still displays the stored timing data when being started next time without secondary input of a user.

The intelligent timer based on the single chip microcomputer is simple in circuit structure and low in cost, timing data of the timer before shutdown can be reserved and displayed when the timer is started next time, secondary input is not needed by a user, and burden of the user is relieved.

Example 2.

The utility model provides an intelligent timer based on singlechip, other characteristics are the same with embodiment 1, the difference lies in: in this embodiment, parameters of the capacitor C1, the capacitor C2 and the capacitor C3 are 30pF, 30pF and 10pF, parameters of the resistor R6, the resistor R9 and the resistor R10 are all 10K Ω, parameters of the resistors R1, R2, R3, R4 and R5 are all 200 Ω, parameters of the resistor R8 are 100 Ω, and parameters of the resistor R7 are 1K Ω, respectively. In the present embodiment, each electronic component is a commercially available electronic component, and the parameters of each electronic component are not limited to the above parameters, and may be other parameters. This intelligent timer based on singlechip, with low costs, and each electronic components is simple components and parts, and circuit connection is simple.

It should be finally noted that the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the scope of the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced with equivalents without departing from the spirit and scope of the technical solutions of the present invention.

Claims (8)

1. The utility model provides an intelligent timer based on singlechip which characterized in that: the device is provided with a singlechip module, a key module, a nixie tube display module, a circuit protection module, a power-down protection module, a calibration function display module and a buzzer module;

the key module, the nixie tube display module, the circuit protection module, the power failure protection module, the calibration function display module and the buzzer module are all connected with the single chip microcomputer module.

2. The intelligent timer based on the single chip microcomputer according to claim 1, wherein: the single chip microcomputer module is provided with a chip U1 with the model number of AT89C51, a capacitor C1, a capacitor C2, a capacitor C3, a resistor R6, a crystal oscillator X1, a reset key SR1, a reset key SR2 and a diode D6;

the pin 31 of the chip U1, one end of the capacitor C1, one end of the capacitor C2, one end of the capacitor C3, one end of the resistor R6, one end of the diode D6, one end of the reset key SR1 and one end of the reset key SR2 are all grounded, the other end of the capacitor C1 is connected to the pin 18 of the chip U1, the other end of the capacitor C2 is connected to the pin 19 of the chip U1, one end of the crystal oscillator X1 is connected to the pin 19 of the chip U1, the other end of the crystal oscillator X1 is connected to the pin 18 of the chip U1, the other end of the capacitor C3 is connected to the pin 9 of the chip U1, the other end of the resistor R6 is connected to the pin 9 of the chip U1, the other end of the diode D6 is connected to the pin 6 of the chip U1, the other end of the reset key SR1 is connected to the pin 9 of the chip U1, and the other end of the reset key SR2 is connected to the pin 16 of the chip U1.

3. The intelligent timer based on the single chip microcomputer according to claim 1, wherein: the key module is provided with a key K1, a key K2, a key K3, a key K4, a key K5 and a key K6, one end of the key K1 is connected with the 10 pin of the chip U1, one end of the key K2 is connected with the 11 pin of the chip U1, one end of the key K3 is connected with the 12 pin of the chip U1, one end of the key K4 is connected with the 13 pin of the chip U1, one end of the key K5 is connected with the 14 pin of the chip U1, one end of the key K6 is connected with the 15 pin of the chip U1, and the other end of the key K1, the other end of the key K2, the other end of the key K3, the other end of the key K4, the other end of the key K5 and the other end of the key K6 are all grounded.

4. The intelligent timer based on the single chip microcomputer according to claim 1, wherein: the nixie tube display module is provided with a first common anode nixie tube and a second common anode nixie tube with the model number of 7SEG-MPX8-CA-RED, and chips U2 and U3 with the model number of 74LS 373;

the pin 3 of the chip U2 is connected with the pin 39 of the chip U1, the pin 4 of the chip U2 is connected with the pin 38 of the chip U1, the pin 7 of the chip U2 is connected with the pin 37 of the chip U1, the pin 8 of the chip U2 is connected with the pin 36 of the chip U1, the pin 13 of the chip U2 is connected with the pin 35 of the chip U1, the pin 14 of the chip U2 is connected with the pin 34 of the chip U1, the pin 17 of the chip U2 is connected with the pin 33 of the chip U1, the pin 18 of the chip U2 is connected with the pin 32 of the chip U1, the pin A of the first common anode nixie tube and the pin A of the second common anode nixie tube are both connected with the pin 2 of the chip U2, the pin B of the first common anode nixie tube and the pin B of the second common anode nixie tube are both connected with the pin 5 of the chip U2, the pin C of the first common anode nixie tube and the pin D of the second common anode nixie tube are both connected with the pin 2 of the chip U2, the pin E of the first common anode nixie tube and the pin E of the second common anode nixie tube are both connected with the pin 12 of the chip U2, the pin F of the first common anode nixie tube and the pin F of the second common anode nixie tube are both connected with the pin 15 of the chip U2, the pin G of the first common anode nixie tube and the pin G of the second common anode nixie tube are both connected with the pin 16 of the chip U2, and the pin DP of the first common anode nixie tube and the pin DP of the second common anode nixie tube are both connected with the pin 19 of the chip U2;

the 3 pin of the chip U3 is connected to the 21 pin of the chip U1, the 4 pin of the chip U3 is connected to the 22 pin of the chip U1, the 7 pin of the chip U3 is connected to the 23 pin of the chip U1, the 8 pin of the chip U3 is connected to the 24 pin of the chip U1, the 13 pin of the chip U3 is connected to the 25 pin of the chip U1, the 14 pin of the chip U3 is connected to the 26 pin of the chip U1, the 17 pin of the chip U3 is connected to the 27 pin of the chip U1, the 18 pin of the chip U3 is connected to the 28 pin of the chip U1, the 1 pin of the first common anode nixie tube is connected to the 2 pin of the chip U3, the 2 pin of the first common anode nixie tube is connected to the 5 pin of the chip U3, the 3 pin of the first common anode nixie tube is connected to the 6 pin of the chip U3, the 4 pin of the first common anode nixie tube is connected to the 9 pin of the chip U3, the 1 pin of the second common anode nixie tube is connected to the 12 pin of the chip U3, the second pin of the chip U3 is connected to the chip U3, the 4 pins of the second common anode nixie tube are connected to the 19 pins of the chip U3.

5. The intelligent timer based on the single chip microcomputer according to claim 1, wherein: the circuit protection module is provided with a resistor RP1 with the model number of RESPACK-8, a pin 1 of the resistor RP1 is grounded, a pin 2 of the resistor RP1 is connected with a pin 32 of a chip U1, a pin 3 of the resistor RP1 is connected with a pin 33 of the chip U1, a pin 4 of the resistor RP1 is connected with a pin 34 of the chip U1, a pin 5 of the resistor RP1 is connected with a pin 35 of the chip U1, a pin 6 of the resistor RP1 is connected with a pin 36 of the chip U1, a pin 7 of the resistor RP1 is connected with a pin 37 of the chip U1, a pin 8 of the resistor RP1 is connected with a pin 38 of the chip U1, and a pin 9 of the resistor RP1 is connected with a pin 39 of the chip U1.

6. The intelligent timer based on the single chip microcomputer according to claim 1, wherein: the power-down protection module is provided with a chip U4, a resistor R9 and a resistor R10 of which the models are AT24C02, one end of the resistor R9 and one end of the resistor R10 are all grounded, the other end of the resistor R9 and the other end of the resistor R10 are all connected with 5 pins of the chip U4, 6 pins of the chip U4 are connected with 7 pins of the chip U1, 6 pins of the chip U4 are connected with 7 pins of the chip U1, 5 pins of the chip U4 are connected with 8 pins of the chip U1, and 1 pin, 2 pins, 3 pins and 7 pins of the chip U4 are all grounded.

7. The intelligent timer based on the single chip microcomputer according to claim 1, wherein: the calibration function display module is provided with a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a diode D1, a diode D2, a diode D3, a diode D4 and a diode D5;

one end of the resistor R1, one end of the resistor R2, one end of the resistor R3, one end of the resistor R4 and one end of the resistor R5 are all grounded, the other end of the resistor R1 is connected with one end of the diode D1, the other end of the resistor R2 is connected with one end of the diode D2, the other end of the resistor R3 is connected with one end of the diode D3, the other end of the resistor R4 is connected with one end of the diode D4, the other end of the resistor R5 is connected with one end of the diode D5, the other end of the diode D1 is connected with a pin 1 of the chip U1, the other end of the diode D2 is connected with a pin 2 of the chip U1, the other end of the diode D3 is connected with a pin 3 of the chip U1, the other end of the diode D4 is connected with a pin 4 of the chip U1, and the other end of the diode D5 is connected with a pin 5 of the chip U1.

8. The intelligent timer based on the single chip microcomputer according to claim 1, wherein: the buzzer module is provided with a resistor R7, a resistor R8, a triode Q1 and a buzzer LS 1;

one end of the resistor R7 is connected with a pin 17 of the chip U4, the other end of the resistor R7 is connected with a pole B of the triode Q1, one end of the resistor R8 is grounded, the other end of the resistor R8 is connected with a pole E of the triode Q1, one end of the buzzer LS1 is connected with a pole C of the triode Q1, and the other end of the buzzer LS1 is grounded.

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